From d13c70c3c8f61d59791f3adf9a8d8ece53833a42 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 14 Jan 2025 10:03:54 -0800 Subject: [PATCH] Wire rename --- passes/opt/opt_balance_tree.cc | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 653540556..630d88563 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -405,10 +405,16 @@ struct OptBalanceTreeWorker { for (auto c : chain_start_cells) { vector chain = create_chain(c); if (process_chain(chain)) { - // Rename cells for formal check to pass as cells signals have changed functionalities post rotation + // Rename cells and wires for formal check to pass as cells signals have changed functionalities post rotation for (Cell *cell : chain) { - module->rename(cell, NEW_ID2_SUFFIX("mid_cell")); - log("Renaming cell %s \n", cell->name.c_str()); + module->rename(cell, NEW_ID2_SUFFIX("rot_cell")); + } + for (Cell *cell : chain) { + SigSpec y_sig = sigmap(cell->getPort(ID::Y)); + Wire *wire = y_sig.as_wire(); + if (wire && !wire->port_input && !wire->port_output) { + module->rename(y_sig.as_wire(), NEW_ID2_SUFFIX("rot_wire")); + } } } cell_count[cell_type] += GetSize(chain);