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https://github.com/YosysHQ/yosys
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csa_tree: move to techmap
This commit is contained in:
Emil J. Tywoniak
nella
parent
eb477b2d56
commit
d0e381506c
3 changed files with 1 additions and 1 deletions
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@ -55,6 +55,7 @@ OBJS += passes/techmap/extractinv.o
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OBJS += passes/techmap/cellmatch.o
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OBJS += passes/techmap/clockgate.o
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OBJS += passes/techmap/constmap.o
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OBJS += passes/techmap/csa_tree.o
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endif
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ifeq ($(DISABLE_SPAWN),0)
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495
passes/techmap/csa_tree.cc
Normal file
495
passes/techmap/csa_tree.cc
Normal file
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@ -0,0 +1,495 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/macc.h"
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#include <queue>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Operand {
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SigSpec sig;
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bool is_signed;
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bool negate;
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};
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struct Traversal
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{
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SigMap sigmap;
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dict<SigBit, pool<Cell*>> bit_consumers;
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dict<SigBit, int> fanout;
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Traversal(Module* module) : sigmap(module) {
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for (auto cell : module->cells())
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for (auto& conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_consumers[bit].insert(cell);
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for (auto& pair : bit_consumers)
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fanout[pair.first] = pair.second.size();
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for (auto wire : module->wires())
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if (wire->port_output)
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for (auto bit : sigmap(SigSpec(wire)))
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fanout[bit]++;
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}
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};
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struct Cells {
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pool<Cell*> addsub;
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pool<Cell*> alu;
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pool<Cell*> macc;
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static bool is_addsub(Cell* cell)
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{
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return cell->type == ID($add) || cell->type == ID($sub);
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}
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static bool is_alu(Cell* cell)
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{
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return cell->type == ID($alu);
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}
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static bool is_macc(Cell* cell)
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{
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return cell->type == ID($macc) || cell->type == ID($macc_v2);
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}
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bool empty() {
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return addsub.empty() && alu.empty() && macc.empty();
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}
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Cells(Module* module) {
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for (auto cell : module->cells()) {
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if (is_addsub(cell))
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addsub.insert(cell);
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else if (is_alu(cell))
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alu.insert(cell);
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else if (is_macc(cell))
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macc.insert(cell);
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}
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}
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};
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struct AluInfo {
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Cells& cells;
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Traversal& traversal;
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bool is_subtract(Cell* cell)
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{
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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return GetSize(bi) == 1 && bi[0] == State::S1 && GetSize(ci) == 1 && ci[0] == State::S1;
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}
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bool is_add(Cell* cell)
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{
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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return GetSize(bi) == 1 && bi[0] == State::S0 && GetSize(ci) == 1 && ci[0] == State::S0;
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}
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bool is_chainable(Cell* cell)
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{
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if (!(is_add(cell) || is_subtract(cell)))
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return false;
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for (auto bit : traversal.sigmap(cell->getPort(ID::X)))
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if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
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return false;
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for (auto bit : traversal.sigmap(cell->getPort(ID::CO)))
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if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
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return false;
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return true;
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}
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};
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struct Rewriter
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{
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Module* module;
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Cells& cells;
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Traversal traversal;
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AluInfo alu_info;
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Rewriter(Module* module, Cells& cells) : module(module), cells(cells), traversal(module), alu_info{cells, traversal} {}
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Cell* sole_chainable_consumer(SigSpec sig, const pool<Cell*>& candidates)
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{
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Cell* consumer = nullptr;
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for (auto bit : sig) {
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if (!traversal.fanout.count(bit) || traversal.fanout[bit] != 1)
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return nullptr;
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if (!traversal.bit_consumers.count(bit) || traversal.bit_consumers[bit].size() != 1)
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return nullptr;
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Cell* c = *traversal.bit_consumers[bit].begin();
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if (!candidates.count(c))
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return nullptr;
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if (consumer == nullptr)
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consumer = c;
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else if (consumer != c)
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return nullptr;
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}
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return consumer;
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}
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dict<Cell*, Cell*> find_parents(const pool<Cell*>& candidates)
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{
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dict<Cell*, Cell*> parent_of;
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for (auto cell : candidates) {
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Cell* consumer = sole_chainable_consumer(
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traversal.sigmap(cell->getPort(ID::Y)), candidates);
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if (consumer && consumer != cell)
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parent_of[cell] = consumer;
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}
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return parent_of;
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}
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pool<Cell*> collect_chain(Cell* root, const dict<Cell*, pool<Cell*>>& children_of)
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{
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pool<Cell*> chain;
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std::queue<Cell*> q;
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q.push(root);
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while (!q.empty()) {
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Cell* cur = q.front();
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q.pop();
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if (!chain.insert(cur).second)
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continue;
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auto it = children_of.find(cur);
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if (it != children_of.end())
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for (auto child : it->second)
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q.push(child);
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}
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return chain;
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}
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pool<SigBit> internal_bits(const pool<Cell*>& chain)
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{
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pool<SigBit> bits;
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for (auto cell : chain)
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for (auto bit : traversal.sigmap(cell->getPort(ID::Y)))
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bits.insert(bit);
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return bits;
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}
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static bool overlaps(SigSpec sig, const pool<SigBit>& bits)
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{
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for (auto bit : sig)
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if (bits.count(bit))
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return true;
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return false;
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}
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bool feeds_subtracted_port(Cell* child, Cell* parent)
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{
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bool parent_subtracts;
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if (parent->type == ID($sub))
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parent_subtracts = true;
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else if (cells.is_alu(parent))
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parent_subtracts = alu_info.is_subtract(parent);
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else
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return false;
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if (!parent_subtracts)
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return false;
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SigSpec child_y = traversal.sigmap(child->getPort(ID::Y));
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SigSpec parent_b = traversal.sigmap(parent->getPort(ID::B));
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for (auto bit : child_y)
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for (auto pbit : parent_b)
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if (bit == pbit)
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return true;
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return false;
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}
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std::vector<Operand> extract_chain_operands(
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const pool<Cell*>& chain,
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Cell* root,
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const dict<Cell*, Cell*>& parent_of,
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int& correction
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) {
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pool<SigBit> chain_bits = internal_bits(chain);
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dict<Cell*, bool> negated;
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negated[root] = false;
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{
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std::queue<Cell*> q;
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q.push(root);
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while (!q.empty()) {
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Cell* cur = q.front(); q.pop();
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for (auto cell : chain) {
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if (!parent_of.count(cell) || parent_of.at(cell) != cur)
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continue;
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if (negated.count(cell))
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continue;
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negated[cell] = negated[cur] ^ feeds_subtracted_port(cell, cur);
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q.push(cell);
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}
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}
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}
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std::vector<Operand> operands;
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correction = 0;
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for (auto cell : chain) {
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bool cell_neg;
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if (negated.count(cell))
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cell_neg = negated[cell];
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else
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cell_neg = false;
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SigSpec a = traversal.sigmap(cell->getPort(ID::A));
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SigSpec b = traversal.sigmap(cell->getPort(ID::B));
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bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
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if (!overlaps(a, chain_bits)) {
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bool neg = cell_neg;
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operands.push_back({a, a_signed, neg});
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if (neg) correction++;
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}
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if (!overlaps(b, chain_bits)) {
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bool neg = cell_neg ^ b_sub;
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operands.push_back({b, b_signed, neg});
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if (neg) correction++;
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}
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}
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return operands;
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}
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bool extract_macc_operands(Cell* cell, std::vector<Operand>& operands, int& correction)
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{
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Macc macc(cell);
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correction = 0;
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for (auto& term : macc.terms) {
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// Bail on multiplication
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if (GetSize(term.in_b) != 0)
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return false;
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operands.push_back({term.in_a, term.is_signed, term.do_subtract});
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if (term.do_subtract)
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correction++;
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}
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return true;
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}
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SigSpec extend_operand(SigSpec sig, bool is_signed, int width)
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{
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if (GetSize(sig) < width) {
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SigBit pad;
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if (is_signed && GetSize(sig) > 0)
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pad = sig[GetSize(sig) - 1];
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else
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pad = State::S0;
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sig.append(SigSpec(pad, width - GetSize(sig)));
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}
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if (GetSize(sig) > width)
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sig = sig.extract(0, width);
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return sig;
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}
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std::pair<SigSpec, SigSpec> emit_fa(SigSpec a, SigSpec b, SigSpec c, int width)
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{
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec cout = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout, sum);
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SigSpec carry;
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carry.append(State::S0);
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carry.append(cout.extract(0, width - 1));
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return {sum, carry};
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}
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struct DepthSig {
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SigSpec sig;
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int depth;
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};
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std::pair<SigSpec, SigSpec> reduce_wallace(std::vector<SigSpec>& sigs, int width, int& fa_count)
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{
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std::vector<DepthSig> ops;
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ops.reserve(sigs.size());
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for (auto& s : sigs)
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ops.push_back({s, 0});
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fa_count = 0;
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for (int level = 0; ops.size() > 2; level++) {
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log_assert(level <= 100);
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std::vector<DepthSig> ready, waiting;
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for (auto& op : ops) {
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if (op.depth <= level)
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ready.push_back(op);
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else
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waiting.push_back(op);
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}
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if (ready.size() < 3) continue;
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std::vector<DepthSig> next;
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size_t i = 0;
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while (i + 2 < ready.size()) {
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auto [sum, carry] = emit_fa(ready[i].sig, ready[i + 1].sig, ready[i + 2].sig, width);
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int d = std::max({ready[i].depth, ready[i + 1].depth,ready[i + 2].depth}) + 1;
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next.push_back({sum, d});
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next.push_back({carry, d});
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fa_count++;
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i += 3;
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}
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for (; i < ready.size(); i++)
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next.push_back(ready[i]);
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for (auto& op : waiting)
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next.push_back(op);
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ops = std::move(next);
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}
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log_assert(ops.size() == 2);
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log(" Tree depth: %d FA levels + 1 final add\n",
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std::max(ops[0].depth, ops[1].depth));
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return {ops[0].sig, ops[1].sig};
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}
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void replace_with_csa_tree(
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std::vector<Operand>& operands,
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SigSpec result_y,
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int correction,
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const char* desc
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) {
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int width = GetSize(result_y);
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std::vector<SigSpec> extended;
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extended.reserve(operands.size() + 1);
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for (auto& op : operands) {
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SigSpec s = extend_operand(op.sig, op.is_signed, width);
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if (op.negate)
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s = module->Not(NEW_ID, s);
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extended.push_back(s);
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}
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if (correction > 0)
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extended.push_back(SigSpec(correction, width));
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int fa_count;
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auto [a, b] = reduce_wallace(extended, width, fa_count);
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log(" %s -> %d $fa + 1 $add (%d operands, module %s)\n",
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desc, fa_count, (int)operands.size(), log_id(module));
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// Emit final add
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module->addAdd(NEW_ID, a, b, result_y, false);
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}
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void process_chains()
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{
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pool<Cell*> candidates;
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for (auto cell : cells.addsub)
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candidates.insert(cell);
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for (auto cell : cells.alu)
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if (alu_info.is_chainable(cell))
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candidates.insert(cell);
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if (candidates.empty())
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return;
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auto parent_of = find_parents(candidates);
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dict<Cell*, pool<Cell*>> children_of;
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pool<Cell*> has_parent;
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for (auto& [child, parent] : parent_of) {
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children_of[parent].insert(child);
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has_parent.insert(child);
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}
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pool<Cell*> processed;
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for (auto root : candidates) {
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if (has_parent.count(root) || processed.count(root))
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continue; // Not a tree root
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pool<Cell*> chain = collect_chain(root, children_of);
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if (chain.size() < 2)
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continue;
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for (auto c : chain)
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processed.insert(c);
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int correction;
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auto operands = extract_chain_operands(
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chain, root, parent_of, correction);
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if (operands.size() < 3)
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continue;
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replace_with_csa_tree(operands, root->getPort(ID::Y),
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correction, "Replaced add/sub chain");
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for (auto cell : chain)
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module->remove(cell);
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}
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}
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void process_maccs()
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{
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for (auto cell : cells.macc) {
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std::vector<Operand> operands;
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int correction;
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if (!extract_macc_operands(cell, operands, correction))
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continue;
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if (operands.size() < 3)
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continue;
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replace_with_csa_tree(operands, cell->getPort(ID::Y),
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correction, "Replaced $macc");
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module->remove(cell);
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}
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}
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};
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void run(Module* module) {
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Cells cells(module);
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if (cells.empty())
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return;
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Rewriter rewriter {module, cells};
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rewriter.process_chains();
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rewriter.process_maccs();
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}
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struct CsaTreePass : public Pass {
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CsaTreePass() : Pass("csa_tree",
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"convert add/sub/macc chains to carry-save adder trees") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" csa_tree [selection]\n");
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log("\n");
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log("This pass replaces chains of $add/$sub cells, $alu cells (with constant\n");
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log("BI/CI), and $macc/$macc_v2 cells (without multiplications) with carry-save\n");
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log("adder trees using $fa cells and a single final $add.\n");
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log("\n");
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log("The tree uses Wallace-tree scheduling: at each level, ready operands are\n");
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log("grouped into triplets and compressed via full adders, giving\n");
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log("O(log_{1.5} N) depth for N input operands.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design* design) override
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{
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log_header(design, "Executing CSA_TREE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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||||
break;
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
run(module);
|
||||
}
|
||||
}
|
||||
} CsaTreePass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Add table
Add a link
Reference in a new issue