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https://github.com/YosysHQ/yosys
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csa_tree: refactor
This commit is contained in:
Emil J. Tywoniak
nella
parent
c3bc2d88da
commit
eb477b2d56
1 changed files with 100 additions and 122 deletions
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@ -13,19 +13,32 @@ struct Operand {
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bool negate;
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};
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struct CsaTreeWorker
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struct Traversal
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{
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Module* module;
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SigMap sigmap;
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dict<SigBit, pool<Cell*>> bit_consumers;
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dict<SigBit, int> fanout;
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Traversal(Module* module) : sigmap(module) {
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for (auto cell : module->cells())
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for (auto& conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_consumers[bit].insert(cell);
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pool<Cell*> addsub_cells;
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pool<Cell*> alu_cells;
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pool<Cell*> macc_cells;
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for (auto& pair : bit_consumers)
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fanout[pair.first] = pair.second.size();
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CsaTreeWorker(Module* module) : module(module), sigmap(module) {}
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for (auto wire : module->wires())
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if (wire->port_output)
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for (auto bit : sigmap(SigSpec(wire)))
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fanout[bit]++;
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}
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};
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struct Cells {
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pool<Cell*> addsub;
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pool<Cell*> alu;
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pool<Cell*> macc;
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static bool is_addsub(Cell* cell)
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{
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@ -42,79 +55,74 @@ struct CsaTreeWorker
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return cell->type == ID($macc) || cell->type == ID($macc_v2);
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}
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bool alu_is_subtract(Cell* cell)
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bool empty() {
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return addsub.empty() && alu.empty() && macc.empty();
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}
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Cells(Module* module) {
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for (auto cell : module->cells()) {
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if (is_addsub(cell))
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addsub.insert(cell);
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else if (is_alu(cell))
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alu.insert(cell);
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else if (is_macc(cell))
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macc.insert(cell);
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}
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}
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};
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struct AluInfo {
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Cells& cells;
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Traversal& traversal;
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bool is_subtract(Cell* cell)
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{
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SigSpec bi = sigmap(cell->getPort(ID::BI));
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SigSpec ci = sigmap(cell->getPort(ID::CI));
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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return GetSize(bi) == 1 && bi[0] == State::S1 && GetSize(ci) == 1 && ci[0] == State::S1;
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}
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bool alu_is_add(Cell* cell)
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bool is_add(Cell* cell)
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{
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SigSpec bi = sigmap(cell->getPort(ID::BI));
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SigSpec ci = sigmap(cell->getPort(ID::CI));
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SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
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SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
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return GetSize(bi) == 1 && bi[0] == State::S0 && GetSize(ci) == 1 && ci[0] == State::S0;
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}
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bool alu_is_chainable(Cell* cell)
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{
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if (!(alu_is_add(cell) || alu_is_subtract(cell)))
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return false;
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for (auto bit : sigmap(cell->getPort(ID::X)))
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if (fanout.count(bit) && fanout[bit] > 0)
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return false;
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for (auto bit : sigmap(cell->getPort(ID::CO)))
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if (fanout.count(bit) && fanout[bit] > 0)
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return false;
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return true;
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}
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bool is_chainable(Cell* cell)
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{
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return is_addsub(cell) || (is_alu(cell) && alu_is_chainable(cell));
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if (!(is_add(cell) || is_subtract(cell)))
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return false;
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for (auto bit : traversal.sigmap(cell->getPort(ID::X)))
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if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
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return false;
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for (auto bit : traversal.sigmap(cell->getPort(ID::CO)))
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if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
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return false;
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return true;
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}
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};
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void classify_cells()
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{
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for (auto cell : module->cells()) {
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if (is_addsub(cell))
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addsub_cells.insert(cell);
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else if (is_alu(cell))
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alu_cells.insert(cell);
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else if (is_macc(cell))
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macc_cells.insert(cell);
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}
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}
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struct Rewriter
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{
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Module* module;
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Cells& cells;
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Traversal traversal;
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AluInfo alu_info;
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void build_fanout_map()
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{
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for (auto cell : module->cells())
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for (auto& conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_consumers[bit].insert(cell);
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for (auto& pair : bit_consumers)
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fanout[pair.first] = pair.second.size();
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for (auto wire : module->wires())
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if (wire->port_output)
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for (auto bit : sigmap(SigSpec(wire)))
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fanout[bit]++;
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}
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Rewriter(Module* module, Cells& cells) : module(module), cells(cells), traversal(module), alu_info{cells, traversal} {}
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Cell* sole_chainable_consumer(SigSpec sig, const pool<Cell*>& candidates)
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{
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Cell* consumer = nullptr;
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for (auto bit : sig) {
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if (!fanout.count(bit) || fanout[bit] != 1)
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if (!traversal.fanout.count(bit) || traversal.fanout[bit] != 1)
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return nullptr;
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if (!bit_consumers.count(bit) || bit_consumers[bit].size() != 1)
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if (!traversal.bit_consumers.count(bit) || traversal.bit_consumers[bit].size() != 1)
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return nullptr;
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Cell* c = *bit_consumers[bit].begin();
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Cell* c = *traversal.bit_consumers[bit].begin();
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if (!candidates.count(c))
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return nullptr;
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@ -131,7 +139,7 @@ struct CsaTreeWorker
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dict<Cell*, Cell*> parent_of;
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for (auto cell : candidates) {
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Cell* consumer = sole_chainable_consumer(
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sigmap(cell->getPort(ID::Y)), candidates);
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traversal.sigmap(cell->getPort(ID::Y)), candidates);
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if (consumer && consumer != cell)
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parent_of[cell] = consumer;
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}
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@ -144,7 +152,8 @@ struct CsaTreeWorker
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std::queue<Cell*> q;
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q.push(root);
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while (!q.empty()) {
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Cell* cur = q.front(); q.pop();
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Cell* cur = q.front();
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q.pop();
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if (!chain.insert(cur).second)
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continue;
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auto it = children_of.find(cur);
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@ -159,7 +168,7 @@ struct CsaTreeWorker
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{
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pool<SigBit> bits;
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for (auto cell : chain)
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for (auto bit : sigmap(cell->getPort(ID::Y)))
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for (auto bit : traversal.sigmap(cell->getPort(ID::Y)))
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bits.insert(bit);
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return bits;
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}
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@ -177,16 +186,16 @@ struct CsaTreeWorker
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bool parent_subtracts;
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if (parent->type == ID($sub))
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parent_subtracts = true;
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else if (is_alu(parent))
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parent_subtracts = alu_is_subtract(parent);
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else if (cells.is_alu(parent))
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parent_subtracts = alu_info.is_subtract(parent);
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else
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return false;
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if (!parent_subtracts)
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return false;
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SigSpec child_y = sigmap(child->getPort(ID::Y));
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SigSpec parent_b = sigmap(parent->getPort(ID::B));
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SigSpec child_y = traversal.sigmap(child->getPort(ID::Y));
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SigSpec parent_b = traversal.sigmap(parent->getPort(ID::B));
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for (auto bit : child_y)
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for (auto pbit : parent_b)
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if (bit == pbit)
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@ -229,11 +238,11 @@ struct CsaTreeWorker
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else
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cell_neg = false;
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SigSpec a = sigmap(cell->getPort(ID::A));
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SigSpec b = sigmap(cell->getPort(ID::B));
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SigSpec a = traversal.sigmap(cell->getPort(ID::A));
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SigSpec b = traversal.sigmap(cell->getPort(ID::B));
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bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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bool b_sub = (cell->type == ID($sub)) || (is_alu(cell) && alu_is_subtract(cell));
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bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
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if (!overlaps(a, chain_bits)) {
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bool neg = cell_neg;
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@ -255,6 +264,7 @@ struct CsaTreeWorker
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correction = 0;
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for (auto& term : macc.terms) {
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// Bail on multiplication
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if (GetSize(term.in_b) != 0)
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return false;
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operands.push_back({term.in_a, term.is_signed, term.do_subtract});
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@ -279,30 +289,12 @@ struct CsaTreeWorker
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return sig;
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}
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SigSpec emit_not(SigSpec sig, int width)
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{
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SigSpec out = module->addWire(NEW_ID, width);
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Cell* inv = module->addCell(NEW_ID, ID($not));
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inv->setParam(ID::A_SIGNED, false);
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inv->setParam(ID::A_WIDTH, width);
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inv->setParam(ID::Y_WIDTH, width);
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inv->setPort(ID::A, sig);
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inv->setPort(ID::Y, out);
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return out;
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}
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std::pair<SigSpec, SigSpec> emit_fa(SigSpec a, SigSpec b, SigSpec c, int width)
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{
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec cout = module->addWire(NEW_ID, width);
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Cell* fa = module->addCell(NEW_ID, ID($fa));
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fa->setParam(ID::WIDTH, width);
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fa->setPort(ID::A, a);
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fa->setPort(ID::B, b);
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fa->setPort(ID::C, c);
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fa->setPort(ID::X, cout);
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fa->setPort(ID::Y, sum);
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module->addFa(NEW_ID, a, b, c, cout, sum);
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SigSpec carry;
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carry.append(State::S0);
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@ -310,19 +302,6 @@ struct CsaTreeWorker
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return {sum, carry};
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}
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void emit_final_add(SigSpec a, SigSpec b, SigSpec y, int width)
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{
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Cell* add = module->addCell(NEW_ID, ID($add));
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add->setParam(ID::A_SIGNED, false);
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add->setParam(ID::B_SIGNED, false);
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add->setParam(ID::A_WIDTH, width);
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add->setParam(ID::B_WIDTH, width);
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add->setParam(ID::Y_WIDTH, width);
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add->setPort(ID::A, a);
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add->setPort(ID::B, b);
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add->setPort(ID::Y, y);
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}
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struct DepthSig {
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SigSpec sig;
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int depth;
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@ -387,7 +366,7 @@ struct CsaTreeWorker
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for (auto& op : operands) {
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SigSpec s = extend_operand(op.sig, op.is_signed, width);
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if (op.negate)
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s = emit_not(s, width);
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s = module->Not(NEW_ID, s);
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extended.push_back(s);
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}
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@ -400,16 +379,17 @@ struct CsaTreeWorker
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log(" %s -> %d $fa + 1 $add (%d operands, module %s)\n",
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desc, fa_count, (int)operands.size(), log_id(module));
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emit_final_add(a, b, result_y, width);
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// Emit final add
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module->addAdd(NEW_ID, a, b, result_y, false);
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}
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void process_chains()
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{
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pool<Cell*> candidates;
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for (auto cell : addsub_cells)
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for (auto cell : cells.addsub)
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candidates.insert(cell);
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for (auto cell : alu_cells)
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if (alu_is_chainable(cell))
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for (auto cell : cells.alu)
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if (alu_info.is_chainable(cell))
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candidates.insert(cell);
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if (candidates.empty())
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@ -427,7 +407,7 @@ struct CsaTreeWorker
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pool<Cell*> processed;
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for (auto root : candidates) {
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if (has_parent.count(root) || processed.count(root))
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continue;
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continue; // Not a tree root
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pool<Cell*> chain = collect_chain(root, children_of);
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if (chain.size() < 2)
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@ -451,7 +431,7 @@ struct CsaTreeWorker
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void process_maccs()
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{
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for (auto cell : macc_cells) {
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for (auto cell : cells.macc) {
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std::vector<Operand> operands;
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int correction;
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if (!extract_macc_operands(cell, operands, correction))
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@ -464,20 +444,19 @@ struct CsaTreeWorker
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module->remove(cell);
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}
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}
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void run()
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{
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classify_cells();
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if (addsub_cells.empty() && alu_cells.empty() && macc_cells.empty())
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return;
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build_fanout_map();
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process_chains();
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process_maccs();
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}
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};
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void run(Module* module) {
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Cells cells(module);
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if (cells.empty())
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return;
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Rewriter rewriter {module, cells};
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rewriter.process_chains();
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rewriter.process_maccs();
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}
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struct CsaTreePass : public Pass {
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CsaTreePass() : Pass("csa_tree",
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"convert add/sub/macc chains to carry-save adder trees") {}
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@ -508,8 +487,7 @@ struct CsaTreePass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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CsaTreeWorker worker(module);
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worker.run();
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run(module);
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}
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}
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} CsaTreePass;
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