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Move unextend initialisation later
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@ -3,19 +3,6 @@ pattern xilinx_dsp_cascadeP
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigSpec> sigC
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state <SigSpec> sigC
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code
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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endcode
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match dsp_pcin
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match dsp_pcin
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select dsp_pcin->type.in(\DSP48E1)
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select dsp_pcin->type.in(\DSP48E1)
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select !param(dsp_pcin, \CREG, State::S1).as_bool()
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select !param(dsp_pcin, \CREG, State::S1).as_bool()
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@ -25,6 +12,16 @@ match dsp_pcin
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endmatch
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endmatch
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code sigC
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code sigC
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigC = unextend(port(dsp_pcin, \C));
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sigC = unextend(port(dsp_pcin, \C));
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endcode
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endcode
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