diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 19fe48bba..37674efea 100644
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -3,19 +3,6 @@ pattern xilinx_dsp_cascadeP
 udata <std::function<SigSpec(const SigSpec&)>> unextend
 state <SigSpec> sigC
 
-code
-	unextend = [](const SigSpec &sig) {
-		int i;
-		for (i = GetSize(sig)-1; i > 0; i--)
-			if (sig[i] != sig[i-1])
-				break;
-		// Do not remove non-const sign bit
-		if (sig[i].wire)
-			++i;
-		return sig.extract(0, i);
-	};
-endcode
-
 match dsp_pcin
 	select dsp_pcin->type.in(\DSP48E1)
 	select !param(dsp_pcin, \CREG, State::S1).as_bool()
@@ -25,6 +12,16 @@ match dsp_pcin
 endmatch
 
 code sigC
+	unextend = [](const SigSpec &sig) {
+		int i;
+		for (i = GetSize(sig)-1; i > 0; i--)
+			if (sig[i] != sig[i-1])
+				break;
+		// Do not remove non-const sign bit
+		if (sig[i].wire)
+			++i;
+		return sig.extract(0, i);
+	};
 	sigC = unextend(port(dsp_pcin, \C));
 endcode