From cf511628b0dc3ec3cc3d372cab3f74f0208f79cc Mon Sep 17 00:00:00 2001
From: Natalia <nataliakokoromyti@gmail.com>
Date: Sun, 18 Jan 2026 02:11:09 -0800
Subject: [PATCH] modify generator for pyosys/wrappers.cc instead of headers

---
 kernel/rtlil.cc                           |  7 ---
 kernel/rtlil.h                            |  2 -
 pyosys/generator.py                       | 10 ++++
 tests/pyosys/test_design_run_pass.py      | 12 +++++
 tests/unit/kernel/test_design_run_pass.cc | 59 -----------------------
 5 files changed, 22 insertions(+), 68 deletions(-)
 create mode 100644 tests/pyosys/test_design_run_pass.py
 delete mode 100644 tests/unit/kernel/test_design_run_pass.cc

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 357ac2c5a..0103cabfb 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1610,13 +1610,6 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
 	return result;
 }
 
-void RTLIL::Design::run_pass(std::string command)
-{
-	log("\n-- Running command `%s' --\n", command.c_str());
-	Pass::call(this, command);
-	log_flush();
-}
-
 RTLIL::Module::Module()
 {
 	static unsigned int hashidx_count = 123456789;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 532aa20b4..fea53081e 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -2032,8 +2032,6 @@ struct RTLIL::Design
 	// partially selected or boxed modules have been ignored
 	std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
 
-	void run_pass(std::string command);
-
 	static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
 
 	std::string to_rtlil_str(bool only_selected = true) const;
diff --git a/pyosys/generator.py b/pyosys/generator.py
index 7d4293abd..0dda98015 100644
--- a/pyosys/generator.py
+++ b/pyosys/generator.py
@@ -701,6 +701,16 @@ class PyosysWrapperGenerator(object):
 
         self.process_class_members(metadata, metadata, cls, basename)
 
+        if basename == "Design":
+            print(
+                '\t\t\t.def("run_pass", [](Design &s, std::vector<std::string> cmd) { Pass::call(cmd, &s); })',
+                file=self.f,
+            )
+            print(
+                '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(cmd, &s); })',
+                file=self.f,
+            )
+
         if expr := metadata.string_expr:
             print(
                 f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})',
diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py
new file mode 100644
index 000000000..c9656fd7a
--- /dev/null
+++ b/tests/pyosys/test_design_run_pass.py
@@ -0,0 +1,12 @@
+from pathlib import Path
+
+from pyosys import libyosys as ys
+
+__file_dir__ = Path(__file__).absolute().parent
+
+design = ys.Design()
+design.run_pass(
+	["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")]
+)
+design.run_pass("prep")
+design.run_pass(["opt", "-full"])
diff --git a/tests/unit/kernel/test_design_run_pass.cc b/tests/unit/kernel/test_design_run_pass.cc
deleted file mode 100644
index 0553f4eb2..000000000
--- a/tests/unit/kernel/test_design_run_pass.cc
+++ /dev/null
@@ -1,59 +0,0 @@
-#include <gtest/gtest.h>
-#include "kernel/rtlil.h"
-#include "kernel/register.h"
-
-YOSYS_NAMESPACE_BEGIN
-
-class DesignRunPassTest : public testing::Test {
-protected:
-	DesignRunPassTest() {
-		if (log_files.empty()) log_files.emplace_back(stdout);
-	}
-	virtual void SetUp() override {
-		IdString::ensure_prepopulated();
-	}
-};
-
-TEST_F(DesignRunPassTest, RunPassExecutesSuccessfully)
-{
-	// Create a design with a simple module
-	RTLIL::Design *design = new RTLIL::Design;
-	RTLIL::Module *module = new RTLIL::Module;
-	module->name = RTLIL::IdString("\\test_module");
-	design->add(module);
-
-	// Add a simple wire to the module
-	RTLIL::Wire *wire = module->addWire(RTLIL::IdString("\\test_wire"), 1);
-	wire->port_input = true;
-	wire->port_id = 1;
-	module->fixup_ports();
-
-	// Call run_pass with a simple pass
-	// We use "check" which is a simple pass that just validates the design
-	ASSERT_NO_THROW(design->run_pass("check"));
-
-	// Verify the design still exists and has the module
-	EXPECT_EQ(design->modules().size(), 1);
-	EXPECT_NE(design->module(RTLIL::IdString("\\test_module")), nullptr);
-
-	delete design;
-}
-
-TEST_F(DesignRunPassTest, RunPassWithHierarchy)
-{
-	// Create a design with a simple module
-	RTLIL::Design *design = new RTLIL::Design;
-	RTLIL::Module *module = new RTLIL::Module;
-	module->name = RTLIL::IdString("\\top");
-	design->add(module);
-
-	// Call run_pass with hierarchy pass
-	ASSERT_NO_THROW(design->run_pass("hierarchy"));
-
-	// Verify the design still has the module
-	EXPECT_EQ(design->modules().size(), 1);
-
-	delete design;
-}
-
-YOSYS_NAMESPACE_END