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Improvements in wreduce

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This commit is contained in:
Clifford Wolf 2015-10-31 13:39:30 +01:00
parent 864808992b
commit ccdbf41be6
2 changed files with 34 additions and 0 deletions
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25
passes/opt/wreduce.cc
View file

@ -201,6 +201,31 @@ struct WreduceWorker
if (max_port_b_size >= 0)
run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something);
if (cell->hasPort("\\A") && cell->hasPort("\\B") && port_a_signed && port_b_signed) {
SigSpec sig_a = mi.sigmap(cell->getPort("\\A")), sig_b = mi.sigmap(cell->getPort("\\B"));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
cell->setParam("\\A_SIGNED", 0);
cell->setParam("\\B_SIGNED", 0);
port_a_signed = false;
port_b_signed = false;
did_something = true;
}
}
if (cell->hasPort("\\A") && !cell->hasPort("\\B") && port_a_signed) {
SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
cell->setParam("\\A_SIGNED", 0);
port_a_signed = false;
did_something = true;
}
}
// Reduce size of port Y based on sizes for A and B and unused bits in Y

9
tests/simple/wreduce.v Normal file
View file

@ -0,0 +1,9 @@
module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z);
assign x = -$signed({1'b0, a});
assign y = $signed({1'b0, a}) + $signed({1'b0, b});
assign z = x ^ y;
endmodule
module wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w);
assign x = a - b, y = a * b, z = a >> b, w = a << b;
endmodule