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tests: fix the rest

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This commit is contained in:
Emil J. Tywoniak 2026-02-07 01:17:35 +01:00
parent cf2431ac2d
commit cc5ebf8ee8
16 changed files with 36 additions and 10 deletions
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2
tests/aiger/run-test.sh
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@ -32,6 +32,7 @@ prep
design -stash gate
design -import gold -as gold
design -import gate -as gate
formalff -clk2ff
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 16 miter
" -l ${aag}.log
@ -49,6 +50,7 @@ prep
design -stash gate
design -import gold -as gold
design -import gate -as gate
formalff -clk2ff
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 16 miter
" -l ${aig}.log

1
tests/arch/ecp5/dpram.ys
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@ -10,6 +10,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
#Blocked by issue #1358 (Missing ECP5 simulation models)
#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
#formalff -clk2ff
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt

1
tests/arch/ice40/dpram.ys
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@ -7,6 +7,7 @@ memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt

1
tests/fsm/generate.py
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@ -116,5 +116,6 @@ for idx in range(args.count):
print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
print('cd ..')
print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
print('formalff -clk2ff')
print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))

1
tests/liberty/read_liberty.ys
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@ -4,6 +4,7 @@ read_verilog retention.lib.verilogsim
proc
rename retention_cell retention_cell_vlog
async2sync
formalff -clk2ff
equiv_make retention_cell_lib retention_cell_vlog equiv
equiv_induct equiv
equiv_status -assert equiv

13
tests/opt/opt_dff_dffmux.ys
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@ -6,7 +6,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -formalff -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D
@ -21,7 +21,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -formalff -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$dffe r:WIDTH=2 %i
@ -37,7 +37,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -formalff -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D
@ -52,7 +52,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -formalff -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=4 %i
select -assert-count 0 t:$dffe %% t:* %D
@ -67,7 +67,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -formalff -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i
@ -86,7 +86,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -formalff -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i
@ -122,6 +122,7 @@ design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
formalff -clk2ff
sat -tempinduct -verify -prove-asserts -show-ports miter
design -load gate

2
tests/sat/asserts.ys
View file

@ -1,3 +1,3 @@
read_verilog -sv asserts.v
hierarchy; proc; opt; async2sync
hierarchy; proc; opt; async2sync; formalff -clk2ff
sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts

2
tests/sat/asserts_seq.ys
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@ -1,5 +1,5 @@
read_verilog -sv asserts_seq.v
hierarchy; proc; opt; async2sync
hierarchy; proc; opt; async2sync; formalff -clk2ff
sat -verify -prove-asserts -tempinduct -seq 1 test_001
sat -falsify -prove-asserts -tempinduct -seq 1 test_002

1
tests/sat/counters-repeat.ys
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@ -4,6 +4,7 @@ proc; opt
expose -shared counter1 counter2
miter -equiv -make_assert -make_outputs counter1 counter2 miter
formalff -clk2ff
cd miter; flatten; opt
sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs

1
tests/sat/counters.ys
View file

@ -4,6 +4,7 @@ proc; opt
expose -shared counter1 counter2
miter -equiv -make_assert -make_outputs counter1 counter2 miter
formalff -clk2ff
cd miter; flatten; opt
sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs

2
tests/sat/dff.ys
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@ -18,4 +18,4 @@ endmodule
EOT
# This ensures that 1) coarse cells have SAT models, 2) fine cells have SAT models, 3) they're equivalent
equiv_opt -assert simplemap
equiv_opt -formalff -assert simplemap

2
tests/svtypes/enum_simple.ys
View file

@ -1,5 +1,5 @@
read_verilog -sv enum_simple.sv
hierarchy; proc; opt; async2sync
hierarchy; proc; opt; async2sync; formalff -clk2ff
sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all

5
tests/techmap/dfflibmap_formal.ys
View file

@ -1,3 +1,4 @@
#TODO formalff shouldn't be used here. Instead, we should use SAT
##################################################################
read_verilog -sv -icells <<EOT
@ -33,6 +34,7 @@ copy top top_unmapped
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
async2sync
formalff -clk2ff
flatten
opt_clean -purge
equiv_make top top_unmapped equiv
@ -74,6 +76,7 @@ copy top top_unmapped
dfflibmap -liberty dfflibmap_dffr_not_next.lib top
async2sync
formalff -clk2ff
flatten
opt_clean -purge
equiv_make top top_unmapped equiv
@ -109,6 +112,7 @@ simplemap top
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
async2sync
formalff -clk2ff
flatten
opt_clean -purge
equiv_make top top_unmapped equiv
@ -140,6 +144,7 @@ simplemap top
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dff_not_next.lib top
async2sync
formalff -clk2ff
flatten
opt_clean -purge
equiv_make top top_unmapped equiv

1
tests/various/abstract_initstates.ys
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@ -10,6 +10,7 @@ endmodule
EOT
proc
formalff -clk2ff
design -save half_clock
sat -set-init-undef -enable_undef -verify -seq 5 -set-at 1 Q 0

10
tests/various/dynamic_part_select.ys
View file

@ -13,6 +13,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### Multiple blocking assingments ###
@ -31,6 +32,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### Non-blocking to the same output register ###
@ -49,6 +51,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### For-loop select, one dynamic input
@ -67,6 +70,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### For-loop select, one dynamic input, (* nowrshmsk *)
@ -85,6 +89,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
#### Double loop (part-select, reset) ###
@ -103,6 +108,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### Reversed part-select case ###
@ -121,6 +127,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### Latches
@ -140,6 +147,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -show-public -verify -set-init-zero equiv
###
@ -159,6 +167,7 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -falsify -set-init-zero equiv
## Part select + latch, with no shift&mask
@ -177,4 +186,5 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
formalff -clk2ff
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv

1
tests/verilog/func_upto.ys
View file

@ -4,5 +4,6 @@ proc
flatten
opt -full
async2sync
formalff -clk2ff
select -module top
sat -verify -seq 1 -prove-asserts -enable_undef