3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-14 12:51:48 +00:00
yosys/tests/sat/counters-repeat.ys
2026-02-07 01:22:24 +01:00

11 lines
274 B
Text

read_verilog counters-repeat.v
proc; opt
expose -shared counter1 counter2
miter -equiv -make_assert -make_outputs counter1 counter2 miter
formalff -clk2ff
cd miter; flatten; opt
sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs