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analogdevices: Native LUTRAM primitives

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This commit is contained in:
Krystine Sherwin 2025-10-08 14:08:41 +13:00
parent 763c69b554
commit cc217456b3
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3 changed files with 182 additions and 1497 deletions
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1083
techlibs/analogdevices/cells_sim.v
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File diff suppressed because it is too large Load diff

46
techlibs/analogdevices/lutrams.txt
View file

@ -4,66 +4,40 @@
# Single-port RAMs. # Single-port RAMs.
ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
cost 8;
widthscale;
option "ABITS" 5 { option "ABITS" 5 {
cost 1;
abits 5; abits 5;
widths 8 global; width 1;
} }
option "ABITS" 6 { option "ABITS" 6 {
cost 2;
abits 6; abits 6;
widths 4 global; width 1;
} }
init no_undef; init no_undef;
prune_rom; prune_rom;
port arsw "RW" { port arsw "RW" {
clock posedge; clock anyedge;
} }
} }
# Dual-port RAMs. # Dual-port RAMs.
ram distributed $__ANALOGDEVICES_LUTRAM_DP_ { ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
cost 8;
widthscale;
option "ABITS" 5 { option "ABITS" 5 {
cost 2;
abits 5; abits 5;
widths 4 global; width 1;
} }
option "ABITS" 6 { option "ABITS" 6 {
cost 4;
abits 6; abits 6;
widths 2 global; width 1;
}
option "ABITS" 7 {
abits 7;
widths 1 global;
} }
init no_undef; init no_undef;
prune_rom; prune_rom;
port arsw "RW" { port arsw "RW" {
clock posedge; clock anyedge;
}
port ar "R" {
}
}
# Simple dual port RAMs.
ram distributed $__ANALOGDEVICES_LUTRAM_SDP_ {
cost 8;
widthscale 7;
option "ABITS" 5 {
abits 5;
widths 6 global;
}
option "ABITS" 6 {
abits 6;
widths 3 global;
}
init no_undef;
prune_rom;
port sw "W" {
clock posedge;
} }
port ar "R" { port ar "R" {
} }

492
techlibs/analogdevices/lutrams_map.v
View file

@ -6,121 +6,91 @@ module $__ANALOGDEVICES_LUTRAM_SP_ (...);
parameter INIT = 0; parameter INIT = 0;
parameter OPTION_ABITS = 5; parameter OPTION_ABITS = 5;
parameter WIDTH = 8; parameter WIDTH = 1;
parameter BITS_USED = 0; parameter PORT_RW_CLK_POL = 1;
output [WIDTH-1:0] PORT_RW_RD_DATA; output PORT_RW_RD_DATA;
input [WIDTH-1:0] PORT_RW_WR_DATA; input PORT_RW_WR_DATA;
input [OPTION_ABITS-1:0] PORT_RW_ADDR; input [OPTION_ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN; input PORT_RW_WR_EN;
input PORT_RW_CLK; input PORT_RW_CLK;
function [(1 << OPTION_ABITS)-1:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
init_slice[i] = INIT[i * WIDTH + idx];
endfunction
function [(2 << OPTION_ABITS)-1:0] init_slice2;
input integer idx;
integer i;
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
endfunction
generate generate
case(OPTION_ABITS) case(OPTION_ABITS)
5: if (WIDTH == 8) 5:
RAM32M if (PORT_RW_CLK_POL)
RAMS32X1
#( #(
.INIT_D(init_slice2(0)), .INIT(INIT),
.INIT_C(init_slice2(1)),
.INIT_B(init_slice2(2)),
.INIT_A(init_slice2(3)),
) )
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
( (
.DOA(PORT_RW_RD_DATA[7:6]), .O(PORT_RW_RD_DATA),
.DOB(PORT_RW_RD_DATA[5:4]), .A0(PORT_RW_ADDR[0]),
.DOC(PORT_RW_RD_DATA[3:2]), .A1(PORT_RW_ADDR[1]),
.DOD(PORT_RW_RD_DATA[1:0]), .A2(PORT_RW_ADDR[2]),
.DIA(PORT_RW_WR_DATA[7:6]), .A3(PORT_RW_ADDR[3]),
.DIB(PORT_RW_WR_DATA[5:4]), .A4(PORT_RW_ADDR[4]),
.DIC(PORT_RW_WR_DATA[3:2]), .D(PORT_RW_WR_DATA),
.DID(PORT_RW_WR_DATA[1:0]),
.ADDRA(PORT_RW_ADDR),
.ADDRB(PORT_RW_ADDR),
.ADDRC(PORT_RW_ADDR),
.ADDRD(PORT_RW_ADDR),
.WE(PORT_RW_WR_EN),
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN),
); );
else else
RAM32M16 RAMS32X1_N
#( #(
.INIT_H(init_slice2(0)), .INIT(INIT),
.INIT_G(init_slice2(1)),
.INIT_F(init_slice2(2)),
.INIT_E(init_slice2(3)),
.INIT_D(init_slice2(4)),
.INIT_C(init_slice2(5)),
.INIT_B(init_slice2(6)),
.INIT_A(init_slice2(7)),
) )
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
( (
.DOA(PORT_RW_RD_DATA[15:14]), .O(PORT_RW_RD_DATA),
.DOB(PORT_RW_RD_DATA[13:12]), .A0(PORT_RW_ADDR[0]),
.DOC(PORT_RW_RD_DATA[11:10]), .A1(PORT_RW_ADDR[1]),
.DOD(PORT_RW_RD_DATA[9:8]), .A2(PORT_RW_ADDR[2]),
.DOE(PORT_RW_RD_DATA[7:6]), .A3(PORT_RW_ADDR[3]),
.DOF(PORT_RW_RD_DATA[5:4]), .A4(PORT_RW_ADDR[4]),
.DOG(PORT_RW_RD_DATA[3:2]), .D(PORT_RW_WR_DATA),
.DOH(PORT_RW_RD_DATA[1:0]),
.DIA(PORT_RW_WR_DATA[15:14]),
.DIB(PORT_RW_WR_DATA[13:12]),
.DIC(PORT_RW_WR_DATA[11:10]),
.DID(PORT_RW_WR_DATA[9:8]),
.DIE(PORT_RW_WR_DATA[7:6]),
.DIF(PORT_RW_WR_DATA[5:4]),
.DIG(PORT_RW_WR_DATA[3:2]),
.DIH(PORT_RW_WR_DATA[1:0]),
.ADDRA(PORT_RW_ADDR),
.ADDRB(PORT_RW_ADDR),
.ADDRC(PORT_RW_ADDR),
.ADDRD(PORT_RW_ADDR),
.ADDRE(PORT_RW_ADDR),
.ADDRF(PORT_RW_ADDR),
.ADDRG(PORT_RW_ADDR),
.ADDRH(PORT_RW_ADDR),
.WE(PORT_RW_WR_EN),
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN),
); );
6: begin 6:
genvar i; if (PORT_RW_CLK_POL)
for (i = 0; i < WIDTH; i = i + 1) RAMS64X1
if (BITS_USED[i])
RAM64X1S
#( #(
.INIT(init_slice(i)), .INIT(INIT),
) )
slice _TECHMAP_REPLACE_
( (
.O(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]), .A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]), .A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]), .A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]), .A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]), .A4(PORT_RW_ADDR[4]),
.A5(PORT_RW_ADDR[5]), .A5(PORT_RW_ADDR[5]),
.D(PORT_RW_WR_DATA[i]), .D(PORT_RW_WR_DATA),
.O(PORT_RW_RD_DATA[i]),
.WE(PORT_RW_WR_EN),
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN),
);
else
RAMS64X1_N
#(
.INIT(INIT),
)
_TECHMAP_REPLACE_
(
.O(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]),
.A5(PORT_RW_ADDR[5]),
.D(PORT_RW_WR_DATA),
.WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN),
); );
end
default: default:
$error("invalid OPTION_ABITS/WIDTH combination"); $error("invalid OPTION_ABITS");
endcase endcase
endgenerate endgenerate
@ -131,328 +101,120 @@ module $__ANALOGDEVICES_LUTRAM_DP_ (...);
parameter INIT = 0; parameter INIT = 0;
parameter OPTION_ABITS = 5; parameter OPTION_ABITS = 5;
parameter WIDTH = 4; parameter WIDTH = 1;
parameter BITS_USED = 0; parameter PORT_RW_CLK_POL = 1;
output [WIDTH-1:0] PORT_RW_RD_DATA; output PORT_RW_RD_DATA;
input [WIDTH-1:0] PORT_RW_WR_DATA; input PORT_RW_WR_DATA;
input [OPTION_ABITS-1:0] PORT_RW_ADDR; input [OPTION_ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN; input PORT_RW_WR_EN;
input PORT_RW_CLK; input PORT_RW_CLK;
output [WIDTH-1:0] PORT_R_RD_DATA; input PORT_R_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R_ADDR; input [OPTION_ABITS-1:0] PORT_R_ADDR;
function [(1 << OPTION_ABITS)-1:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
init_slice[i] = INIT[i * WIDTH + idx];
endfunction
function [(2 << OPTION_ABITS)-1:0] init_slice2;
input integer idx;
integer i;
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
endfunction
generate generate
case (OPTION_ABITS) case(OPTION_ABITS)
5: if (WIDTH == 4) 5:
RAM32M if (PORT_RW_CLK_POL)
RAMD32X1
#( #(
.INIT_D(init_slice2(0)), .INIT(INIT),
.INIT_C(init_slice2(0)),
.INIT_B(init_slice2(1)),
.INIT_A(init_slice2(1)),
) )
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
( (
.DOA(PORT_R_RD_DATA[3:2]), .DPO(PORT_R_RD_DATA),
.DOB(PORT_RW_RD_DATA[3:2]), .SPO(PORT_RW_RD_DATA),
.DOC(PORT_R_RD_DATA[1:0]), .A0(PORT_RW_ADDR[0]),
.DOD(PORT_RW_RD_DATA[1:0]), .A1(PORT_RW_ADDR[1]),
.DIA(PORT_RW_WR_DATA[3:2]), .A2(PORT_RW_ADDR[2]),
.DIB(PORT_RW_WR_DATA[3:2]), .A3(PORT_RW_ADDR[3]),
.DIC(PORT_RW_WR_DATA[1:0]), .A4(PORT_RW_ADDR[4]),
.DID(PORT_RW_WR_DATA[1:0]), .D(PORT_RW_WR_DATA),
.ADDRA(PORT_R_ADDR), .DPRA0(PORT_R_ADDR[0]),
.ADDRB(PORT_RW_ADDR), .DPRA1(PORT_R_ADDR[1]),
.ADDRC(PORT_R_ADDR), .DPRA2(PORT_R_ADDR[2]),
.ADDRD(PORT_RW_ADDR), .DPRA3(PORT_R_ADDR[3]),
.WE(PORT_RW_WR_EN), .DPRA4(PORT_R_ADDR[4]),
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN),
); );
else else
RAM32M16 RAMD32X1_N
#( #(
.INIT_H(init_slice2(0)), .INIT(INIT),
.INIT_G(init_slice2(0)),
.INIT_F(init_slice2(1)),
.INIT_E(init_slice2(1)),
.INIT_D(init_slice2(2)),
.INIT_C(init_slice2(2)),
.INIT_B(init_slice2(3)),
.INIT_A(init_slice2(3)),
) )
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
( (
.DOA(PORT_R_RD_DATA[7:6]), .DPO(PORT_R_RD_DATA),
.DOB(PORT_RW_RD_DATA[7:6]), .SPO(PORT_RW_RD_DATA),
.DOC(PORT_R_RD_DATA[5:4]), .A0(PORT_RW_ADDR[0]),
.DOD(PORT_RW_RD_DATA[5:4]), .A1(PORT_RW_ADDR[1]),
.DOE(PORT_R_RD_DATA[3:2]), .A2(PORT_RW_ADDR[2]),
.DOF(PORT_RW_RD_DATA[3:2]), .A3(PORT_RW_ADDR[3]),
.DOG(PORT_R_RD_DATA[1:0]), .A4(PORT_RW_ADDR[4]),
.DOH(PORT_RW_RD_DATA[1:0]), .D(PORT_RW_WR_DATA),
.DIA(PORT_RW_WR_DATA[7:6]), .DPRA0(PORT_R_ADDR[0]),
.DIB(PORT_RW_WR_DATA[7:6]), .DPRA1(PORT_R_ADDR[1]),
.DIC(PORT_RW_WR_DATA[5:4]), .DPRA2(PORT_R_ADDR[2]),
.DID(PORT_RW_WR_DATA[5:4]), .DPRA3(PORT_R_ADDR[3]),
.DIE(PORT_RW_WR_DATA[3:2]), .DPRA4(PORT_R_ADDR[4]),
.DIF(PORT_RW_WR_DATA[3:2]),
.DIG(PORT_RW_WR_DATA[1:0]),
.DIH(PORT_RW_WR_DATA[1:0]),
.ADDRA(PORT_R_ADDR),
.ADDRB(PORT_RW_ADDR),
.ADDRC(PORT_R_ADDR),
.ADDRD(PORT_RW_ADDR),
.ADDRE(PORT_R_ADDR),
.ADDRF(PORT_RW_ADDR),
.ADDRG(PORT_R_ADDR),
.ADDRH(PORT_RW_ADDR),
.WE(PORT_RW_WR_EN),
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN),
); );
6: begin 6:
genvar i; if (PORT_RW_CLK_POL)
for (i = 0; i < WIDTH; i = i + 1) RAMD64X1
if (BITS_USED[i])
RAM64X1D
#( #(
.INIT(init_slice(i)), .INIT(INIT),
) )
slice _TECHMAP_REPLACE_
( (
.DPO(PORT_R_RD_DATA),
.SPO(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]), .A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]), .A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]), .A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]), .A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]), .A4(PORT_RW_ADDR[4]),
.A5(PORT_RW_ADDR[5]), .A5(PORT_RW_ADDR[5]),
.D(PORT_RW_WR_DATA[i]), .D(PORT_RW_WR_DATA),
.SPO(PORT_RW_RD_DATA[i]), .DPRA0(PORT_R_ADDR[0]),
.WE(PORT_RW_WR_EN), .DPRA1(PORT_R_ADDR[1]),
.WCLK(PORT_RW_CLK), .DPRA2(PORT_R_ADDR[2]),
.DPRA3(PORT_R_ADDR[3]),
.DPRA4(PORT_R_ADDR[4]),
.DPRA5(PORT_R_ADDR[5]),
.WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN),
);
else
RAMD64X1_N
#(
.INIT(INIT),
)
_TECHMAP_REPLACE_
(
.DPO(PORT_R_RD_DATA),
.SPO(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]),
.A5(PORT_RW_ADDR[5]),
.D(PORT_RW_WR_DATA),
.DPRA0(PORT_R_ADDR[0]), .DPRA0(PORT_R_ADDR[0]),
.DPRA1(PORT_R_ADDR[1]), .DPRA1(PORT_R_ADDR[1]),
.DPRA2(PORT_R_ADDR[2]), .DPRA2(PORT_R_ADDR[2]),
.DPRA3(PORT_R_ADDR[3]), .DPRA3(PORT_R_ADDR[3]),
.DPRA4(PORT_R_ADDR[4]), .DPRA4(PORT_R_ADDR[4]),
.DPRA5(PORT_R_ADDR[5]), .DPRA5(PORT_R_ADDR[5]),
.DPO(PORT_R_RD_DATA[i]),
);
end
7: begin
genvar i;
for (i = 0; i < WIDTH; i = i + 1)
if (BITS_USED[i])
RAM128X1D
#(
.INIT(init_slice(i)),
)
slice
(
.A(PORT_RW_ADDR),
.D(PORT_RW_WR_DATA[i]),
.SPO(PORT_RW_RD_DATA[i]),
.WE(PORT_RW_WR_EN),
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.DPRA(PORT_R_ADDR),
.DPO(PORT_R_RD_DATA[i]),
);
end
8: begin
genvar i;
for (i = 0; i < WIDTH; i = i + 1)
if (BITS_USED[i])
RAM256X1D
#(
.INIT(init_slice(i)),
)
slice
(
.A(PORT_RW_ADDR),
.D(PORT_RW_WR_DATA[i]),
.SPO(PORT_RW_RD_DATA[i]),
.WE(PORT_RW_WR_EN), .WE(PORT_RW_WR_EN),
.WCLK(PORT_RW_CLK),
.DPRA(PORT_R_ADDR),
.DPO(PORT_R_RD_DATA[i]),
); );
end
default: default:
$error("invalid OPTION_ABITS/WIDTH combination"); $error("invalid OPTION_ABITS");
endcase
endgenerate
endmodule
module $__ANALOGDEVICES_LUTRAM_SDP_ (...);
parameter INIT = 0;
parameter OPTION_ABITS = 5;
parameter WIDTH = 6;
parameter BITS_USED = 0;
input [WIDTH-1:0] PORT_W_WR_DATA;
input [OPTION_ABITS-1:0] PORT_W_ADDR;
input PORT_W_WR_EN;
input PORT_W_CLK;
output [WIDTH-1:0] PORT_R_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R_ADDR;
function [(1 << OPTION_ABITS)-1:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
init_slice[i] = INIT[i * WIDTH + idx];
endfunction
function [(2 << OPTION_ABITS)-1:0] init_slice2;
input integer idx;
integer i;
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
endfunction
generate
case (OPTION_ABITS)
5: if (WIDTH == 6)
RAM32M
#(
.INIT_C(init_slice2(0)),
.INIT_B(init_slice2(1)),
.INIT_A(init_slice2(2)),
)
_TECHMAP_REPLACE_
(
.DOA(PORT_R_RD_DATA[5:4]),
.DOB(PORT_R_RD_DATA[3:2]),
.DOC(PORT_R_RD_DATA[1:0]),
.DIA(PORT_W_WR_DATA[5:4]),
.DIB(PORT_W_WR_DATA[3:2]),
.DIC(PORT_W_WR_DATA[1:0]),
.ADDRA(PORT_R_ADDR),
.ADDRB(PORT_R_ADDR),
.ADDRC(PORT_R_ADDR),
.ADDRD(PORT_W_ADDR),
.WE(PORT_W_WR_EN),
.WCLK(PORT_W_CLK),
);
else
RAM32M16
#(
.INIT_G(init_slice2(0)),
.INIT_F(init_slice2(1)),
.INIT_E(init_slice2(2)),
.INIT_D(init_slice2(3)),
.INIT_C(init_slice2(4)),
.INIT_B(init_slice2(5)),
.INIT_A(init_slice2(6)),
)
_TECHMAP_REPLACE_
(
.DOA(PORT_R_RD_DATA[13:12]),
.DOB(PORT_R_RD_DATA[11:10]),
.DOC(PORT_R_RD_DATA[9:8]),
.DOD(PORT_R_RD_DATA[7:6]),
.DOE(PORT_R_RD_DATA[5:4]),
.DOF(PORT_R_RD_DATA[3:2]),
.DOG(PORT_R_RD_DATA[1:0]),
.DIA(PORT_W_WR_DATA[13:12]),
.DIB(PORT_W_WR_DATA[11:10]),
.DIC(PORT_W_WR_DATA[9:8]),
.DID(PORT_W_WR_DATA[7:6]),
.DIE(PORT_W_WR_DATA[5:4]),
.DIF(PORT_W_WR_DATA[3:2]),
.DIG(PORT_W_WR_DATA[1:0]),
.ADDRA(PORT_R_ADDR),
.ADDRB(PORT_R_ADDR),
.ADDRC(PORT_R_ADDR),
.ADDRD(PORT_R_ADDR),
.ADDRE(PORT_R_ADDR),
.ADDRF(PORT_R_ADDR),
.ADDRG(PORT_R_ADDR),
.ADDRH(PORT_W_ADDR),
.WE(PORT_W_WR_EN),
.WCLK(PORT_W_CLK),
);
6: if (WIDTH == 3)
RAM64M
#(
.INIT_C(init_slice(0)),
.INIT_B(init_slice(1)),
.INIT_A(init_slice(2)),
)
_TECHMAP_REPLACE_
(
.DOA(PORT_R_RD_DATA[2]),
.DOB(PORT_R_RD_DATA[1]),
.DOC(PORT_R_RD_DATA[0]),
.DIA(PORT_W_WR_DATA[2]),
.DIB(PORT_W_WR_DATA[1]),
.DIC(PORT_W_WR_DATA[0]),
.ADDRA(PORT_R_ADDR),
.ADDRB(PORT_R_ADDR),
.ADDRC(PORT_R_ADDR),
.ADDRD(PORT_W_ADDR),
.WE(PORT_W_WR_EN),
.WCLK(PORT_W_CLK),
);
else
RAM64M8
#(
.INIT_G(init_slice(0)),
.INIT_F(init_slice(1)),
.INIT_E(init_slice(2)),
.INIT_D(init_slice(3)),
.INIT_C(init_slice(4)),
.INIT_B(init_slice(5)),
.INIT_A(init_slice(6)),
)
_TECHMAP_REPLACE_
(
.DOA(PORT_R_RD_DATA[6]),
.DOB(PORT_R_RD_DATA[5]),
.DOC(PORT_R_RD_DATA[4]),
.DOD(PORT_R_RD_DATA[3]),
.DOE(PORT_R_RD_DATA[2]),
.DOF(PORT_R_RD_DATA[1]),
.DOG(PORT_R_RD_DATA[0]),
.DIA(PORT_W_WR_DATA[6]),
.DIB(PORT_W_WR_DATA[5]),
.DIC(PORT_W_WR_DATA[4]),
.DID(PORT_W_WR_DATA[3]),
.DIE(PORT_W_WR_DATA[2]),
.DIF(PORT_W_WR_DATA[1]),
.DIG(PORT_W_WR_DATA[0]),
.ADDRA(PORT_R_ADDR),
.ADDRB(PORT_R_ADDR),
.ADDRC(PORT_R_ADDR),
.ADDRD(PORT_R_ADDR),
.ADDRE(PORT_R_ADDR),
.ADDRF(PORT_R_ADDR),
.ADDRG(PORT_R_ADDR),
.ADDRH(PORT_W_ADDR),
.WE(PORT_W_WR_EN),
.WCLK(PORT_W_CLK),
);
default:
$error("invalid OPTION_ABITS/WIDTH combination");
endcase endcase
endgenerate endgenerate