diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v
index 9a64f7454..8dac86f94 100644
--- a/techlibs/analogdevices/cells_sim.v
+++ b/techlibs/analogdevices/cells_sim.v
@@ -583,107 +583,60 @@ endmodule
 
 // Single port.
 
-module RAM16X1S (
-  output O,
-  input A0, A1, A2, A3,
-  input D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [15:0] INIT = 16'h0000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [3:0] a = {A3, A2, A1, A0};
-  reg [15:0] mem = INIT;
-  assign O = mem[a];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[a] <= D;
-endmodule
-
-module RAM16X1S_1 (
-  output O,
-  input A0, A1, A2, A3,
-  input D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [15:0] INIT = 16'h0000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [3:0] a = {A3, A2, A1, A0};
-  reg [15:0] mem = INIT;
-  assign O = mem[a];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(negedge clk) if (WE) mem[a] <= D;
-endmodule
-
-module RAM32X1S (
+module RAMS32X1 (
   output O,
   input A0, A1, A2, A3, A4,
   input D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input WCLK,
   input WE
 );
   parameter [31:0] INIT = 32'h00000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   wire [4:0] a = {A4, A3, A2, A1, A0};
   reg [31:0] mem = INIT;
   assign O = mem[a];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[a] <= D;
+  always @(posedge WCLK) if (WE) mem[a] <= D;
 endmodule
 
-module RAM32X1S_1 (
+module RAMS32X1_N (
   output O,
   input A0, A1, A2, A3, A4,
   input D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input WCLK,
   input WE
 );
   parameter [31:0] INIT = 32'h00000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   wire [4:0] a = {A4, A3, A2, A1, A0};
   reg [31:0] mem = INIT;
   assign O = mem[a];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(negedge clk) if (WE) mem[a] <= D;
+  always @(negedge WCLK) if (WE) mem[a] <= D;
 endmodule
 
-module RAM64X1S (
+module RAMS64X1 (
   output O,
   input A0, A1, A2, A3, A4, A5,
   input D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input WCLK,
   input WE
 );
   parameter [63:0] INIT = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
   reg [63:0] mem = INIT;
   assign O = mem[a];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[a] <= D;
+  always @(posedge WCLK) if (WE) mem[a] <= D;
 endmodule
 
-module RAM64X1S_1 (
+module RAMS64X1_N (
   output O,
   input A0, A1, A2, A3, A4, A5,
   input D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input WCLK,
   input WE
 );
   parameter [63:0] INIT = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
   reg [63:0] mem = INIT;
   assign O = mem[a];
@@ -691,1082 +644,78 @@ module RAM64X1S_1 (
   always @(negedge clk) if (WE) mem[a] <= D;
 endmodule
 
-module RAM128X1S (
-  output O,
-  input A0, A1, A2, A3, A4, A5, A6,
-  input D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [127:0] INIT = 128'h00000000000000000000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
-  reg [127:0] mem = INIT;
-  assign O = mem[a];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[a] <= D;
-endmodule
-
-module RAM128X1S_1 (
-  output O,
-  input A0, A1, A2, A3, A4, A5, A6,
-  input D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [127:0] INIT = 128'h00000000000000000000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
-  reg [127:0] mem = INIT;
-  assign O = mem[a];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(negedge clk) if (WE) mem[a] <= D;
-endmodule
-
-module RAM256X1S (
-  output O,
-  input [7:0] A,
-  input D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [255:0] INIT = 256'h0;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [255:0] mem = INIT;
-  assign O = mem[A];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[A] <= D;
-endmodule
-
-module RAM512X1S (
-  output O,
-  input [8:0] A,
-  input D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [511:0] INIT = 512'h0;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [511:0] mem = INIT;
-  assign O = mem[A];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[A] <= D;
-endmodule
-
-// Single port, wide.
-
-module RAM16X2S (
-  output O0, O1,
-  input A0, A1, A2, A3,
-  input D0, D1,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [15:0] INIT_00 = 16'h0000;
-  parameter [15:0] INIT_01 = 16'h0000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [3:0] a = {A3, A2, A1, A0};
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  reg [15:0] mem0 = INIT_00;
-  reg [15:0] mem1 = INIT_01;
-  assign O0 = mem0[a];
-  assign O1 = mem1[a];
-  always @(posedge clk)
-    if (WE) begin
-      mem0[a] <= D0;
-      mem1[a] <= D1;
-    end
-endmodule
-
-module RAM32X2S (
-  output O0, O1,
-  input A0, A1, A2, A3, A4,
-  input D0, D1,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [31:0] INIT_00 = 32'h00000000;
-  parameter [31:0] INIT_01 = 32'h00000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [4:0] a = {A4, A3, A2, A1, A0};
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  reg [31:0] mem0 = INIT_00;
-  reg [31:0] mem1 = INIT_01;
-  assign O0 = mem0[a];
-  assign O1 = mem1[a];
-  always @(posedge clk)
-    if (WE) begin
-      mem0[a] <= D0;
-      mem1[a] <= D1;
-    end
-endmodule
-
-module RAM64X2S (
-  output O0, O1,
-  input A0, A1, A2, A3, A4, A5,
-  input D0, D1,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [63:0] INIT_00 = 64'h0000000000000000;
-  parameter [63:0] INIT_01 = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [5:0] a = {A5, A3, A2, A1, A0};
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  reg [63:0] mem0 = INIT_00;
-  reg [63:0] mem1 = INIT_01;
-  assign O0 = mem0[a];
-  assign O1 = mem1[a];
-  always @(posedge clk)
-    if (WE) begin
-      mem0[a] <= D0;
-      mem1[a] <= D1;
-    end
-endmodule
-
-module RAM16X4S (
-  output O0, O1, O2, O3,
-  input A0, A1, A2, A3,
-  input D0, D1, D2, D3,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [15:0] INIT_00 = 16'h0000;
-  parameter [15:0] INIT_01 = 16'h0000;
-  parameter [15:0] INIT_02 = 16'h0000;
-  parameter [15:0] INIT_03 = 16'h0000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [3:0] a = {A3, A2, A1, A0};
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  reg [15:0] mem0 = INIT_00;
-  reg [15:0] mem1 = INIT_01;
-  reg [15:0] mem2 = INIT_02;
-  reg [15:0] mem3 = INIT_03;
-  assign O0 = mem0[a];
-  assign O1 = mem1[a];
-  assign O2 = mem2[a];
-  assign O3 = mem3[a];
-  always @(posedge clk)
-    if (WE) begin
-      mem0[a] <= D0;
-      mem1[a] <= D1;
-      mem2[a] <= D2;
-      mem3[a] <= D3;
-    end
-endmodule
-
-module RAM32X4S (
-  output O0, O1, O2, O3,
-  input A0, A1, A2, A3, A4,
-  input D0, D1, D2, D3,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [31:0] INIT_00 = 32'h00000000;
-  parameter [31:0] INIT_01 = 32'h00000000;
-  parameter [31:0] INIT_02 = 32'h00000000;
-  parameter [31:0] INIT_03 = 32'h00000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [4:0] a = {A4, A3, A2, A1, A0};
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  reg [31:0] mem0 = INIT_00;
-  reg [31:0] mem1 = INIT_01;
-  reg [31:0] mem2 = INIT_02;
-  reg [31:0] mem3 = INIT_03;
-  assign O0 = mem0[a];
-  assign O1 = mem1[a];
-  assign O2 = mem2[a];
-  assign O3 = mem3[a];
-  always @(posedge clk)
-    if (WE) begin
-      mem0[a] <= D0;
-      mem1[a] <= D1;
-      mem2[a] <= D2;
-      mem3[a] <= D3;
-    end
-endmodule
-
-module RAM16X8S (
-  output [7:0] O,
-  input A0, A1, A2, A3,
-  input [7:0] D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [15:0] INIT_00 = 16'h0000;
-  parameter [15:0] INIT_01 = 16'h0000;
-  parameter [15:0] INIT_02 = 16'h0000;
-  parameter [15:0] INIT_03 = 16'h0000;
-  parameter [15:0] INIT_04 = 16'h0000;
-  parameter [15:0] INIT_05 = 16'h0000;
-  parameter [15:0] INIT_06 = 16'h0000;
-  parameter [15:0] INIT_07 = 16'h0000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [3:0] a = {A3, A2, A1, A0};
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  reg [15:0] mem0 = INIT_00;
-  reg [15:0] mem1 = INIT_01;
-  reg [15:0] mem2 = INIT_02;
-  reg [15:0] mem3 = INIT_03;
-  reg [15:0] mem4 = INIT_04;
-  reg [15:0] mem5 = INIT_05;
-  reg [15:0] mem6 = INIT_06;
-  reg [15:0] mem7 = INIT_07;
-  assign O[0] = mem0[a];
-  assign O[1] = mem1[a];
-  assign O[2] = mem2[a];
-  assign O[3] = mem3[a];
-  assign O[4] = mem4[a];
-  assign O[5] = mem5[a];
-  assign O[6] = mem6[a];
-  assign O[7] = mem7[a];
-  always @(posedge clk)
-    if (WE) begin
-      mem0[a] <= D[0];
-      mem1[a] <= D[1];
-      mem2[a] <= D[2];
-      mem3[a] <= D[3];
-      mem4[a] <= D[4];
-      mem5[a] <= D[5];
-      mem6[a] <= D[6];
-      mem7[a] <= D[7];
-    end
-endmodule
-
-module RAM32X8S (
-  output [7:0] O,
-  input A0, A1, A2, A3, A4,
-  input [7:0] D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [31:0] INIT_00 = 32'h00000000;
-  parameter [31:0] INIT_01 = 32'h00000000;
-  parameter [31:0] INIT_02 = 32'h00000000;
-  parameter [31:0] INIT_03 = 32'h00000000;
-  parameter [31:0] INIT_04 = 32'h00000000;
-  parameter [31:0] INIT_05 = 32'h00000000;
-  parameter [31:0] INIT_06 = 32'h00000000;
-  parameter [31:0] INIT_07 = 32'h00000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [4:0] a = {A4, A3, A2, A1, A0};
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  reg [31:0] mem0 = INIT_00;
-  reg [31:0] mem1 = INIT_01;
-  reg [31:0] mem2 = INIT_02;
-  reg [31:0] mem3 = INIT_03;
-  reg [31:0] mem4 = INIT_04;
-  reg [31:0] mem5 = INIT_05;
-  reg [31:0] mem6 = INIT_06;
-  reg [31:0] mem7 = INIT_07;
-  assign O[0] = mem0[a];
-  assign O[1] = mem1[a];
-  assign O[2] = mem2[a];
-  assign O[3] = mem3[a];
-  assign O[4] = mem4[a];
-  assign O[5] = mem5[a];
-  assign O[6] = mem6[a];
-  assign O[7] = mem7[a];
-  always @(posedge clk)
-    if (WE) begin
-      mem0[a] <= D[0];
-      mem1[a] <= D[1];
-      mem2[a] <= D[2];
-      mem3[a] <= D[3];
-      mem4[a] <= D[4];
-      mem5[a] <= D[5];
-      mem6[a] <= D[6];
-      mem7[a] <= D[7];
-    end
-endmodule
-
 // Dual port.
 
-(* abc9_box, lib_whitebox *)
-module RAM32X1D (
+module RAMD32X1 (
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
   input  WE,
   input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
   parameter INIT = 32'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
   wire [4:0] a = {A4, A3, A2, A1, A0};
   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
   reg [31:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[a] <= D;
-  specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
-    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
-    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-    $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
-    $setup(A0, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-    $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
-    $setup(A1, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-    $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
-    $setup(A2, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-    $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
-    $setup(A3, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-    $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
-    $setup(A4, posedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (!IS_WCLK_INVERTED) (posedge WCLK => (SPO : D))    = 1153;
-    if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153;
-    if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D))    = 1153;
-    if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153;
-    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
-    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
-    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
-    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
-    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
-  endspecify
+  always @(posedge WCLK) if (WE) mem[a] <= D;
 endmodule
 
-(* abc9_box, lib_whitebox *)
-module RAM32X1D_1 (
+module RAMD32X1_N (
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
   input  WE,
-  input  A0,
-  input  A1,
-  input  A2,
-  input  A3,
-  input  A4,
+  input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
   parameter INIT = 32'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
   wire [4:0] a = {A4, A3, A2, A1, A0};
   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
   reg [31:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(negedge clk) if (WE) mem[a] <= D;
-  specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , negedge WCLK &&& WE, 453);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-    $setup(WE, negedge WCLK, 654);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-    $setup(A0, negedge WCLK &&& WE, 245);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-    $setup(A1, negedge WCLK &&& WE, 208);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-    $setup(A2, negedge WCLK &&& WE, 147);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-    $setup(A3, negedge WCLK &&& WE, 68);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-    $setup(A4, negedge WCLK &&& WE, 66);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => (SPO : D))    = 1153;
-    if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
-    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
-    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
-    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
-    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
-    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
-  endspecify
+  always @(negedge WCLK) if (WE) mem[a] <= D;
 endmodule
 
-(* abc9_box, lib_whitebox *)
-module RAM64X1D (
+module RAMD64X1 (
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
   input  WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
   parameter INIT = 64'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
   reg [63:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[a] <= D;
-  specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
-    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
-    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-    $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
-    $setup(A0, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-    $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
-    $setup(A1, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-    $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
-    $setup(A2, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-    $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
-    $setup(A3, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-    $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
-    $setup(A4, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-    $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
-    $setup(A5, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D))    = 1153;
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D))    = 1153;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
-    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
-    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
-    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
-    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
-    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
-    (A5 => SPO) = 127; (DPRA5 => DPO) = 127;
-  endspecify
+  always @(posedge WCLK) if (WE) mem[a] <= D;
 endmodule
 
-module RAM64X1D_1 (
+module RAMD64X1_N (
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
   input  WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
   parameter INIT = 64'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
   reg [63:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(negedge clk) if (WE) mem[a] <= D;
-  specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , negedge WCLK &&& WE, 453);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-    $setup(WE, negedge WCLK, 654);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-    $setup(A0, negedge WCLK &&& WE, 362);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-    $setup(A1, negedge WCLK &&& WE, 245);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-    $setup(A2, negedge WCLK &&& WE, 208);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-    $setup(A3, negedge WCLK &&& WE, 147);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-    $setup(A4, negedge WCLK &&& WE, 68);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-    $setup(A5, negedge WCLK &&& WE, 66);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => (SPO : D))    = 1153;
-    if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
-    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
-    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
-    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
-    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
-    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
-    (A5 => SPO) = 127; (DPRA5 => DPO) = 127;
-  endspecify
-endmodule
-
-(* abc9_box, lib_whitebox *)
-module RAM128X1D (
-  output       DPO, SPO,
-  input        D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input        WCLK,
-  input        WE,
-  input  [6:0] A,
-  input  [6:0] DPRA
-);
-  parameter INIT = 128'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  reg [127:0] mem = INIT;
-  assign SPO = mem[A];
-  assign DPO = mem[DPRA];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[A] <= D;
-  specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
-    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
-    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
-    $setup(A[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 616);
-    $setup(A[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 616);
-    $setup(A[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
-    $setup(A[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
-    $setup(A[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
-    $setup(A[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
-    $setup(A[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
-    $setup(A[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
-    $setup(A[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
-    $setup(A[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
-    $setup(A[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
-    $setup(A[5], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
-    $setup(A[6], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
-    $setup(A[6], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
-`ifndef __ICARUS__
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D))    = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
-    (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    (A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    (A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    (A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    (A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
-    (DPRA[0] => DPO) = 642 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */;
-    (DPRA[1] => DPO) = 631 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */;
-    (DPRA[2] => DPO) = 472 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */;
-    (DPRA[3] => DPO) = 407 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */;
-    (DPRA[4] => DPO) = 238 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */;
-    (DPRA[5] => DPO) = 127 + 223 /* to cross LUTMUX7 */ + 174 /* CMUX */;
-    (DPRA[6] => DPO) = 0 + 296 /* to select LUTMUX7 */ + 174 /* CMUX */;
-`endif
-  endspecify
-endmodule
-
-module RAM256X1D (
-  output DPO, SPO,
-  input        D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input        WCLK,
-  input        WE,
-  input  [7:0] A, DPRA
-);
-  parameter INIT = 256'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  reg [255:0] mem = INIT;
-  assign SPO = mem[A];
-  assign DPO = mem[DPRA];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk) if (WE) mem[A] <= D;
-endmodule
-
-// Multi port.
-
-(* abc9_box, lib_whitebox *)
-module RAM32M (
-  output [1:0] DOA,
-  output [1:0] DOB,
-  output [1:0] DOC,
-  output [1:0] DOD,
-  input  [4:0] ADDRA, ADDRB, ADDRC,
-  input  [4:0] ADDRD,
-  input  [1:0] DIA,
-  input  [1:0] DIB,
-  input  [1:0] DIC,
-  input  [1:0] DID,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input        WCLK,
-  input        WE
-);
-  parameter [63:0] INIT_A = 64'h0000000000000000;
-  parameter [63:0] INIT_B = 64'h0000000000000000;
-  parameter [63:0] INIT_C = 64'h0000000000000000;
-  parameter [63:0] INIT_D = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [63:0] mem_a = INIT_A;
-  reg [63:0] mem_b = INIT_B;
-  reg [63:0] mem_c = INIT_C;
-  reg [63:0] mem_d = INIT_D;
-  assign DOA = mem_a[2*ADDRA+:2];
-  assign DOB = mem_b[2*ADDRB+:2];
-  assign DOC = mem_c[2*ADDRC+:2];
-  assign DOD = mem_d[2*ADDRD+:2];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk)
-    if (WE) begin
-      mem_a[2*ADDRD+:2] <= DIA;
-      mem_b[2*ADDRD+:2] <= DIB;
-      mem_c[2*ADDRD+:2] <= DIC;
-      mem_d[2*ADDRD+:2] <= DID;
-    end
-  specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
-    $setup(ADDRD[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
-    $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
-    $setup(ADDRD[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
-    $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
-    $setup(ADDRD[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
-    $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
-    $setup(ADDRD[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
-    $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
-    $setup(ADDRD[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-    $setup(DIA[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
-    $setup(DIA[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
-    $setup(DIA[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
-    $setup(DIA[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 384);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-    $setup(DIB[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 461);
-    $setup(DIB[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 461);
-    $setup(DIB[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
-    $setup(DIB[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 354);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-    $setup(DIC[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 457);
-    $setup(DIC[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 457);
-    $setup(DIC[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
-    $setup(DIC[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 375);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-    $setup(DID[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
-    $setup(DID[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 310);
-    $setup(DID[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 334);
-    $setup(DID[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 334);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
-    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
-    (ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642;
-    (ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631;
-    (ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472;
-    (ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407;
-    (ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238;
-  endspecify
-endmodule
-
-module RAM32M16 (
-  output [1:0] DOA,
-  output [1:0] DOB,
-  output [1:0] DOC,
-  output [1:0] DOD,
-  output [1:0] DOE,
-  output [1:0] DOF,
-  output [1:0] DOG,
-  output [1:0] DOH,
-  input [4:0] ADDRA,
-  input [4:0] ADDRB,
-  input [4:0] ADDRC,
-  input [4:0] ADDRD,
-  input [4:0] ADDRE,
-  input [4:0] ADDRF,
-  input [4:0] ADDRG,
-  input [4:0] ADDRH,
-  input [1:0] DIA,
-  input [1:0] DIB,
-  input [1:0] DIC,
-  input [1:0] DID,
-  input [1:0] DIE,
-  input [1:0] DIF,
-  input [1:0] DIG,
-  input [1:0] DIH,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [63:0] INIT_A = 64'h0000000000000000;
-  parameter [63:0] INIT_B = 64'h0000000000000000;
-  parameter [63:0] INIT_C = 64'h0000000000000000;
-  parameter [63:0] INIT_D = 64'h0000000000000000;
-  parameter [63:0] INIT_E = 64'h0000000000000000;
-  parameter [63:0] INIT_F = 64'h0000000000000000;
-  parameter [63:0] INIT_G = 64'h0000000000000000;
-  parameter [63:0] INIT_H = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [63:0] mem_a = INIT_A;
-  reg [63:0] mem_b = INIT_B;
-  reg [63:0] mem_c = INIT_C;
-  reg [63:0] mem_d = INIT_D;
-  reg [63:0] mem_e = INIT_E;
-  reg [63:0] mem_f = INIT_F;
-  reg [63:0] mem_g = INIT_G;
-  reg [63:0] mem_h = INIT_H;
-  assign DOA = mem_a[2*ADDRA+:2];
-  assign DOB = mem_b[2*ADDRB+:2];
-  assign DOC = mem_c[2*ADDRC+:2];
-  assign DOD = mem_d[2*ADDRD+:2];
-  assign DOE = mem_e[2*ADDRE+:2];
-  assign DOF = mem_f[2*ADDRF+:2];
-  assign DOG = mem_g[2*ADDRG+:2];
-  assign DOH = mem_h[2*ADDRH+:2];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk)
-    if (WE) begin
-      mem_a[2*ADDRH+:2] <= DIA;
-      mem_b[2*ADDRH+:2] <= DIB;
-      mem_c[2*ADDRH+:2] <= DIC;
-      mem_d[2*ADDRH+:2] <= DID;
-      mem_e[2*ADDRH+:2] <= DIE;
-      mem_f[2*ADDRH+:2] <= DIF;
-      mem_g[2*ADDRH+:2] <= DIG;
-      mem_h[2*ADDRH+:2] <= DIH;
-    end
-endmodule
-
-(* abc9_box, lib_whitebox *)
-module RAM64M (
-  output       DOA,
-  output       DOB,
-  output       DOC,
-  output       DOD,
-  input  [5:0] ADDRA, ADDRB, ADDRC,
-  input  [5:0] ADDRD,
-  input        DIA,
-  input        DIB,
-  input        DIC,
-  input        DID,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input        WCLK,
-  input        WE
-);
-  parameter [63:0] INIT_A = 64'h0000000000000000;
-  parameter [63:0] INIT_B = 64'h0000000000000000;
-  parameter [63:0] INIT_C = 64'h0000000000000000;
-  parameter [63:0] INIT_D = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [63:0] mem_a = INIT_A;
-  reg [63:0] mem_b = INIT_B;
-  reg [63:0] mem_c = INIT_C;
-  reg [63:0] mem_d = INIT_D;
-  assign DOA = mem_a[ADDRA];
-  assign DOB = mem_b[ADDRB];
-  assign DOC = mem_c[ADDRC];
-  assign DOD = mem_d[ADDRD];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk)
-    if (WE) begin
-      mem_a[ADDRD] <= DIA;
-      mem_b[ADDRD] <= DIB;
-      mem_c[ADDRD] <= DIC;
-      mem_d[ADDRD] <= DID;
-    end
-  specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
-    $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
-    $setup(ADDRD[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
-    $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
-    $setup(ADDRD[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
-    $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
-    $setup(ADDRD[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
-    $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
-    $setup(ADDRD[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
-    $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
-    $setup(ADDRD[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
-    $setup(ADDRD[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
-    $setup(ADDRD[5], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-    $setup(DIA, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
-    $setup(DIA, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 384);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-    $setup(DIB, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
-    $setup(DIB, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 354);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-    $setup(DIC, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
-    $setup(DIC, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 375);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-    $setup(DID, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
-    $setup(DID, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 310);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 654);
-    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 654);
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA : DIA)) = 1153;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA : DIA)) = 1153;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB : DIB)) = 1161;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB : DIB)) = 1161;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC : DIC)) = 1158;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC : DIC)) = 1158;
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163;
-    (ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642;
-    (ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631;
-    (ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472;
-    (ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407;
-    (ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238;
-  endspecify
-endmodule
-
-module RAM64M8 (
-  output DOA,
-  output DOB,
-  output DOC,
-  output DOD,
-  output DOE,
-  output DOF,
-  output DOG,
-  output DOH,
-  input [5:0] ADDRA,
-  input [5:0] ADDRB,
-  input [5:0] ADDRC,
-  input [5:0] ADDRD,
-  input [5:0] ADDRE,
-  input [5:0] ADDRF,
-  input [5:0] ADDRG,
-  input [5:0] ADDRH,
-  input DIA,
-  input DIB,
-  input DIC,
-  input DID,
-  input DIE,
-  input DIF,
-  input DIG,
-  input DIH,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE
-);
-  parameter [63:0] INIT_A = 64'h0000000000000000;
-  parameter [63:0] INIT_B = 64'h0000000000000000;
-  parameter [63:0] INIT_C = 64'h0000000000000000;
-  parameter [63:0] INIT_D = 64'h0000000000000000;
-  parameter [63:0] INIT_E = 64'h0000000000000000;
-  parameter [63:0] INIT_F = 64'h0000000000000000;
-  parameter [63:0] INIT_G = 64'h0000000000000000;
-  parameter [63:0] INIT_H = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [63:0] mem_a = INIT_A;
-  reg [63:0] mem_b = INIT_B;
-  reg [63:0] mem_c = INIT_C;
-  reg [63:0] mem_d = INIT_D;
-  reg [63:0] mem_e = INIT_E;
-  reg [63:0] mem_f = INIT_F;
-  reg [63:0] mem_g = INIT_G;
-  reg [63:0] mem_h = INIT_H;
-  assign DOA = mem_a[ADDRA];
-  assign DOB = mem_b[ADDRB];
-  assign DOC = mem_c[ADDRC];
-  assign DOD = mem_d[ADDRD];
-  assign DOE = mem_e[ADDRE];
-  assign DOF = mem_f[ADDRF];
-  assign DOG = mem_g[ADDRG];
-  assign DOH = mem_h[ADDRH];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk)
-    if (WE) begin
-      mem_a[ADDRH] <= DIA;
-      mem_b[ADDRH] <= DIB;
-      mem_c[ADDRH] <= DIC;
-      mem_d[ADDRH] <= DID;
-      mem_e[ADDRH] <= DIE;
-      mem_f[ADDRH] <= DIF;
-      mem_g[ADDRH] <= DIG;
-      mem_h[ADDRH] <= DIH;
-    end
-endmodule
-
-module RAM32X16DR8 (
-  output       DOA,
-  output       DOB,
-  output       DOC,
-  output       DOD,
-  output       DOE,
-  output       DOF,
-  output       DOG,
-  output [1:0] DOH,
-  input  [5:0] ADDRA, ADDRB, ADDRC, ADDRD, ADDRE, ADDRF, ADDRG,
-  input  [4:0] ADDRH,
-  input  [1:0] DIA,
-  input  [1:0] DIB,
-  input  [1:0] DIC,
-  input  [1:0] DID,
-  input  [1:0] DIE,
-  input  [1:0] DIF,
-  input  [1:0] DIG,
-  input  [1:0] DIH,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input        WCLK,
-  input        WE
-);
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h;
-  assign DOA = mem_a[ADDRA];
-  assign DOB = mem_b[ADDRB];
-  assign DOC = mem_c[ADDRC];
-  assign DOD = mem_d[ADDRD];
-  assign DOE = mem_e[ADDRE];
-  assign DOF = mem_f[ADDRF];
-  assign DOG = mem_g[ADDRG];
-  assign DOH = mem_h[2*ADDRH+:2];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk)
-    if (WE) begin
-      mem_a[2*ADDRH+:2] <= DIA;
-      mem_b[2*ADDRH+:2] <= DIB;
-      mem_c[2*ADDRH+:2] <= DIC;
-      mem_d[2*ADDRH+:2] <= DID;
-      mem_e[2*ADDRH+:2] <= DIE;
-      mem_f[2*ADDRH+:2] <= DIF;
-      mem_g[2*ADDRH+:2] <= DIG;
-      mem_h[2*ADDRH+:2] <= DIH;
-    end
-endmodule
-
-module RAM64X8SW (
-  output [7:0] O,
-  input [5:0] A,
-  input D,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_WCLK_INVERTED" *)
-  input WCLK,
-  input WE,
-  input [2:0] WSEL
-);
-  parameter [63:0] INIT_A = 64'h0000000000000000;
-  parameter [63:0] INIT_B = 64'h0000000000000000;
-  parameter [63:0] INIT_C = 64'h0000000000000000;
-  parameter [63:0] INIT_D = 64'h0000000000000000;
-  parameter [63:0] INIT_E = 64'h0000000000000000;
-  parameter [63:0] INIT_F = 64'h0000000000000000;
-  parameter [63:0] INIT_G = 64'h0000000000000000;
-  parameter [63:0] INIT_H = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  reg [63:0] mem_a = INIT_A;
-  reg [63:0] mem_b = INIT_B;
-  reg [63:0] mem_c = INIT_C;
-  reg [63:0] mem_d = INIT_D;
-  reg [63:0] mem_e = INIT_E;
-  reg [63:0] mem_f = INIT_F;
-  reg [63:0] mem_g = INIT_G;
-  reg [63:0] mem_h = INIT_H;
-  assign O[7] = mem_a[A];
-  assign O[6] = mem_b[A];
-  assign O[5] = mem_c[A];
-  assign O[4] = mem_d[A];
-  assign O[3] = mem_e[A];
-  assign O[2] = mem_f[A];
-  assign O[1] = mem_g[A];
-  assign O[0] = mem_h[A];
-  wire clk = WCLK ^ IS_WCLK_INVERTED;
-  always @(posedge clk)
-    if (WE) begin
-      case (WSEL)
-      3'b111: mem_a[A] <= D;
-      3'b110: mem_b[A] <= D;
-      3'b101: mem_c[A] <= D;
-      3'b100: mem_d[A] <= D;
-      3'b011: mem_e[A] <= D;
-      3'b010: mem_f[A] <= D;
-      3'b001: mem_g[A] <= D;
-      3'b000: mem_h[A] <= D;
-      endcase
-    end
-endmodule
-
-// ROM.
-
-module ROM16X1 (
-  output O,
-  input A0, A1, A2, A3
-);
-  parameter [15:0] INIT = 16'h0;
-  assign O = INIT[{A3, A2, A1, A0}];
-endmodule
-
-module ROM32X1 (
-  output O,
-  input A0, A1, A2, A3, A4
-);
-  parameter [31:0] INIT = 32'h0;
-  assign O = INIT[{A4, A3, A2, A1, A0}];
-endmodule
-
-module ROM64X1 (
-  output O,
-  input A0, A1, A2, A3, A4, A5
-);
-  parameter [63:0] INIT = 64'h0;
-  assign O = INIT[{A5, A4, A3, A2, A1, A0}];
-endmodule
-
-module ROM128X1 (
-  output O,
-  input A0, A1, A2, A3, A4, A5, A6
-);
-  parameter [127:0] INIT = 128'h0;
-  assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}];
-endmodule
-
-module ROM256X1 (
-  output O,
-  input A0, A1, A2, A3, A4, A5, A6, A7
-);
-  parameter [255:0] INIT = 256'h0;
-  assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}];
+  always @(posedge WCLK) if (WE) mem[a] <= D;
 endmodule
 
 // Shift registers.
diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt
index ae1c16ebb..3218024bb 100644
--- a/techlibs/analogdevices/lutrams.txt
+++ b/techlibs/analogdevices/lutrams.txt
@@ -4,66 +4,40 @@
 # Single-port RAMs.
 
 ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
-	cost 8;
-	widthscale;
 	option "ABITS" 5 {
+		cost 1;
 		abits 5;
-		widths 8 global;
+		width 1;
 	}
 	option "ABITS" 6 {
+		cost 2;
 		abits 6;
-		widths 4 global;
+		width 1;
 	}
 	init no_undef;
 	prune_rom;
 	port arsw "RW" {
-		clock posedge;
+		clock anyedge;
 	}
 }
 
 # Dual-port RAMs.
 
 ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
-	cost 8;
-	widthscale;
 	option "ABITS" 5 {
+		cost 2;
 		abits 5;
-		widths 4 global;
+		width 1;
 	}
 	option "ABITS" 6 {
+		cost 4;
 		abits 6;
-		widths 2 global;
-	}
-	option "ABITS" 7 {
-		abits 7;
-		widths 1 global;
+		width 1;
 	}
 	init no_undef;
 	prune_rom;
 	port arsw "RW" {
-		clock posedge;
-	}
-	port ar "R" {
-	}
-}
-
-# Simple dual port RAMs.
-
-ram distributed $__ANALOGDEVICES_LUTRAM_SDP_ {
-	cost 8;
-	widthscale 7;
-	option "ABITS" 5 {
-		abits 5;
-		widths 6 global;
-	}
-	option "ABITS" 6 {
-		abits 6;
-		widths 3 global;
-	}
-	init no_undef;
-	prune_rom;
-	port sw "W" {
-		clock posedge;
+		clock anyedge;
 	}
 	port ar "R" {
 	}
diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v
index 2142fdf7c..d12c9ae81 100644
--- a/techlibs/analogdevices/lutrams_map.v
+++ b/techlibs/analogdevices/lutrams_map.v
@@ -6,121 +6,91 @@ module $__ANALOGDEVICES_LUTRAM_SP_ (...);
 
 parameter INIT = 0;
 parameter OPTION_ABITS = 5;
-parameter WIDTH = 8;
-parameter BITS_USED = 0;
+parameter WIDTH = 1;
+parameter PORT_RW_CLK_POL = 1;
 
-output [WIDTH-1:0] PORT_RW_RD_DATA;
-input [WIDTH-1:0] PORT_RW_WR_DATA;
+output PORT_RW_RD_DATA;
+input PORT_RW_WR_DATA;
 input [OPTION_ABITS-1:0] PORT_RW_ADDR;
 input PORT_RW_WR_EN;
 input PORT_RW_CLK;
 
-function [(1 << OPTION_ABITS)-1:0] init_slice;
-	input integer idx;
-	integer i;
-	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
-		init_slice[i] = INIT[i * WIDTH + idx];
-endfunction
-
-function [(2 << OPTION_ABITS)-1:0] init_slice2;
-	input integer idx;
-	integer i;
-	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
-		init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
-endfunction
-
 generate
 case(OPTION_ABITS)
-5: if (WIDTH == 8)
-	RAM32M
+5:
+if (PORT_RW_CLK_POL)
+	RAMS32X1
 	#(
-		.INIT_D(init_slice2(0)),
-		.INIT_C(init_slice2(1)),
-		.INIT_B(init_slice2(2)),
-		.INIT_A(init_slice2(3)),
+		.INIT(INIT),
 	)
 	_TECHMAP_REPLACE_
 	(
-		.DOA(PORT_RW_RD_DATA[7:6]),
-		.DOB(PORT_RW_RD_DATA[5:4]),
-		.DOC(PORT_RW_RD_DATA[3:2]),
-		.DOD(PORT_RW_RD_DATA[1:0]),
-		.DIA(PORT_RW_WR_DATA[7:6]),
-		.DIB(PORT_RW_WR_DATA[5:4]),
-		.DIC(PORT_RW_WR_DATA[3:2]),
-		.DID(PORT_RW_WR_DATA[1:0]),
-		.ADDRA(PORT_RW_ADDR),
-		.ADDRB(PORT_RW_ADDR),
-		.ADDRC(PORT_RW_ADDR),
-		.ADDRD(PORT_RW_ADDR),
-		.WE(PORT_RW_WR_EN),
+		.O(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.D(PORT_RW_WR_DATA),
 		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
 	);
 else
-	RAM32M16
+	RAMS32X1_N
 	#(
-		.INIT_H(init_slice2(0)),
-		.INIT_G(init_slice2(1)),
-		.INIT_F(init_slice2(2)),
-		.INIT_E(init_slice2(3)),
-		.INIT_D(init_slice2(4)),
-		.INIT_C(init_slice2(5)),
-		.INIT_B(init_slice2(6)),
-		.INIT_A(init_slice2(7)),
+		.INIT(INIT),
 	)
 	_TECHMAP_REPLACE_
 	(
-		.DOA(PORT_RW_RD_DATA[15:14]),
-		.DOB(PORT_RW_RD_DATA[13:12]),
-		.DOC(PORT_RW_RD_DATA[11:10]),
-		.DOD(PORT_RW_RD_DATA[9:8]),
-		.DOE(PORT_RW_RD_DATA[7:6]),
-		.DOF(PORT_RW_RD_DATA[5:4]),
-		.DOG(PORT_RW_RD_DATA[3:2]),
-		.DOH(PORT_RW_RD_DATA[1:0]),
-		.DIA(PORT_RW_WR_DATA[15:14]),
-		.DIB(PORT_RW_WR_DATA[13:12]),
-		.DIC(PORT_RW_WR_DATA[11:10]),
-		.DID(PORT_RW_WR_DATA[9:8]),
-		.DIE(PORT_RW_WR_DATA[7:6]),
-		.DIF(PORT_RW_WR_DATA[5:4]),
-		.DIG(PORT_RW_WR_DATA[3:2]),
-		.DIH(PORT_RW_WR_DATA[1:0]),
-		.ADDRA(PORT_RW_ADDR),
-		.ADDRB(PORT_RW_ADDR),
-		.ADDRC(PORT_RW_ADDR),
-		.ADDRD(PORT_RW_ADDR),
-		.ADDRE(PORT_RW_ADDR),
-		.ADDRF(PORT_RW_ADDR),
-		.ADDRG(PORT_RW_ADDR),
-		.ADDRH(PORT_RW_ADDR),
-		.WE(PORT_RW_WR_EN),
+		.O(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.D(PORT_RW_WR_DATA),
 		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
+	);
+6:
+if (PORT_RW_CLK_POL)
+	RAMS64X1
+	#(
+		.INIT(INIT),
+	)
+	_TECHMAP_REPLACE_
+	(
+		.O(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.A5(PORT_RW_ADDR[5]),
+		.D(PORT_RW_WR_DATA),
+		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
+	);
+else
+	RAMS64X1_N
+	#(
+		.INIT(INIT),
+	)
+	_TECHMAP_REPLACE_
+	(
+		.O(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.A5(PORT_RW_ADDR[5]),
+		.D(PORT_RW_WR_DATA),
+		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
 	);
-6: begin
-	genvar i;
-	for (i = 0; i < WIDTH; i = i + 1)
-		if (BITS_USED[i])
-			RAM64X1S
-			#(
-				.INIT(init_slice(i)),
-			)
-			slice
-			(
-				.A0(PORT_RW_ADDR[0]),
-				.A1(PORT_RW_ADDR[1]),
-				.A2(PORT_RW_ADDR[2]),
-				.A3(PORT_RW_ADDR[3]),
-				.A4(PORT_RW_ADDR[4]),
-				.A5(PORT_RW_ADDR[5]),
-				.D(PORT_RW_WR_DATA[i]),
-				.O(PORT_RW_RD_DATA[i]),
-				.WE(PORT_RW_WR_EN),
-				.WCLK(PORT_RW_CLK),
-			);
-end
 default:
-	$error("invalid OPTION_ABITS/WIDTH combination");
+	$error("invalid OPTION_ABITS");
 endcase
 endgenerate
 
@@ -131,328 +101,120 @@ module $__ANALOGDEVICES_LUTRAM_DP_ (...);
 
 parameter INIT = 0;
 parameter OPTION_ABITS = 5;
-parameter WIDTH = 4;
-parameter BITS_USED = 0;
+parameter WIDTH = 1;
+parameter PORT_RW_CLK_POL = 1;
 
-output [WIDTH-1:0] PORT_RW_RD_DATA;
-input [WIDTH-1:0] PORT_RW_WR_DATA;
+output PORT_RW_RD_DATA;
+input PORT_RW_WR_DATA;
 input [OPTION_ABITS-1:0] PORT_RW_ADDR;
 input PORT_RW_WR_EN;
 input PORT_RW_CLK;
 
-output [WIDTH-1:0] PORT_R_RD_DATA;
+input PORT_R_RD_DATA;
 input [OPTION_ABITS-1:0] PORT_R_ADDR;
 
-function [(1 << OPTION_ABITS)-1:0] init_slice;
-	input integer idx;
-	integer i;
-	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
-		init_slice[i] = INIT[i * WIDTH + idx];
-endfunction
-
-function [(2 << OPTION_ABITS)-1:0] init_slice2;
-	input integer idx;
-	integer i;
-	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
-		init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
-endfunction
-
 generate
-case (OPTION_ABITS)
-5: if (WIDTH == 4)
-	RAM32M
+case(OPTION_ABITS)
+5:
+if (PORT_RW_CLK_POL)
+	RAMD32X1
 	#(
-		.INIT_D(init_slice2(0)),
-		.INIT_C(init_slice2(0)),
-		.INIT_B(init_slice2(1)),
-		.INIT_A(init_slice2(1)),
+		.INIT(INIT),
 	)
 	_TECHMAP_REPLACE_
 	(
-		.DOA(PORT_R_RD_DATA[3:2]),
-		.DOB(PORT_RW_RD_DATA[3:2]),
-		.DOC(PORT_R_RD_DATA[1:0]),
-		.DOD(PORT_RW_RD_DATA[1:0]),
-		.DIA(PORT_RW_WR_DATA[3:2]),
-		.DIB(PORT_RW_WR_DATA[3:2]),
-		.DIC(PORT_RW_WR_DATA[1:0]),
-		.DID(PORT_RW_WR_DATA[1:0]),
-		.ADDRA(PORT_R_ADDR),
-		.ADDRB(PORT_RW_ADDR),
-		.ADDRC(PORT_R_ADDR),
-		.ADDRD(PORT_RW_ADDR),
-		.WE(PORT_RW_WR_EN),
+		.DPO(PORT_R_RD_DATA),
+		.SPO(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.D(PORT_RW_WR_DATA),
+		.DPRA0(PORT_R_ADDR[0]),
+		.DPRA1(PORT_R_ADDR[1]),
+		.DPRA2(PORT_R_ADDR[2]),
+		.DPRA3(PORT_R_ADDR[3]),
+		.DPRA4(PORT_R_ADDR[4]),
 		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
 	);
 else
-	RAM32M16
+	RAMD32X1_N
 	#(
-		.INIT_H(init_slice2(0)),
-		.INIT_G(init_slice2(0)),
-		.INIT_F(init_slice2(1)),
-		.INIT_E(init_slice2(1)),
-		.INIT_D(init_slice2(2)),
-		.INIT_C(init_slice2(2)),
-		.INIT_B(init_slice2(3)),
-		.INIT_A(init_slice2(3)),
+		.INIT(INIT),
 	)
 	_TECHMAP_REPLACE_
 	(
-		.DOA(PORT_R_RD_DATA[7:6]),
-		.DOB(PORT_RW_RD_DATA[7:6]),
-		.DOC(PORT_R_RD_DATA[5:4]),
-		.DOD(PORT_RW_RD_DATA[5:4]),
-		.DOE(PORT_R_RD_DATA[3:2]),
-		.DOF(PORT_RW_RD_DATA[3:2]),
-		.DOG(PORT_R_RD_DATA[1:0]),
-		.DOH(PORT_RW_RD_DATA[1:0]),
-		.DIA(PORT_RW_WR_DATA[7:6]),
-		.DIB(PORT_RW_WR_DATA[7:6]),
-		.DIC(PORT_RW_WR_DATA[5:4]),
-		.DID(PORT_RW_WR_DATA[5:4]),
-		.DIE(PORT_RW_WR_DATA[3:2]),
-		.DIF(PORT_RW_WR_DATA[3:2]),
-		.DIG(PORT_RW_WR_DATA[1:0]),
-		.DIH(PORT_RW_WR_DATA[1:0]),
-		.ADDRA(PORT_R_ADDR),
-		.ADDRB(PORT_RW_ADDR),
-		.ADDRC(PORT_R_ADDR),
-		.ADDRD(PORT_RW_ADDR),
-		.ADDRE(PORT_R_ADDR),
-		.ADDRF(PORT_RW_ADDR),
-		.ADDRG(PORT_R_ADDR),
-		.ADDRH(PORT_RW_ADDR),
-		.WE(PORT_RW_WR_EN),
+		.DPO(PORT_R_RD_DATA),
+		.SPO(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.D(PORT_RW_WR_DATA),
+		.DPRA0(PORT_R_ADDR[0]),
+		.DPRA1(PORT_R_ADDR[1]),
+		.DPRA2(PORT_R_ADDR[2]),
+		.DPRA3(PORT_R_ADDR[3]),
+		.DPRA4(PORT_R_ADDR[4]),
 		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
+	);
+6:
+if (PORT_RW_CLK_POL)
+	RAMD64X1
+	#(
+		.INIT(INIT),
+	)
+	_TECHMAP_REPLACE_
+	(
+		.DPO(PORT_R_RD_DATA),
+		.SPO(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.A5(PORT_RW_ADDR[5]),
+		.D(PORT_RW_WR_DATA),
+		.DPRA0(PORT_R_ADDR[0]),
+		.DPRA1(PORT_R_ADDR[1]),
+		.DPRA2(PORT_R_ADDR[2]),
+		.DPRA3(PORT_R_ADDR[3]),
+		.DPRA4(PORT_R_ADDR[4]),
+		.DPRA5(PORT_R_ADDR[5]),
+		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
+	);
+else
+	RAMD64X1_N
+	#(
+		.INIT(INIT),
+	)
+	_TECHMAP_REPLACE_
+	(
+		.DPO(PORT_R_RD_DATA),
+		.SPO(PORT_RW_RD_DATA),
+		.A0(PORT_RW_ADDR[0]),
+		.A1(PORT_RW_ADDR[1]),
+		.A2(PORT_RW_ADDR[2]),
+		.A3(PORT_RW_ADDR[3]),
+		.A4(PORT_RW_ADDR[4]),
+		.A5(PORT_RW_ADDR[5]),
+		.D(PORT_RW_WR_DATA),
+		.DPRA0(PORT_R_ADDR[0]),
+		.DPRA1(PORT_R_ADDR[1]),
+		.DPRA2(PORT_R_ADDR[2]),
+		.DPRA3(PORT_R_ADDR[3]),
+		.DPRA4(PORT_R_ADDR[4]),
+		.DPRA5(PORT_R_ADDR[5]),
+		.WCLK(PORT_RW_CLK),
+		.WE(PORT_RW_WR_EN),
 	);
-6: begin
-	genvar i;
-	for (i = 0; i < WIDTH; i = i + 1)
-		if (BITS_USED[i])
-			RAM64X1D
-			#(
-				.INIT(init_slice(i)),
-			)
-			slice
-			(
-				.A0(PORT_RW_ADDR[0]),
-				.A1(PORT_RW_ADDR[1]),
-				.A2(PORT_RW_ADDR[2]),
-				.A3(PORT_RW_ADDR[3]),
-				.A4(PORT_RW_ADDR[4]),
-				.A5(PORT_RW_ADDR[5]),
-				.D(PORT_RW_WR_DATA[i]),
-				.SPO(PORT_RW_RD_DATA[i]),
-				.WE(PORT_RW_WR_EN),
-				.WCLK(PORT_RW_CLK),
-				.DPRA0(PORT_R_ADDR[0]),
-				.DPRA1(PORT_R_ADDR[1]),
-				.DPRA2(PORT_R_ADDR[2]),
-				.DPRA3(PORT_R_ADDR[3]),
-				.DPRA4(PORT_R_ADDR[4]),
-				.DPRA5(PORT_R_ADDR[5]),
-				.DPO(PORT_R_RD_DATA[i]),
-			);
-end
-7: begin
-	genvar i;
-	for (i = 0; i < WIDTH; i = i + 1)
-		if (BITS_USED[i])
-			RAM128X1D
-			#(
-				.INIT(init_slice(i)),
-			)
-			slice
-			(
-				.A(PORT_RW_ADDR),
-				.D(PORT_RW_WR_DATA[i]),
-				.SPO(PORT_RW_RD_DATA[i]),
-				.WE(PORT_RW_WR_EN),
-				.WCLK(PORT_RW_CLK),
-				.DPRA(PORT_R_ADDR),
-				.DPO(PORT_R_RD_DATA[i]),
-			);
-end
-8: begin
-	genvar i;
-	for (i = 0; i < WIDTH; i = i + 1)
-		if (BITS_USED[i])
-			RAM256X1D
-			#(
-				.INIT(init_slice(i)),
-			)
-			slice
-			(
-				.A(PORT_RW_ADDR),
-				.D(PORT_RW_WR_DATA[i]),
-				.SPO(PORT_RW_RD_DATA[i]),
-				.WE(PORT_RW_WR_EN),
-				.WCLK(PORT_RW_CLK),
-				.DPRA(PORT_R_ADDR),
-				.DPO(PORT_R_RD_DATA[i]),
-			);
-end
 default:
-	$error("invalid OPTION_ABITS/WIDTH combination");
-endcase
-endgenerate
-
-endmodule
-
-
-module $__ANALOGDEVICES_LUTRAM_SDP_ (...);
-
-parameter INIT = 0;
-parameter OPTION_ABITS = 5;
-parameter WIDTH = 6;
-parameter BITS_USED = 0;
-
-input [WIDTH-1:0] PORT_W_WR_DATA;
-input [OPTION_ABITS-1:0] PORT_W_ADDR;
-input PORT_W_WR_EN;
-input PORT_W_CLK;
-
-output [WIDTH-1:0] PORT_R_RD_DATA;
-input [OPTION_ABITS-1:0] PORT_R_ADDR;
-
-function [(1 << OPTION_ABITS)-1:0] init_slice;
-	input integer idx;
-	integer i;
-	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
-		init_slice[i] = INIT[i * WIDTH + idx];
-endfunction
-
-function [(2 << OPTION_ABITS)-1:0] init_slice2;
-	input integer idx;
-	integer i;
-	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
-		init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
-endfunction
-
-generate
-case (OPTION_ABITS)
-5: if (WIDTH == 6)
-	RAM32M
-	#(
-		.INIT_C(init_slice2(0)),
-		.INIT_B(init_slice2(1)),
-		.INIT_A(init_slice2(2)),
-	)
-	_TECHMAP_REPLACE_
-	(
-		.DOA(PORT_R_RD_DATA[5:4]),
-		.DOB(PORT_R_RD_DATA[3:2]),
-		.DOC(PORT_R_RD_DATA[1:0]),
-		.DIA(PORT_W_WR_DATA[5:4]),
-		.DIB(PORT_W_WR_DATA[3:2]),
-		.DIC(PORT_W_WR_DATA[1:0]),
-		.ADDRA(PORT_R_ADDR),
-		.ADDRB(PORT_R_ADDR),
-		.ADDRC(PORT_R_ADDR),
-		.ADDRD(PORT_W_ADDR),
-		.WE(PORT_W_WR_EN),
-		.WCLK(PORT_W_CLK),
-	);
-else
-	RAM32M16
-	#(
-		.INIT_G(init_slice2(0)),
-		.INIT_F(init_slice2(1)),
-		.INIT_E(init_slice2(2)),
-		.INIT_D(init_slice2(3)),
-		.INIT_C(init_slice2(4)),
-		.INIT_B(init_slice2(5)),
-		.INIT_A(init_slice2(6)),
-	)
-	_TECHMAP_REPLACE_
-	(
-		.DOA(PORT_R_RD_DATA[13:12]),
-		.DOB(PORT_R_RD_DATA[11:10]),
-		.DOC(PORT_R_RD_DATA[9:8]),
-		.DOD(PORT_R_RD_DATA[7:6]),
-		.DOE(PORT_R_RD_DATA[5:4]),
-		.DOF(PORT_R_RD_DATA[3:2]),
-		.DOG(PORT_R_RD_DATA[1:0]),
-		.DIA(PORT_W_WR_DATA[13:12]),
-		.DIB(PORT_W_WR_DATA[11:10]),
-		.DIC(PORT_W_WR_DATA[9:8]),
-		.DID(PORT_W_WR_DATA[7:6]),
-		.DIE(PORT_W_WR_DATA[5:4]),
-		.DIF(PORT_W_WR_DATA[3:2]),
-		.DIG(PORT_W_WR_DATA[1:0]),
-		.ADDRA(PORT_R_ADDR),
-		.ADDRB(PORT_R_ADDR),
-		.ADDRC(PORT_R_ADDR),
-		.ADDRD(PORT_R_ADDR),
-		.ADDRE(PORT_R_ADDR),
-		.ADDRF(PORT_R_ADDR),
-		.ADDRG(PORT_R_ADDR),
-		.ADDRH(PORT_W_ADDR),
-		.WE(PORT_W_WR_EN),
-		.WCLK(PORT_W_CLK),
-	);
-6: if (WIDTH == 3)
-	RAM64M
-	#(
-		.INIT_C(init_slice(0)),
-		.INIT_B(init_slice(1)),
-		.INIT_A(init_slice(2)),
-	)
-	_TECHMAP_REPLACE_
-	(
-		.DOA(PORT_R_RD_DATA[2]),
-		.DOB(PORT_R_RD_DATA[1]),
-		.DOC(PORT_R_RD_DATA[0]),
-		.DIA(PORT_W_WR_DATA[2]),
-		.DIB(PORT_W_WR_DATA[1]),
-		.DIC(PORT_W_WR_DATA[0]),
-		.ADDRA(PORT_R_ADDR),
-		.ADDRB(PORT_R_ADDR),
-		.ADDRC(PORT_R_ADDR),
-		.ADDRD(PORT_W_ADDR),
-		.WE(PORT_W_WR_EN),
-		.WCLK(PORT_W_CLK),
-	);
-else
-	RAM64M8
-	#(
-		.INIT_G(init_slice(0)),
-		.INIT_F(init_slice(1)),
-		.INIT_E(init_slice(2)),
-		.INIT_D(init_slice(3)),
-		.INIT_C(init_slice(4)),
-		.INIT_B(init_slice(5)),
-		.INIT_A(init_slice(6)),
-	)
-	_TECHMAP_REPLACE_
-	(
-		.DOA(PORT_R_RD_DATA[6]),
-		.DOB(PORT_R_RD_DATA[5]),
-		.DOC(PORT_R_RD_DATA[4]),
-		.DOD(PORT_R_RD_DATA[3]),
-		.DOE(PORT_R_RD_DATA[2]),
-		.DOF(PORT_R_RD_DATA[1]),
-		.DOG(PORT_R_RD_DATA[0]),
-		.DIA(PORT_W_WR_DATA[6]),
-		.DIB(PORT_W_WR_DATA[5]),
-		.DIC(PORT_W_WR_DATA[4]),
-		.DID(PORT_W_WR_DATA[3]),
-		.DIE(PORT_W_WR_DATA[2]),
-		.DIF(PORT_W_WR_DATA[1]),
-		.DIG(PORT_W_WR_DATA[0]),
-		.ADDRA(PORT_R_ADDR),
-		.ADDRB(PORT_R_ADDR),
-		.ADDRC(PORT_R_ADDR),
-		.ADDRD(PORT_R_ADDR),
-		.ADDRE(PORT_R_ADDR),
-		.ADDRF(PORT_R_ADDR),
-		.ADDRG(PORT_R_ADDR),
-		.ADDRH(PORT_W_ADDR),
-		.WE(PORT_W_WR_EN),
-		.WCLK(PORT_W_CLK),
-	);
-default:
-	$error("invalid OPTION_ABITS/WIDTH combination");
+	$error("invalid OPTION_ABITS");
 endcase
 endgenerate