mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 03:35:40 +00:00
Code Activity

rtlil: set Module* on inner-process AttrObjects at construction

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-05 14:29:40 +02:00
parent f1edb571f2
commit ca632e82c4
4 changed files with 13 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/proc/proc_rom.cc
View file

@ -196,15 +196,18 @@ struct RomWorker
if (abits == GetSize(sw->signal)) {
sw->signal = SigSpec();
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->actions.push_back(SigSig(lhs, rdata));
sw->cases.push_back(cs);
} else {
sw->signal = sw->signal.extract_end(abits);
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
cs->actions.push_back(SigSig(lhs, rdata));
sw->cases.push_back(cs);
RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
cs2->module = module;
cs2->actions.push_back(SigSig(lhs, default_val));
sw->cases.push_back(cs2);
}