diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 5e81cab8a..a8391b6e1 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -689,6 +689,7 @@ struct AST_INTERNAL::ProcessGenerator
 				ast->detectSignWidth(width_hint, sign_hint);
 
 				RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
+				sw->module = current_module;
 				set_src_attr(sw, ast);
 				sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
 				current_case->switches.push_back(sw);
@@ -723,6 +724,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 					RTLIL::CaseRule *backup_case = current_case;
 					current_case = new RTLIL::CaseRule;
+					current_case->module = current_module;
 					pool<RTLIL::SigBit> backup_assigned_bits = std::move(current_case_assigned_bits);
 					current_case_assigned_bits.clear();
 					set_src_attr(current_case, child.get());
@@ -759,12 +761,14 @@ struct AST_INTERNAL::ProcessGenerator
 					last_generated_case->compare.clear();
 			#else
 					default_case = new RTLIL::CaseRule;
+					default_case->module = current_module;
 					addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)));
 					sw->cases.push_back(default_case);
 			#endif
 				} else {
 					if (default_case == nullptr) {
 						default_case = new RTLIL::CaseRule;
+						default_case->module = current_module;
 						addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
 					}
 					sw->cases.push_back(default_case);
diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc
index 9160204ea..664cc7a8c 100644
--- a/frontends/rtlil/rtlil_frontend.cc
+++ b/frontends/rtlil/rtlil_frontend.cc
@@ -838,6 +838,7 @@ struct RTLILFrontendWorker {
 	void parse_switch()
 	{
 		RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
+		rule->module = current_module;
 		rule->signal = parse_sigspec();
 		rule->absorb_attrs(std::move(attrbuf));
 		switch_stack.back()->push_back(rule);
@@ -856,6 +857,7 @@ struct RTLILFrontendWorker {
 
 			expect_keyword("case");
 			RTLIL::CaseRule *case_rule = new RTLIL::CaseRule;
+			case_rule->module = current_module;
 			case_rule->absorb_attrs(std::move(attrbuf));
 			rule->cases.push_back(case_rule);
 			switch_stack.push_back(&case_rule->switches);
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 34ab12a42..f7450d9b9 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1259,6 +1259,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		current_case = &proc->root_case;
 
 		RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
+		sw->module = module;
 		sw->signal = sig_select;
 		current_case->switches.push_back(sw);
 
@@ -1294,6 +1295,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 
 					for (int32_t i = right; i<left; i++) {
 						RTLIL::CaseRule *cs = new RTLIL::CaseRule;
+						cs->module = module;
 						cs->compare.push_back(RTLIL::Const(i,width));
 						cs->actions.push_back(action);
 						sw->cases.push_back(cs);
@@ -1301,12 +1303,14 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 				}
 
 				RTLIL::CaseRule *cs = new RTLIL::CaseRule;
+				cs->module = module;
 				cs->compare.push_back(sel_left);
 				cs->actions.push_back(action);
 				sw->cases.push_back(cs);
 			}
 		}
 		RTLIL::CaseRule *cs_default = new RTLIL::CaseRule;
+		cs_default->module = module;
 		cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default));
 		sw->cases.push_back(cs_default);
 
diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc
index bdf37825d..52a72cdf0 100644
--- a/passes/proc/proc_rom.cc
+++ b/passes/proc/proc_rom.cc
@@ -196,15 +196,18 @@ struct RomWorker
 		if (abits == GetSize(sw->signal)) {
 			sw->signal = SigSpec();
 			RTLIL::CaseRule *cs = new RTLIL::CaseRule;
+			cs->module = module;
 			cs->actions.push_back(SigSig(lhs, rdata));
 			sw->cases.push_back(cs);
 		} else {
 			sw->signal = sw->signal.extract_end(abits);
 			RTLIL::CaseRule *cs = new RTLIL::CaseRule;
+			cs->module = module;
 			cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
 			cs->actions.push_back(SigSig(lhs, rdata));
 			sw->cases.push_back(cs);
 			RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
+			cs2->module = module;
 			cs2->actions.push_back(SigSig(lhs, default_val));
 			sw->cases.push_back(cs2);
 		}