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rtlil: set Module* on inner-process AttrObjects at construction
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4 changed files with 13 additions and 0 deletions
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@ -689,6 +689,7 @@ struct AST_INTERNAL::ProcessGenerator
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ast->detectSignWidth(width_hint, sign_hint);
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RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
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sw->module = current_module;
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set_src_attr(sw, ast);
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sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
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current_case->switches.push_back(sw);
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@ -723,6 +724,7 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::CaseRule *backup_case = current_case;
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current_case = new RTLIL::CaseRule;
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current_case->module = current_module;
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pool<RTLIL::SigBit> backup_assigned_bits = std::move(current_case_assigned_bits);
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current_case_assigned_bits.clear();
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set_src_attr(current_case, child.get());
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@ -759,12 +761,14 @@ struct AST_INTERNAL::ProcessGenerator
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last_generated_case->compare.clear();
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#else
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default_case = new RTLIL::CaseRule;
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default_case->module = current_module;
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addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)));
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sw->cases.push_back(default_case);
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#endif
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} else {
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if (default_case == nullptr) {
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default_case = new RTLIL::CaseRule;
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default_case->module = current_module;
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addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
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}
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sw->cases.push_back(default_case);
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