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VHDL is case insensitive, make sure netlist name is proper

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This commit is contained in:
Miodrag Milanovic 2024-07-18 16:56:52 +02:00
parent 81df8557d9
commit c94aa719d9
1 changed files with 5 additions and 0 deletions
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5
frontends/verific/verific.cc
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@ -58,6 +58,7 @@ USING_YOSYS_NAMESPACE
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
#include "vhdl_file.h" #include "vhdl_file.h"
#include "VhdlIdDef.h"
#include "VhdlUnits.h" #include "VhdlUnits.h"
#include "NameSpace.h" #include "NameSpace.h"
#endif #endif
@ -2817,6 +2818,10 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
if (show_message) if (show_message)
log("Adding VHDL unit '%s' to elaboration queue.\n", name); log("Adding VHDL unit '%s' to elaboration queue.\n", name);
vhdl_units.InsertLast(vhdl_unit); vhdl_units.InsertLast(vhdl_unit);
if (strcmp(name, vhdl_unit->Id()->OrigName()) != 0) {
top_mod_names.erase(name);
top_mod_names.insert(vhdl_unit->Id()->OrigName());
}
continue; continue;
} }
#endif #endif