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wip simlib

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Emil J. Tywoniak 2026-01-12 22:24:24 +01:00
parent 0c7afe8e31
commit c7ea80661d
1 changed files with 11 additions and 5 deletions
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16
techlibs/common/simlib.v
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@ -3259,10 +3259,16 @@ endmodule
//- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
//-
module \$priority (A, Y);
parameter WIDTH = 8;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A & (~A + 1);
parameter WIDTH = 0;
parameter P_WIDTH = 0;
parameter POLARITY = 0;
input [P_WIDTH*WIDTH-1:0] A;
output [P_WIDTH*WIDTH-1:0] Y;
genvar offset;
generate
for (offset = 0; offset < P_WIDTH*WIDTH; offset = offset + P_WIDTH) begin
assign Y[offset : offset+P_WIDTH-1] = POLARITY[offset : offset+P_WIDTH-1] ^ ((A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) & (~(A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) + 1));
end
endgenerate
endmodule