From c7ea80661daaa981421c5bb447d05eb6fb78bdde Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 12 Jan 2026 22:24:24 +0100 Subject: [PATCH] wip simlib --- techlibs/common/simlib.v | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index fcdbab555..1c0e16735 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -3259,10 +3259,16 @@ endmodule //- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set. //- module \$priority (A, Y); -parameter WIDTH = 8; -input [WIDTH-1:0] A; -output [WIDTH-1:0] Y; - -assign Y = A & (~A + 1); + parameter WIDTH = 0; + parameter P_WIDTH = 0; + parameter POLARITY = 0; + input [P_WIDTH*WIDTH-1:0] A; + output [P_WIDTH*WIDTH-1:0] Y; + genvar offset; + generate + for (offset = 0; offset < P_WIDTH*WIDTH; offset = offset + P_WIDTH) begin + assign Y[offset : offset+P_WIDTH-1] = POLARITY[offset : offset+P_WIDTH-1] ^ ((A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) & (~(A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) + 1)); + end + endgenerate endmodule