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URAM mapping : Fix port indexes according to Yosys warnings

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This commit is contained in:
Adrien Prost-Boucle 2025-05-09 15:09:11 +02:00
parent c4a49f0c55
commit c7de531231
1 changed files with 3 additions and 3 deletions
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6
techlibs/xilinx/urams_map.v
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@ -264,7 +264,7 @@ module $__XILINX_URAM_SP_ (...);
.RST_MODE_A(PORT_A_OPTION_RST_MODE), .RST_MODE_A(PORT_A_OPTION_RST_MODE),
.RST_MODE_B(PORT_A_OPTION_RST_MODE), .RST_MODE_B(PORT_A_OPTION_RST_MODE),
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.ADDR_A({10'b0, PORT_A_ADDR, 1'b0}), .ADDR_A({11'b0, PORT_A_ADDR, 1'b0}),
.BWE_A(PORT_A_WR_BE[WR_BE_WIDTH/2-1:0]), .BWE_A(PORT_A_WR_BE[WR_BE_WIDTH/2-1:0]),
.EN_A(PORT_A_CLK_EN), .EN_A(PORT_A_CLK_EN),
.RDB_WR_A(PORT_A_WR_EN), .RDB_WR_A(PORT_A_WR_EN),
@ -274,8 +274,8 @@ module $__XILINX_URAM_SP_ (...);
.DIN_A(DIN_A), .DIN_A(DIN_A),
.DOUT_A(DOUT_A), .DOUT_A(DOUT_A),
.ADDR_B({10'b0, PORT_A_ADDR, 1'b1}), .ADDR_B({11'b0, PORT_A_ADDR, 1'b1}),
.BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH]/2), .BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH/2]),
.EN_B(PORT_A_CLK_EN), .EN_B(PORT_A_CLK_EN),
.RDB_WR_B(PORT_A_WR_EN), .RDB_WR_B(PORT_A_WR_EN),
.INJECT_DBITERR_B(1'b0), .INJECT_DBITERR_B(1'b0),