diff --git a/techlibs/xilinx/urams_map.v b/techlibs/xilinx/urams_map.v
index 6f861143b..c0af64825 100644
--- a/techlibs/xilinx/urams_map.v
+++ b/techlibs/xilinx/urams_map.v
@@ -264,7 +264,7 @@ module $__XILINX_URAM_SP_ (...);
 		.RST_MODE_A(PORT_A_OPTION_RST_MODE),
 		.RST_MODE_B(PORT_A_OPTION_RST_MODE),
 	) _TECHMAP_REPLACE_ (
-		.ADDR_A({10'b0, PORT_A_ADDR, 1'b0}),
+		.ADDR_A({11'b0, PORT_A_ADDR, 1'b0}),
 		.BWE_A(PORT_A_WR_BE[WR_BE_WIDTH/2-1:0]),
 		.EN_A(PORT_A_CLK_EN),
 		.RDB_WR_A(PORT_A_WR_EN),
@@ -274,8 +274,8 @@ module $__XILINX_URAM_SP_ (...);
 		.DIN_A(DIN_A),
 		.DOUT_A(DOUT_A),
 
-		.ADDR_B({10'b0, PORT_A_ADDR, 1'b1}),
-		.BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH]/2),
+		.ADDR_B({11'b0, PORT_A_ADDR, 1'b1}),
+		.BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH/2]),
 		.EN_B(PORT_A_CLK_EN),
 		.RDB_WR_B(PORT_A_WR_EN),
 		.INJECT_DBITERR_B(1'b0),