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https://github.com/YosysHQ/yosys
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wip
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parent
50b63c6481
commit
c7ab9f0300
3 changed files with 78 additions and 16 deletions
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@ -186,7 +186,7 @@ for name, expr in base_cells:
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cells.append([name + "_X", 12, XOR(E, expr)])
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with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf:
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def mkGate(name, cost, expr, max_load=9999, block_delay = 10, fanout_delay = 5):
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def mkGate(name, cost, expr, max_load=9999, block_delay = 422, fanout_delay = 5):
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name = name.replace(" ", "")
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expr = expr.map()
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@ -194,9 +194,22 @@ with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf:
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if expr.isInv(): phase = "INV"
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if expr.isNonInv(): phase = "NONINV"
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expr_genlib = expr.as_genlib_term()
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if "E" in expr_genlib:
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block_delay += 66
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print("", file=glf)
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print("GATE %s %d Y=%s;" % (name, cost, expr.as_genlib_term()), file=glf)
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print("PIN * %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf)
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print("GATE %s %d Y=%s;" % (name, cost, expr_genlib), file=glf)
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if "A" in expr_genlib:
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print("PIN A %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf)
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if "B" in expr_genlib:
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print("PIN B %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf)
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if "C" in expr_genlib:
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print("PIN C %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf)
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if "D" in expr_genlib:
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print("PIN D %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf)
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if "E" in expr_genlib:
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print("PIN E %s 1 %d 66 %d 66 %d" % (phase, max_load, fanout_delay, fanout_delay), file=glf)
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print("GATE $__ZERO 0 Y=CONST0;", file=glf)
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print("GATE $__ONE 0 Y=CONST1;", file=glf)
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for name, cost, expr in cells:
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