From c7ab9f030098d21f2a6157e4ae0945d204a7cc70 Mon Sep 17 00:00:00 2001 From: Lofty Date: Tue, 27 May 2025 09:59:48 +0100 Subject: [PATCH] wip --- techlibs/gatemate/cells_sim.v | 67 ++++++++++++++++++++++---- techlibs/gatemate/make_lut_tree_lib.py | 19 ++++++-- techlibs/gatemate/synth_gatemate.cc | 8 +-- 3 files changed, 78 insertions(+), 16 deletions(-) diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index d930b83f8..86a32bc73 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -237,7 +237,7 @@ module CC_ODDR #( endmodule - +(* abc9_box, lib_whitebox *) module CC_DFF #( parameter [0:0] CLK_INV = 1'b0, parameter [0:0] EN_INV = 1'b0, @@ -252,6 +252,15 @@ module CC_DFF #( input SR, output reg Q ); + specify + if ((~EN_INV && EN) || (EN_INV && ~EN)) (posedge CLK => (Q : D)) = 500; + + $setup(D, posedge CLK, 100); + $setup(EN, posedge CLK, 150); + + if ((~SR_INV && SR) || (SR_INV && ~SR)) (SR => Q) = 150; + endspecify + wire clk, en, sr; assign clk = (CLK_INV) ? ~CLK : CLK; assign en = (EN_INV) ? ~EN : EN; @@ -301,49 +310,71 @@ module CC_DLT #( endmodule - +(* abc9_lut=1 *) module CC_LUT1 ( output O, input I0 ); parameter [1:0] INIT = 0; + specify + (I0 => O) = 453; + endspecify + assign O = I0 ? INIT[1] : INIT[0]; endmodule - +(* abc9_lut=1 *) module CC_LUT2 ( output O, input I0, I1 ); parameter [3:0] INIT = 0; + specify + (I0 => O) = 453; + (I1 => O) = 449; + endspecify + wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; assign O = I0 ? s1[1] : s1[0]; endmodule - +(* abc9_lut=1 *) module CC_LUT3 ( output O, input I0, I1, I2 ); parameter [7:0] INIT = 0; + specify + (I0 => O) = 453; + (I1 => O) = 449; + (I2 => O) = 471; + endspecify + wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; assign O = I0 ? s1[1] : s1[0]; endmodule - +(* abc9_lut=2 *) module CC_LUT4 ( output O, input I0, I1, I2, I3 ); parameter [15:0] INIT = 0; + specify + (I0 => O) = 453; + (I1 => O) = 449; + (I2 => O) = 488; + (I3 => O) = 484; + endspecify + wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; @@ -361,12 +392,21 @@ module CC_MX2 ( endmodule - +(* abc9_box, lib_whitebox *) module CC_MX4 ( input D0, D1, D2, D3, input S0, S1, output Y ); + specify + (D0 => Y) = 453; + (D1 => Y) = 449; + (D2 => Y) = 488; + (D3 => Y) = 484; + (S0 => Y) = 422; + (S1 => Y) = 385; + endspecify + assign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0); @@ -386,11 +426,20 @@ module CC_MX8 ( endmodule - +(* abc9_box, lib_whitebox *) module CC_ADDF ( - input A, B, CI, - output CO, S + input A, B, (* abc9_carry *) input CI, + (* abc9_carry *) output CO, output S ); + specify + (A => CO) = 0; + (B => CO) = 0; + (CI => CO) = 0; + (A => S) = 484; + (B => S) = 449; + (CI => S) = 0; + endspecify + assign {CO, S} = A + B + CI; endmodule diff --git a/techlibs/gatemate/make_lut_tree_lib.py b/techlibs/gatemate/make_lut_tree_lib.py index 25ca88882..bdac872d5 100644 --- a/techlibs/gatemate/make_lut_tree_lib.py +++ b/techlibs/gatemate/make_lut_tree_lib.py @@ -186,7 +186,7 @@ for name, expr in base_cells: cells.append([name + "_X", 12, XOR(E, expr)]) with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf: - def mkGate(name, cost, expr, max_load=9999, block_delay = 10, fanout_delay = 5): + def mkGate(name, cost, expr, max_load=9999, block_delay = 422, fanout_delay = 5): name = name.replace(" ", "") expr = expr.map() @@ -194,9 +194,22 @@ with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf: if expr.isInv(): phase = "INV" if expr.isNonInv(): phase = "NONINV" + expr_genlib = expr.as_genlib_term() + if "E" in expr_genlib: + block_delay += 66 + print("", file=glf) - print("GATE %s %d Y=%s;" % (name, cost, expr.as_genlib_term()), file=glf) - print("PIN * %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf) + print("GATE %s %d Y=%s;" % (name, cost, expr_genlib), file=glf) + if "A" in expr_genlib: + print("PIN A %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf) + if "B" in expr_genlib: + print("PIN B %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf) + if "C" in expr_genlib: + print("PIN C %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf) + if "D" in expr_genlib: + print("PIN D %s 1 %d %d %d %d %d" % (phase, max_load, block_delay, fanout_delay, block_delay, fanout_delay), file=glf) + if "E" in expr_genlib: + print("PIN E %s 1 %d 66 %d 66 %d" % (phase, max_load, fanout_delay, fanout_delay), file=glf) print("GATE $__ZERO 0 Y=CONST0;", file=glf) print("GATE $__ONE 0 Y=CONST1;", file=glf) for name, cost, expr in cells: diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index fa36252f5..e0c5abbd9 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -308,21 +308,21 @@ struct SynthGateMatePass : public ScriptPass if (check_label("map_luts")) { if (luttree || help_mode) { - std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib"; + std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib -script \"+&sweep;&dc2;&nf\""; if (dff) { abc_args += " -dff"; } - run("abc " + abc_args, "(with -luttree)"); + run("abc_new " + abc_args, "(with -luttree)"); run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)"); run("gatemate_foldinv", "(with -luttree)"); run("techmap -map +/gatemate/inv_map.v", "(with -luttree)"); } if (!luttree || help_mode) { - std::string abc_args = " -dress -lut 4"; + std::string abc_args = " -maxlut 4"; if (dff) { abc_args += " -dff"; } - run("abc " + abc_args, "(without -luttree)"); + run("abc9 " + abc_args, "(without -luttree)"); } run("clean"); }