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verilog: specify polarity to be separate token

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This commit is contained in:
Eddie Hung 2020-02-19 11:45:19 -08:00
parent ae409d4d81
commit c6b22f5b7d
2 changed files with 19 additions and 12 deletions
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7
frontends/verilog/verilog_lexer.l
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@ -518,7 +518,12 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
".*" { return TOK_WILDCARD_CONNECT; }
[-+]?[=*]> {
[+-] {
if (!specify_mode) REJECT;
frontend_verilog_yylval.ch = yytext[0];
return TOK_SPECIFY_POL;
}
[=*]> {
if (!specify_mode) REJECT;
yylval->string = new std::string(yytext);
return TOK_SPECIFY_OPER;