From c6b22f5b7db0d7a12b5949ae2c0d3b8a9701764f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 19 Feb 2020 11:45:19 -0800
Subject: [PATCH] verilog: specify polarity to be separate token

---
 frontends/verilog/verilog_lexer.l  |  7 ++++++-
 frontends/verilog/verilog_parser.y | 24 +++++++++++++-----------
 2 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index f6a3ac4db..e10e6114b 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -518,7 +518,12 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 
 ".*" { return TOK_WILDCARD_CONNECT; }
 
-[-+]?[=*]> {
+[+-] {
+    if (!specify_mode) REJECT;
+    frontend_verilog_yylval.ch = yytext[0];
+    return TOK_SPECIFY_POL;
+}
+[=*]> {
 	if (!specify_mode) REJECT;
 	yylval->string = new std::string(yytext);
 	return TOK_SPECIFY_OPER;
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index b4e60b98a..daf34fb1e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -204,6 +204,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
+%token <ch> TOK_SPECIFY_POL
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -236,7 +237,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
 %type <specify_triple_ptr> specify_triple specify_opt_triple
 %type <specify_rise_fall_ptr> specify_rise_fall
 %type <ast> specify_if specify_condition
-%type <ch> specify_edge
+%type <ch> specify_edge specify_polarity
 
 // operator precedence from low to high
 %left OP_LOR
@@ -868,14 +869,21 @@ specify_item_list:
 	specify_item specify_item_list |
 	/* empty */;
 
+specify_polarity:
+    TOK_SPECIFY_POL |
+    /* empty */ {
+        $$ = 0;
+    };
+
 specify_item:
-	specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
+	specify_if '(' specify_edge expr specify_polarity TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
 		AstNode *en_expr = $1;
 		char specify_edge = $3;
 		AstNode *src_expr = $4;
-		string *oper = $5;
-		specify_target *target = $6;
-		specify_rise_fall *timing = $9;
+		char oper_polarity = $5;
+		string *oper = $6;
+		specify_target *target = $7;
+		specify_rise_fall *timing = $10;
 
 		if (specify_edge != 0 && target->dat == nullptr)
 			frontend_verilog_yyerror("Found specify edge but no data spec.\n");
@@ -887,14 +895,8 @@ specify_item:
 		cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
 		SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
 
-		char oper_polarity = 0;
 		char oper_type = oper->at(0);
 
-		if (oper->size() == 3) {
-			oper_polarity = oper->at(0);
-			oper_type = oper->at(1);
-		}
-
 		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
 		cell->children.back()->str = "\\FULL";