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Make Module stop accessing internals of SigSpec

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This commit is contained in:
Robert O'Callahan 2025-10-27 12:41:50 +00:00
parent c9a4c608ce
commit c4f3e61339
2 changed files with 17 additions and 14 deletions
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25
kernel/rtlil.cc
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@ -2657,10 +2657,9 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
RTLIL::Module *mod; RTLIL::Module *mod;
void operator()(RTLIL::SigSpec &sig) void operator()(RTLIL::SigSpec &sig)
{ {
sig.pack(); sig.rewrite_wires([this](RTLIL::Wire *&wire) {
for (auto &c : sig.chunks_) wire = mod->wires_.at(wire->name);
if (c.wire != NULL) });
c.wire = mod->wires_.at(c.wire->name);
} }
}; };
@ -2808,12 +2807,10 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
const pool<RTLIL::Wire*> *wires_p; const pool<RTLIL::Wire*> *wires_p;
void operator()(RTLIL::SigSpec &sig) { void operator()(RTLIL::SigSpec &sig) {
sig.pack(); sig.rewrite_wires([this](RTLIL::Wire *&wire) {
for (auto &c : sig.chunks_) if (wires_p->count(wire))
if (c.wire != NULL && wires_p->count(c.wire)) { wire = module->addWire(stringf("$delete_wire$%d", autoidx++), wire->width);
c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width); });
c.offset = 0;
}
} }
void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) { void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
@ -5151,6 +5148,14 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
} }
} }
void RTLIL::SigSpec::rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewrite)
{
pack();
for (RTLIL::SigChunk &chunk : chunks_)
if (chunk.wire != nullptr)
rewrite(chunk.wire);
}
void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
{ {
if (signal.width_ == 0) if (signal.width_ == 0)

6
kernel/rtlil.h
View file

@ -1251,10 +1251,6 @@ private:
unpack(); unpack();
} }
// Only used by Module::remove(const pool<Wire*> &wires)
// but cannot be more specific as it isn't yet declared
friend struct RTLIL::Module;
public: public:
SigSpec() : width_(0), hash_(0) {} SigSpec() : width_(0), hash_(0) {}
SigSpec(std::initializer_list<RTLIL::SigSpec> parts); SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
@ -1326,6 +1322,8 @@ public:
RTLIL::SigSpec extract(int offset, int length = 1) const; RTLIL::SigSpec extract(int offset, int length = 1) const;
RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
void rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewrite);
RTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; }; RTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };
RTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; }; RTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };