diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index aa4743a87..21a466b42 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2657,10 +2657,9 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 		RTLIL::Module *mod;
 		void operator()(RTLIL::SigSpec &sig)
 		{
-			sig.pack();
-			for (auto &c : sig.chunks_)
-				if (c.wire != NULL)
-					c.wire = mod->wires_.at(c.wire->name);
+			sig.rewrite_wires([this](RTLIL::Wire *&wire) {
+				wire = mod->wires_.at(wire->name);
+			});
 		}
 	};
 
@@ -2808,12 +2807,10 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 		const pool<RTLIL::Wire*> *wires_p;
 
 		void operator()(RTLIL::SigSpec &sig) {
-			sig.pack();
-			for (auto &c : sig.chunks_)
-				if (c.wire != NULL && wires_p->count(c.wire)) {
-					c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
-					c.offset = 0;
-				}
+			sig.rewrite_wires([this](RTLIL::Wire *&wire) {
+				if (wires_p->count(wire))
+					wire = module->addWire(stringf("$delete_wire$%d", autoidx++), wire->width);
+			});
 		}
 
 		void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
@@ -5151,6 +5148,14 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
 	}
 }
 
+void RTLIL::SigSpec::rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewrite)
+{
+	pack();
+	for (RTLIL::SigChunk &chunk : chunks_)
+		if (chunk.wire != nullptr)
+			rewrite(chunk.wire);
+}
+
 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
 {
 	if (signal.width_ == 0)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 394c6f25d..a2be435bd 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1251,10 +1251,6 @@ private:
 			unpack();
 	}
 
-	// Only used by Module::remove(const pool<Wire*> &wires)
-	// but cannot be more specific as it isn't yet declared
-	friend struct RTLIL::Module;
-
 public:
 	SigSpec() : width_(0), hash_(0) {}
 	SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
@@ -1326,6 +1322,8 @@ public:
 	RTLIL::SigSpec extract(int offset, int length = 1) const;
 	RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
 
+	void rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewrite);
+
 	RTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };
 	RTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };