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Make Module stop accessing internals of SigSpec

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This commit is contained in:
Robert O'Callahan 2025-10-27 12:41:50 +00:00
parent c9a4c608ce
commit c4f3e61339
2 changed files with 17 additions and 14 deletions
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25
kernel/rtlil.cc
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@ -2657,10 +2657,9 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
RTLIL::Module *mod;
void operator()(RTLIL::SigSpec &sig)
{
sig.pack();
for (auto &c : sig.chunks_)
if (c.wire != NULL)
c.wire = mod->wires_.at(c.wire->name);
sig.rewrite_wires([this](RTLIL::Wire *&wire) {
wire = mod->wires_.at(wire->name);
});
}
};
@ -2808,12 +2807,10 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
const pool<RTLIL::Wire*> *wires_p;
void operator()(RTLIL::SigSpec &sig) {
sig.pack();
for (auto &c : sig.chunks_)
if (c.wire != NULL && wires_p->count(c.wire)) {
c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
c.offset = 0;
}
sig.rewrite_wires([this](RTLIL::Wire *&wire) {
if (wires_p->count(wire))
wire = module->addWire(stringf("$delete_wire$%d", autoidx++), wire->width);
});
}
void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
@ -5151,6 +5148,14 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
}
}
void RTLIL::SigSpec::rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewrite)
{
pack();
for (RTLIL::SigChunk &chunk : chunks_)
if (chunk.wire != nullptr)
rewrite(chunk.wire);
}
void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
{
if (signal.width_ == 0)