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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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54
techlibs/xilinx/xilinx_srl.cc
View file

@ -30,12 +30,12 @@ void run_fixed(xilinx_srl_pm &pm)
{
auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed;
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), design->twines.unescaped_str(st.first->type));
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_))) {
SigBit Q = cell->getPort(TW::Q);
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
@ -59,15 +59,15 @@ void run_fixed(xilinx_srl_pm &pm)
auto first_cell = ud.longest_chain.back();
auto last_cell = ud.longest_chain.front();
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
c->setParam(ID::INIT, initval.as_const());
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setParam(ID(CLKPOL), 1);
else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_), ID(FDRE_1)))
c->setParam(ID(CLKPOL), 0);
else if (first_cell->type.in(ID(FDRE))) {
if (!first_cell->getParam(ID(IS_C_INVERTED)).as_bool())
@ -77,9 +77,9 @@ void run_fixed(xilinx_srl_pm &pm)
}
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
c->setParam(ID(ENPOL), 1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
c->setParam(ID(ENPOL), 0);
else
c->setParam(ID(ENPOL), 2);
@ -88,9 +88,9 @@ void run_fixed(xilinx_srl_pm &pm)
c->setPort(TW::D, first_cell->getPort(TW::D));
c->setPort(TW::Q, last_cell->getPort(TW::Q));
c->setPort(TW::L, GetSize(ud.longest_chain)-1);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
c->setPort(TW::E, first_cell->getPort(TW::CE));
@ -100,7 +100,7 @@ void run_fixed(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, c->type.unescape());
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
}
void run_variable(xilinx_srl_pm &pm)
@ -108,14 +108,14 @@ void run_variable(xilinx_srl_pm &pm)
auto &st = pm.st_variable;
auto &ud = pm.ud_variable;
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), st.first->type.unescape());
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), design->twines.unescaped_str(st.first->type));
SigSpec initval;
for (const auto &i : ud.chain) {
auto cell = i.first;
auto slice = i.second;
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
SigBit Q = cell->getPort(TW::Q)[slice];
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
@ -134,46 +134,46 @@ void run_variable(xilinx_srl_pm &pm)
auto first_cell = ud.chain.back().first;
auto first_slice = ud.chain.back().second;
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
c->setParam(ID::DEPTH, GetSize(ud.chain));
c->setParam(ID::INIT, initval.as_const());
Const clkpol, enpol;
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
clkpol = 1;
else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_)))
clkpol = 0;
else if (first_cell->type.in(ID($dff), ID($dffe)))
else if (first_cell->type.in(TW($dff), TW($dffe)))
clkpol = first_cell->getParam(ID::CLK_POLARITY);
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
enpol = 1;
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
enpol = 0;
else if (first_cell->type.in(ID($dffe)))
else if (first_cell->type.in(TW($dffe)))
enpol = first_cell->getParam(ID::EN_POLARITY);
else
enpol = 2;
c->setParam(ID(CLKPOL), clkpol);
c->setParam(ID(ENPOL), enpol);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::C, first_cell->getPort(TW::C));
else if (first_cell->type.in(ID($dff), ID($dffe)))
else if (first_cell->type.in(TW($dff), TW($dffe)))
c->setPort(TW::C, first_cell->getPort(TW::CLK));
else
log_abort();
c->setPort(TW::D, first_cell->getPort(TW::D)[first_slice]);
c->setPort(TW::Q, st.shiftx->getPort(TW::Y));
c->setPort(TW::L, st.shiftx->getPort(TW::B));
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($dff)))
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID($dffe)))
else if (first_cell->type.in(TW($dffe)))
c->setPort(TW::E, first_cell->getPort(TW::EN));
else
log_abort();
@ -181,7 +181,7 @@ void run_variable(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, c->type.unescape());
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
}
struct XilinxSrlPass : public Pass {