diff --git a/Makefile b/Makefile
index 0a73fac89..df1670b08 100644
--- a/Makefile
+++ b/Makefile
@@ -672,7 +672,8 @@ OBJS += kernel/log_compat.o
 endif
 OBJS += kernel/binding.o kernel/tclapi.o
 OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o kernel/twine.o
-OBJS += kernel/drivertools.o kernel/functional.o kernel/threading.o
+OBJS += kernel/drivertools.o kernel/threading.o
+# OBJS += kernel/functional.o
 ifeq ($(ENABLE_ZLIB),1)
 OBJS += kernel/fstdata.o
 endif
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 1c647c447..15078baa5 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -221,7 +221,7 @@ struct AigerWriter
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type == ID($_NOT_))
+			if (cell->type == TW($_NOT_))
 			{
 				SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
@@ -231,7 +231,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
+			if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_)))
 			{
 				SigBit D = sigmap(cell->getPort(TW::D).as_bit());
 				SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
@@ -239,14 +239,14 @@ struct AigerWriter
 				undriven_bits.erase(Q);
 				ff_map[Q] = D;
 
-				if (cell->type != ID($_FF_)) {
+				if (cell->type != TW($_FF_)) {
 					auto sig_clk = sigmap(cell->getPort(TW::C).as_bit());
-					ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
+					ywmap_clocks[sig_clk] |= cell->type == TW($_DFF_N_) ? 2 : 1;
 				}
 				continue;
 			}
 
-			if (cell->type == ID($anyinit))
+			if (cell->type == TW($anyinit))
 			{
 				auto sig_d = sigmap(cell->getPort(TW::D));
 				auto sig_q = sigmap(cell->getPort(TW::Q));
@@ -257,7 +257,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($_AND_))
+			if (cell->type == TW($_AND_))
 			{
 				SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit B = sigmap(cell->getPort(TW::B).as_bit());
@@ -269,7 +269,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($initstate))
+			if (cell->type == TW($initstate))
 			{
 				SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
 				undriven_bits.erase(Y);
@@ -277,7 +277,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($assert))
+			if (cell->type == TW($assert))
 			{
 				SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@@ -288,7 +288,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($assume))
+			if (cell->type == TW($assume))
 			{
 				SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@@ -299,7 +299,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($live))
+			if (cell->type == TW($live))
 			{
 				SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@@ -309,7 +309,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($fair))
+			if (cell->type == TW($fair))
 			{
 				SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
@@ -319,7 +319,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($anyconst))
+			if (cell->type == TW($anyconst))
 			{
 				for (auto bit : sigmap(cell->getPort(TW::Y))) {
 					undriven_bits.erase(bit);
@@ -328,7 +328,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($anyseq))
+			if (cell->type == TW($anyseq))
 			{
 				for (auto bit : sigmap(cell->getPort(TW::Y))) {
 					undriven_bits.erase(bit);
@@ -337,7 +337,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
+			if (cell->type.in(TW($scopeinfo), TW($input_port), TW($output_port), TW($public)))
 				continue;
 
 			log_error("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
@@ -773,10 +773,10 @@ struct AigerWriter
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_), ID($anyinit), ID($anyconst), ID($anyseq)))
+			if (cell->type.in(TW($_FF_), TW($_DFF_N_), TW($_DFF_P_), TW($anyinit), TW($anyconst), TW($anyseq)))
 			{
 				// Use sig_q to get the FF output name, but sig to lookup aiger bits
-				auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? TW::Y : TW::Q);
+				auto sig_qy = cell->getPort(cell->type.in(TW($anyconst), TW($anyseq)) ? TW::Y : TW::Q);
 				SigSpec sig = sigmap(sig_qy);
 
 				if (cell->get_bool_attribute(ID(clk2fflogic)))
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 61364d2de..70334f3b2 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -187,11 +187,11 @@ struct XAigerWriter
 		TimingInfo timing;
 
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+			if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 				continue;
 
 			if (!cell->has_keep_attr()) {
-				if (cell->type == ID($_NOT_))
+				if (cell->type == TW($_NOT_))
 				{
 					SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 					SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
@@ -201,7 +201,7 @@ struct XAigerWriter
 					continue;
 				}
 
-				if (cell->type == ID($_AND_))
+				if (cell->type == TW($_AND_))
 				{
 					SigBit A = sigmap(cell->getPort(TW::A).as_bit());
 					SigBit B = sigmap(cell->getPort(TW::B).as_bit());
@@ -213,7 +213,7 @@ struct XAigerWriter
 					continue;
 				}
 
-				if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
+				if (dff_mode && cell->type.in(TW($_DFF_N_), TW($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
 				{
 					SigBit D = sigmap(cell->getPort(TW::D).as_bit());
 					SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
@@ -224,7 +224,7 @@ struct XAigerWriter
 					continue;
 				}
 
-				if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
+				if (cell->type.in(TW($specify2), TW($specify3), TW($specrule)))
 					continue;
 			}
 
@@ -248,12 +248,12 @@ struct XAigerWriter
 						continue;
 				}
 
-				auto inst_name_id = RTLIL::IdString(design->twines.str(inst_module->meta_->name));
+				auto inst_name_id = inst_module->meta_->name;
 				if (!timing.count(inst_name_id))
 					timing.setup_module(inst_module);
 
 				for (auto &i : timing.at(inst_name_id).arrival) {
-					auto port_name_ref = design->twines.add(Twine{i.first.name.str()});
+					auto port_name_ref = i.first.name;
 					if (!cell->hasPort(port_name_ref))
 						continue;
 
@@ -273,7 +273,7 @@ struct XAigerWriter
 					if (ys_debug(1)) {
 						static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
 						if (seen.emplace(inst_name_id, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
-								cell->type.unescape(), i.first.name.unescape(), offset, d);
+								cell->type.unescape(), design->twines.unescaped_str(i.first.name), offset, d);
 					}
 #endif
 					arrival_times[rhs[offset]] = d;
@@ -308,7 +308,7 @@ struct XAigerWriter
 					}
 			}
 
-			//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);
+			//log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescaped(), cell);
 		}
 
 		dict<IdString, std::vector<TwineRef>> box_ports;
diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc
index 81abc7b1f..df4e5ab9e 100644
--- a/backends/aiger2/aiger.cc
+++ b/backends/aiger2/aiger.cc
@@ -32,21 +32,21 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), \
-					ID($bwmux)
+#define BITWISE_OPS TW($buf), TW($not), TW($mux), TW($and), TW($or), TW($xor), TW($xnor), TW($fa), \
+					TW($bwmux)
 
-#define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)
+#define REDUCE_OPS TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool)
 
-#define LOGIC_OPS ID($logic_and), ID($logic_or), ID($logic_not)
+#define LOGIC_OPS TW($logic_and), TW($logic_or), TW($logic_not)
 
-#define GATE_OPS ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), \
-				 ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), \
-				 ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)
+#define GATE_OPS TW($_BUF_), TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), \
+				 TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_), TW($_MUX_), TW($_NMUX_), \
+				 TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)
 
-#define CMP_OPS ID($eq), ID($ne), ID($lt), ID($le), ID($ge), ID($gt)
+#define CMP_OPS TW($eq), TW($ne), TW($lt), TW($le), TW($ge), TW($gt)
 
 // TODO
-//#define ARITH_OPS ID($add), ID($sub), ID($neg)
+//#define ARITH_OPS TW($add), TW($sub), TW($neg)
 
 static constexpr auto known_ops = []() constexpr {
 	StaticCellTypes::Categories::Category c{};
@@ -60,7 +60,7 @@ static constexpr auto known_ops = []() constexpr {
 		c.set_id(id);
 	for (auto id : {CMP_OPS})
 		c.set_id(id);
-	for (auto id : {ID($pos), ID($pmux), ID($bmux)})
+	for (auto id : {TW($pos), TW($pmux), TW($bmux)})
 		c.set_id(id);
 	return c;
 }();
@@ -109,7 +109,7 @@ struct Index {
 		int pos = index_wires(info, m);
 
 		for (auto cell : m->cells()) {
-			if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port), ID($output_port), ID($public)))
+			if (known_ops(cell->type) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public)))
 				continue;
 
 			Module *submodule = m->design->module(cell->type);
@@ -128,7 +128,7 @@ struct Index {
 					// can't bail at this point. If they are hit by a traversal
 					// (which can only really happen with $tribuf not
 					// $connect), we can still detect this as an error later.
-					if (cell->type == ID($connect) || (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf))))
+					if (cell->type == TW($connect) || (cell->type == TW($tribuf) && cell->has_attribute(ID(aiger2_zbuf))))
 						continue;
 					if (!submodule || submodule->get_blackbox_attribute())
 						log_error("Unsupported cell type: %s (%s in %s)\n",
@@ -292,18 +292,18 @@ struct Index {
 			aport.extend_u0(width, asigned);
 			bport.extend_u0(width, bsigned);
 
-			if (cell->type.in(ID($eq), ID($ne))) {
+			if (cell->type.in(TW($eq), TW($ne))) {
 				int carry = CTRUE;
 				for (int i = 0; i < width; i++) {
 					Lit a = visit(cursor, aport[i]);
 					Lit b = visit(cursor, bport[i]);
 					carry = AND(carry, XNOR(a, b));
 				}
-				return (cell->type == ID($eq)) ? carry : /* $ne */ NOT(carry);
-			} else if (cell->type.in(ID($lt), ID($le), ID($gt), ID($ge))) {
-				if (cell->type.in(ID($gt), ID($ge)))
+				return (cell->type == TW($eq)) ? carry : /* $ne */ NOT(carry);
+			} else if (cell->type.in(TW($lt), TW($le), TW($gt), TW($ge))) {
+				if (cell->type.in(TW($gt), TW($ge)))
 					std::swap(aport, bport);
-				int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE;
+				int carry = cell->type.in(TW($le), TW($ge)) ? CFALSE : CTRUE;
 				Lit a = Writer::EMPTY_LIT;
 				Lit b = Writer::EMPTY_LIT;
 				// TODO: this might not be the most economic structure; revisit at a later date
@@ -317,28 +317,28 @@ struct Index {
 			} else {
 				log_abort();
 			}
-		} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
+		} else if (cell->type.in(REDUCE_OPS, TW($logic_not))) {
 			SigSpec inport = cell->getPort(TW::A);
 
 			std::vector<Lit> lits;
 			for (int i = 0; i < inport.size(); i++) {
 				Lit lit = visit(cursor, inport[i]);
-				if (cell->type.in(ID($reduce_and), ID($reduce_xor), ID($reduce_xnor))) {
+				if (cell->type.in(TW($reduce_and), TW($reduce_xor), TW($reduce_xnor))) {
 					lits.push_back(lit);
-				} else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+				} else if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
 					lits.push_back(NOT(lit));
 				} else {
 					log_abort();
 				}
 			}
 
-			Lit acc = REDUCE(lits, cell->type.in(ID($reduce_xor), ID($reduce_xnor)));
+			Lit acc = REDUCE(lits, cell->type.in(TW($reduce_xor), TW($reduce_xnor)));
 
-			if (!cell->type.in(ID($reduce_xnor), ID($reduce_or), ID($reduce_bool)))
+			if (!cell->type.in(TW($reduce_xnor), TW($reduce_or), TW($reduce_bool)))
 				return acc;
 			else
 				return NOT(acc);
-		} else if (cell->type.in(ID($logic_and), ID($logic_or))) {
+		} else if (cell->type.in(TW($logic_and), TW($logic_or))) {
 			SigSpec aport = cell->getPort(TW::A);
 			SigSpec bport = cell->getPort(TW::B);
 
@@ -356,13 +356,13 @@ struct Index {
 				b = OR(b, l);
 			}
 
-			if (cell->type == ID($logic_and))
+			if (cell->type == TW($logic_and))
 				return AND(a, b);
-			else if (cell->type == ID($logic_or))
+			else if (cell->type == TW($logic_or))
 				return OR(a, b);
 			else
 				log_abort();
-		} else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) {
+		} else if (cell->type.in(BITWISE_OPS, GATE_OPS, TW($pos))) {
 			SigSpec aport = cell->getPort(TW::A);
 			Lit a;
 			if (obit < aport.size()) {
@@ -374,9 +374,9 @@ struct Index {
 					a = CFALSE;
 			}
 
-			if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) {
+			if (cell->type.in(TW($buf), TW($pos), TW($_BUF_))) {
 				return a;
-			} else if (cell->type.in(ID($not), ID($_NOT_))) {
+			} else if (cell->type.in(TW($not), TW($_NOT_))) {
 				return NOT(a);
 			} else {
 				SigSpec bport = cell->getPort(TW::B);
@@ -390,32 +390,32 @@ struct Index {
 						b = CFALSE;
 				}
 
-				if (cell->type.in(ID($and), ID($_AND_))) {
+				if (cell->type.in(TW($and), TW($_AND_))) {
 					return AND(a, b);
-				} else if (cell->type.in(ID($_NAND_))) {
+				} else if (cell->type.in(TW($_NAND_))) {
 					return NOT(AND(a, b));
-				} else if (cell->type.in(ID($or), ID($_OR_))) {
+				} else if (cell->type.in(TW($or), TW($_OR_))) {
 					return OR(a, b);
-				} else if (cell->type.in(ID($_NOR_))) {
+				} else if (cell->type.in(TW($_NOR_))) {
 					return NOT(OR(a, b));
-				} else if (cell->type.in(ID($xor), ID($_XOR_))) {
+				} else if (cell->type.in(TW($xor), TW($_XOR_))) {
 					return XOR(a, b);
-				} else if (cell->type.in(ID($xnor), ID($_XNOR_))) {
+				} else if (cell->type.in(TW($xnor), TW($_XNOR_))) {
 					return XNOR(a, b);
-				} else if (cell->type.in(ID($_ANDNOT_))) {
+				} else if (cell->type.in(TW($_ANDNOT_))) {
 					return AND(a, NOT(b));
-				} else if (cell->type.in(ID($_ORNOT_))) {
+				} else if (cell->type.in(TW($_ORNOT_))) {
 					return OR(a, NOT(b));
-				} else if (cell->type.in(ID($mux), ID($_MUX_))) {
+				} else if (cell->type.in(TW($mux), TW($_MUX_))) {
 					Lit s = visit(cursor, cell->getPort(TW::S));
 					return MUX(a, b, s);
-				} else if (cell->type.in(ID($bwmux))) {
+				} else if (cell->type.in(TW($bwmux))) {
 					Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
 					return MUX(a, b, s);
-				} else if (cell->type.in(ID($_NMUX_))) {
+				} else if (cell->type.in(TW($_NMUX_))) {
 					Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
 					return NOT(MUX(a, b, s));
-				} else if (cell->type.in(ID($fa))) {
+				} else if (cell->type.in(TW($fa))) {
 					Lit c = visit(cursor, cell->getPort(TW::C)[obit]);
 					Lit ab = XOR(a, b);
 					if (oport == TW::Y) {
@@ -425,16 +425,16 @@ struct Index {
 						Lit c_and_ab = AND(c, ab);
 						return OR(a_and_b, c_and_ab);
 					}
-				} else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
+				} else if (cell->type.in(TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_))) {
 					Lit c, d;
 
 					c = visit(cursor, cell->getPort(TW::C)[obit]);
-					if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_)))
+					if (/* 4 input types */ cell->type.in(TW($_AOI4_), TW($_OAI4_)))
 						d = visit(cursor, cell->getPort(TW::D)[obit]);
 					else
-						d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE;
+						d = cell->type == TW($_AOI3_) ? CTRUE : CFALSE;
 
-					if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_))) {
+					if (/* aoi */ cell->type.in(TW($_AOI3_), TW($_AOI4_))) {
 						Lit a_and_b = AND(a, b);
 						Lit c_and_d = AND(c, d);
 						return NOT(OR(a_and_b, c_and_d));
@@ -447,7 +447,7 @@ struct Index {
 					log_abort();
 				}
 			}
-		} else if (cell->type == ID($pmux)) {
+		} else if (cell->type == TW($pmux)) {
 			SigSpec aport = cell->getPort(TW::A);
 			SigSpec bport = cell->getPort(TW::B);
 			SigSpec sport = cell->getPort(TW::S);
@@ -468,7 +468,7 @@ struct Index {
 			Lit reduce_bar = NOT(REDUCE(bar));
 
 			return OR(reduce_sels_and_a, reduce_bar);
-		} else if (cell->type == ID($bmux)) {
+		} else if (cell->type == TW($bmux)) {
 			SigSpec aport = cell->getPort(TW::A);
 			SigSpec sport = cell->getPort(TW::S);
 			int width = cell->getParam(ID::WIDTH).as_int();
@@ -537,7 +537,7 @@ struct Index {
 			Design *design = index.design;
 			auto &minfo = leaf_minfo(index);
 			if (!minfo.suboffsets.count(cell))
-				log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescape(), cell, cell->module);
+				log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescaped(), cell, cell->module);
 			Module *def = design->module(cell->type);
 			log_assert(def);
 			levels.push_back(Level(index.modules.at(def), cell));
@@ -660,7 +660,7 @@ struct Index {
 				auto &port = instance->getPort(portname);
 				if (bit.offset >= port.size())
 					log_error("Bit %d of input port %s on instance %s of %s unconnected\n",
-							  bit.offset, design->twines.str(portname).c_str(), instance, instance->type.unescape());
+							  bit.offset, design->twines.str(portname).c_str(), instance, design->twines.unescaped_str(instance->type));
 				ret = visit(cursor, port[bit.offset]);
 			}
 			cursor.enter(*this, instance);
@@ -845,7 +845,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
 				char buf[32];
 				snprintf(buf, sizeof(buf), "o%d ", i);
 				f->write(buf, strlen(buf));
-				std::string name = bit.wire->name.unescape();
+				std::string name = design->twines.unescaped_str(bit.wire->name);
 				f->write(name.data(), name.size());
 				f->put('\n');
 			}
@@ -858,7 +858,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
 				char buf[32];
 				snprintf(buf, sizeof(buf), "i%d ", i);
 				f->write(buf, strlen(buf));
-				std::string name = bit.wire->name.unescape();
+				std::string name = design->twines.unescaped_str(bit.wire->name);
 				f->write(name.data(), name.size());
 				f->put('\n');
 			}
@@ -1090,7 +1090,7 @@ struct XAigerWriter : AigerWriter {
 			for (auto box : minfo.found_blackboxes) {
 				log_debug(" - %s.%s (type %s): ", cursor.path(),
 						  box,
-						  box->type.unescape());
+						  design->twines.unescaped_str(box->type));
 
 				Module *box_module = design->module(box->type), *box_derived;
 
@@ -1159,7 +1159,7 @@ struct XAigerWriter : AigerWriter {
 						} else {
 							// FIXME: hierarchical path
 							log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
-										design->twines.str(port_id).c_str(), i, box, box->type.unescape());
+										design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
 							bit = RTLIL::Sx;
 						}
 
@@ -1194,7 +1194,7 @@ struct XAigerWriter : AigerWriter {
 						} else {
 							// FIXME: hierarchical path
 							log_warning("connection on port %s[%d] of instance %s (type %s) missing\n",
-										design->twines.str(port_id).c_str(), i, box, box->type.unescape());
+										design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
 							pad_pi();
 							continue;
 						}
@@ -1211,7 +1211,7 @@ struct XAigerWriter : AigerWriter {
 					holes_wb->setPort(port_id, w);
 				} else {
 					log_error("Ambiguous port direction on %s/%s\n",
-							  box->type.unescape(), design->twines.str(port_id).c_str());
+							  design->twines.unescaped_str(box->type), design->twines.str(port_id).c_str());
 				}
 			}
 		}
@@ -1406,7 +1406,7 @@ struct Aiger2Backend : Backend {
 				continue;
 			if (known_ops(cell.type))
 				continue;
-			std::string name = cell.type.unescape();
+			std::string name = design->twines.unescaped_str(cell.type);
 			if (col + name.size() + 2 > 72) {
 				log("\n    ");
 				col = 0;
@@ -1428,7 +1428,7 @@ struct Aiger2Backend : Backend {
 				continue;
 			if (known_ops(cell.type))
 				continue;
-			std::string name = cell.type.unescape();
+			std::string name = design->twines.unescaped_str(cell.type);
 			if (col + name.size() + 2 > 72) {
 				log("\n    ");
 				col = 0;
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 195a2676a..db058dbf1 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -91,7 +91,7 @@ struct BlifDumper
 
 	const std::string str(RTLIL::IdString id)
 	{
-		std::string str = id.unescape();
+		std::string str = design->twines.unescaped_str(id);
 		for (size_t i = 0; i < str.size(); i++)
 			if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
 				str[i] = '?';
@@ -108,7 +108,7 @@ struct BlifDumper
 			return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef";
 		}
 
-		std::string str = sig.wire->name.unescape();
+		std::string str = design->twines.unescaped_str(sig.wire->name);
 		for (size_t i = 0; i < str.size(); i++)
 			if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
 				str[i] = '?';
@@ -150,7 +150,7 @@ struct BlifDumper
 	void dump_params(const char *command, dict<IdString, Const> &params)
 	{
 		for (auto &param : params) {
-			f << stringf("%s %s ", command, param.first.unescape());
+			f << stringf("%s %s ", command, design->twines.unescaped_str(param.first));
 			if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
 				std::string str = param.second.decode_string();
 				f << stringf("\"");
@@ -232,7 +232,7 @@ struct BlifDumper
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type == ID($scopeinfo))
+			if (cell->type == TW($scopeinfo))
 				continue;
 
 			if (config->unbuf_types.count(cell->type)) {
@@ -244,131 +244,131 @@ struct BlifDumper
 				continue;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_NOT_)) {
+			if (!config->icells_mode && cell->type == TW($_NOT_)) {
 				f << stringf(".names %s %s\n0 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_AND_)) {
+			if (!config->icells_mode && cell->type == TW($_AND_)) {
 				f << stringf(".names %s %s %s\n11 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_OR_)) {
+			if (!config->icells_mode && cell->type == TW($_OR_)) {
 				f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_XOR_)) {
+			if (!config->icells_mode && cell->type == TW($_XOR_)) {
 				f << stringf(".names %s %s %s\n10 1\n01 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_NAND_)) {
+			if (!config->icells_mode && cell->type == TW($_NAND_)) {
 				f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_NOR_)) {
+			if (!config->icells_mode && cell->type == TW($_NOR_)) {
 				f << stringf(".names %s %s %s\n00 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_XNOR_)) {
+			if (!config->icells_mode && cell->type == TW($_XNOR_)) {
 				f << stringf(".names %s %s %s\n11 1\n00 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
+			if (!config->icells_mode && cell->type == TW($_ANDNOT_)) {
 				f << stringf(".names %s %s %s\n10 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
+			if (!config->icells_mode && cell->type == TW($_ORNOT_)) {
 				f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_AOI3_)) {
+			if (!config->icells_mode && cell->type == TW($_AOI3_)) {
 				f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_OAI3_)) {
+			if (!config->icells_mode && cell->type == TW($_OAI3_)) {
 				f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_AOI4_)) {
+			if (!config->icells_mode && cell->type == TW($_AOI4_)) {
 				f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
 						str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_OAI4_)) {
+			if (!config->icells_mode && cell->type == TW($_OAI4_)) {
 				f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
 						str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_MUX_)) {
+			if (!config->icells_mode && cell->type == TW($_MUX_)) {
 				f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
 						str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_NMUX_)) {
+			if (!config->icells_mode && cell->type == TW($_NMUX_)) {
 				f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
 						str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
 						str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_FF_)) {
+			if (!config->icells_mode && cell->type == TW($_FF_)) {
 				f << stringf(".latch %s %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
 						str_init(cell->getPort(TW::Q)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
+			if (!config->icells_mode && cell->type == TW($_DFF_N_)) {
 				f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
 						str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
+			if (!config->icells_mode && cell->type == TW($_DFF_P_)) {
 				f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
 						str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
+			if (!config->icells_mode && cell->type == TW($_DLATCH_N_)) {
 				f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
 						str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
+			if (!config->icells_mode && cell->type == TW($_DLATCH_P_)) {
 				f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
 						str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($lut)) {
+			if (!config->icells_mode && cell->type == TW($lut)) {
 				f << stringf(".names");
 				auto &inputs = cell->getPort(TW::A);
 				auto width = cell->parameters.at(ID::WIDTH).as_int();
@@ -390,7 +390,7 @@ struct BlifDumper
 				goto internal_cell;
 			}
 
-			if (!config->icells_mode && cell->type == ID($sop)) {
+			if (!config->icells_mode && cell->type == TW($sop)) {
 				f << stringf(".names");
 				auto &inputs = cell->getPort(TW::A);
 				auto width = cell->parameters.at(ID::WIDTH).as_int();
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index eea913066..e9d219596 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -119,7 +119,7 @@ struct BtorWorker
 	template<typename T>
 	string getinfo(T *obj, bool srcsym = false)
 	{
-		string infostr = obj->name.unescape();
+		string infostr = design->twines.unescaped_str(obj->name);
 		if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
 		if (obj->has_attribute(ID::src)) {
 			string src = module && module->design ? module->design->get_src_attribute(obj) : std::string();
@@ -147,7 +147,7 @@ struct BtorWorker
 
 	string getinfo(Mem *mem, bool srcsym = false)
 	{
-		string infostr = mem->memid.unescape();
+		string infostr = design->twines.unescaped_str(mem->memid);
 		if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
 		if (mem->has_attribute(ID::src)) {
 			string src = module && module->design ? module->design->get_src_attribute(mem) : std::string();
@@ -280,24 +280,24 @@ struct BtorWorker
 		cell_recursion_guard.insert(cell);
 		btorf_push(cell->module->design->twines.str(cell->meta_->name));
 
-		if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
-				ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
+		if (cell->type.in(TW($add), TW($sub), TW($mul), TW($and), TW($or), TW($xor), TW($xnor), TW($shl), TW($sshl), TW($shr), TW($sshr), TW($shift), TW($shiftx),
+				TW($concat), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_)))
 		{
 			string btor_op;
-			if (cell->type == ID($add)) btor_op = "add";
-			if (cell->type == ID($sub)) btor_op = "sub";
-			if (cell->type == ID($mul)) btor_op = "mul";
-			if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
-			if (cell->type == ID($shr)) btor_op = "srl";
-			if (cell->type == ID($sshr)) btor_op = "sra";
-			if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
-			if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
-			if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
-			if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
-			if (cell->type == ID($concat)) btor_op = "concat";
-			if (cell->type == ID($_NAND_)) btor_op = "nand";
-			if (cell->type == ID($_NOR_)) btor_op = "nor";
-			if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
+			if (cell->type == TW($add)) btor_op = "add";
+			if (cell->type == TW($sub)) btor_op = "sub";
+			if (cell->type == TW($mul)) btor_op = "mul";
+			if (cell->type.in(TW($shl), TW($sshl))) btor_op = "sll";
+			if (cell->type == TW($shr)) btor_op = "srl";
+			if (cell->type == TW($sshr)) btor_op = "sra";
+			if (cell->type.in(TW($shift), TW($shiftx))) btor_op = "shift";
+			if (cell->type.in(TW($and), TW($_AND_))) btor_op = "and";
+			if (cell->type.in(TW($or), TW($_OR_))) btor_op = "or";
+			if (cell->type.in(TW($xor), TW($_XOR_))) btor_op = "xor";
+			if (cell->type == TW($concat)) btor_op = "concat";
+			if (cell->type == TW($_NAND_)) btor_op = "nand";
+			if (cell->type == TW($_NOR_)) btor_op = "nor";
+			if (cell->type.in(TW($xnor), TW($_XNOR_))) btor_op = "xnor";
 			log_assert(!btor_op.empty());
 
 			int width_ay = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
@@ -309,17 +309,17 @@ struct BtorWorker
 			if (btor_op == "shift" && !b_signed)
 				btor_op = "srl";
 
-			if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
+			if (cell->type.in(TW($shl), TW($sshl), TW($shr), TW($sshr)))
 				b_signed = false;
 
-			if (cell->type == ID($sshr) && !a_signed)
+			if (cell->type == TW($sshr) && !a_signed)
 				btor_op = "srl";
 
 			int sid = get_bv_sid(width);
 			int nid;
 
 			int nid_a;
-			if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) {
+			if (cell->type.in(TW($shl), TW($shr), TW($shift), TW($shiftx)) && a_signed && width_ay < width) {
 				// sign-extend A up to the width of Y
 				int nid_a_padded = get_sig_nid(cell->getPort(TW::A), width_ay, a_signed);
 
@@ -371,17 +371,17 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
+		if (cell->type.in(TW($div), TW($mod), TW($modfloor)))
 		{
 			bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
 			bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
 
 			string btor_op;
-			if (cell->type == ID($div)) btor_op = "div";
+			if (cell->type == TW($div)) btor_op = "div";
 			// "rem" = truncating modulo
-			if (cell->type == ID($mod)) btor_op = "rem";
+			if (cell->type == TW($mod)) btor_op = "rem";
 			// "mod" = flooring modulo
-			if (cell->type == ID($modfloor)) {
+			if (cell->type == TW($modfloor)) {
 				// "umod" doesn't exist because it's the same as "urem"
 				btor_op = a_signed || b_signed ? "mod" : "rem";
 			}
@@ -411,7 +411,7 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+		if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 		{
 			int sid = get_bv_sid(1);
 			int nid_a = get_sig_nid(cell->getPort(TW::A));
@@ -420,12 +420,12 @@ struct BtorWorker
 			int nid1 = next_nid++;
 			int nid2 = next_nid++;
 
-			if (cell->type == ID($_ANDNOT_)) {
+			if (cell->type == TW($_ANDNOT_)) {
 				btorf("%d not %d %d\n", nid1, sid, nid_b);
 				btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
 			}
 
-			if (cell->type == ID($_ORNOT_)) {
+			if (cell->type == TW($_ORNOT_)) {
 				btorf("%d not %d %d\n", nid1, sid, nid_b);
 				btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
 			}
@@ -435,7 +435,7 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
+		if (cell->type.in(TW($_OAI3_), TW($_AOI3_)))
 		{
 			int sid = get_bv_sid(1);
 			int nid_a = get_sig_nid(cell->getPort(TW::A));
@@ -446,13 +446,13 @@ struct BtorWorker
 			int nid2 = next_nid++;
 			int nid3 = next_nid++;
 
-			if (cell->type == ID($_OAI3_)) {
+			if (cell->type == TW($_OAI3_)) {
 				btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
 				btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
 				btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
 			}
 
-			if (cell->type == ID($_AOI3_)) {
+			if (cell->type == TW($_AOI3_)) {
 				btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
 				btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
 				btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
@@ -463,7 +463,7 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
+		if (cell->type.in(TW($_OAI4_), TW($_AOI4_)))
 		{
 			int sid = get_bv_sid(1);
 			int nid_a = get_sig_nid(cell->getPort(TW::A));
@@ -476,14 +476,14 @@ struct BtorWorker
 			int nid3 = next_nid++;
 			int nid4 = next_nid++;
 
-			if (cell->type == ID($_OAI4_)) {
+			if (cell->type == TW($_OAI4_)) {
 				btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
 				btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
 				btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
 				btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell));
 			}
 
-			if (cell->type == ID($_AOI4_)) {
+			if (cell->type == TW($_AOI4_)) {
 				btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
 				btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
 				btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
@@ -495,15 +495,15 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
+		if (cell->type.in(TW($lt), TW($le), TW($eq), TW($eqx), TW($ne), TW($nex), TW($ge), TW($gt)))
 		{
 			string btor_op;
-			if (cell->type == ID($lt)) btor_op = "lt";
-			if (cell->type == ID($le)) btor_op = "lte";
-			if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
-			if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
-			if (cell->type == ID($ge)) btor_op = "gte";
-			if (cell->type == ID($gt)) btor_op = "gt";
+			if (cell->type == TW($lt)) btor_op = "lt";
+			if (cell->type == TW($le)) btor_op = "lte";
+			if (cell->type.in(TW($eq), TW($eqx))) btor_op = "eq";
+			if (cell->type.in(TW($ne), TW($nex))) btor_op = "neq";
+			if (cell->type == TW($ge)) btor_op = "gte";
+			if (cell->type == TW($gt)) btor_op = "gt";
 			log_assert(!btor_op.empty());
 
 			int width = 1;
@@ -518,7 +518,7 @@ struct BtorWorker
 			int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
 
 			int nid = next_nid++;
-			if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
+			if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt))) {
 				btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell));
 			} else {
 				btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
@@ -537,11 +537,11 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
+		if (cell->type.in(TW($not), TW($neg), TW($_NOT_), TW($pos), TW($buf), TW($_BUF_)))
 		{
 			string btor_op;
-			if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
-			if (cell->type == ID($neg)) btor_op = "neg";
+			if (cell->type.in(TW($not), TW($_NOT_))) btor_op = "not";
+			if (cell->type == TW($neg)) btor_op = "neg";
 
 			int width = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
 
@@ -551,7 +551,7 @@ struct BtorWorker
 
 			// the $pos/$buf cells just pass through, all other cells need an actual operation applied
 			int nid = nid_a;
-			if (!cell->type.in(ID($pos), ID($buf), ID($_BUF_)))
+			if (!cell->type.in(TW($pos), TW($buf), TW($_BUF_)))
 			{
 				log_assert(!btor_op.empty());
 				int sid = get_bv_sid(width);
@@ -570,12 +570,12 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
+		if (cell->type.in(TW($logic_and), TW($logic_or), TW($logic_not)))
 		{
 			string btor_op;
-			if (cell->type == ID($logic_and)) btor_op = "and";
-			if (cell->type == ID($logic_or))  btor_op = "or";
-			if (cell->type == ID($logic_not)) btor_op = "not";
+			if (cell->type == TW($logic_and)) btor_op = "and";
+			if (cell->type == TW($logic_or))  btor_op = "or";
+			if (cell->type == TW($logic_not)) btor_op = "not";
 			log_assert(!btor_op.empty());
 
 			int sid = get_bv_sid(1);
@@ -614,12 +614,12 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
+		if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($reduce_xor), TW($reduce_xnor)))
 		{
 			string btor_op;
-			if (cell->type == ID($reduce_and)) btor_op = "redand";
-			if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
-			if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
+			if (cell->type == TW($reduce_and)) btor_op = "redand";
+			if (cell->type.in(TW($reduce_or), TW($reduce_bool))) btor_op = "redor";
+			if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) btor_op = "redxor";
 			log_assert(!btor_op.empty());
 
 			int sid = get_bv_sid(1);
@@ -627,7 +627,7 @@ struct BtorWorker
 
 			int nid = next_nid++;
 
-			if (cell->type == ID($reduce_xnor)) {
+			if (cell->type == TW($reduce_xnor)) {
 				int nid2 = next_nid++;
 				btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
 				btorf("%d not %d %d\n", nid2, sid, nid);
@@ -650,7 +650,7 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
+		if (cell->type.in(TW($mux), TW($_MUX_), TW($_NMUX_)))
 		{
 			SigSpec sig_a = sigmap(cell->getPort(TW::A));
 			SigSpec sig_b = sigmap(cell->getPort(TW::B));
@@ -664,7 +664,7 @@ struct BtorWorker
 			int sid = get_bv_sid(GetSize(sig_y));
 			int nid = next_nid++;
 
-			if (cell->type == ID($_NMUX_)) {
+			if (cell->type == TW($_NMUX_)) {
 				int tmp = nid;
 				nid = next_nid++;
 				btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
@@ -677,7 +677,7 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type == ID($pmux))
+		if (cell->type == TW($pmux))
 		{
 			SigSpec sig_a = sigmap(cell->getPort(TW::A));
 			SigSpec sig_b = sigmap(cell->getPort(TW::B));
@@ -703,21 +703,21 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($dff), ID($ff), ID($anyinit), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
+		if (cell->type.in(TW($dff), TW($ff), TW($anyinit), TW($_DFF_P_), TW($_DFF_N), TW($_FF_)))
 		{
 			SigSpec sig_d = sigmap(cell->getPort(TW::D));
 			SigSpec sig_q = sigmap(cell->getPort(TW::Q));
 
-			if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
+			if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(TW($dff), TW($_DFF_P_), TW($_DFF_N_)))
 			{
-				SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? TW::CLK : TW::C));
+				SigSpec sig_c = sigmap(cell->getPort(cell->type == TW($dff) ? TW::CLK : TW::C));
 				int nid = get_sig_nid(sig_c);
 				bool negedge = false;
 
-				if (cell->type == ID($_DFF_N_))
+				if (cell->type == TW($_DFF_N_))
 					negedge = true;
 
-				if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
+				if (cell->type == TW($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
 					negedge = true;
 
 				if (!info_filename.empty())
@@ -756,7 +756,7 @@ struct BtorWorker
 			if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
 				btorf("%d state %d\n", nid, sid);
 			else
-				btorf("%d state %d %s\n", nid, sid, symbol.unescape());
+				btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(symbol));
 
 			if (cell->get_bool_attribute(ID(clk2fflogic)))
 				ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
@@ -775,7 +775,7 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($anyconst), ID($anyseq)))
+		if (cell->type.in(TW($anyconst), TW($anyseq)))
 		{
 			SigSpec sig_y = sigmap(cell->getPort(TW::Y));
 
@@ -786,7 +786,7 @@ struct BtorWorker
 
 			ywmap_state(sig_y);
 
-			if (cell->type == ID($anyconst)) {
+			if (cell->type == TW($anyconst)) {
 				int nid2 = next_nid++;
 				btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
 			}
@@ -795,7 +795,7 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type == ID($initstate))
+		if (cell->type == TW($initstate))
 		{
 			SigSpec sig_y = sigmap(cell->getPort(TW::Y));
 
@@ -834,12 +834,12 @@ struct BtorWorker
 
 			if (asyncwr && syncwr)
 				log_error("Memory %s.%s has mixed async/sync write ports.\n",
-						module, mem->memid.unescape());
+						module, design->twines.unescaped_str(mem->memid));
 
 			for (auto &port : mem->rd_ports) {
 				if (port.clk_enable)
 					log_error("Memory %s.%s has sync read ports.  Please use memory_nordff to convert them first.\n",
-							module, mem->memid.unescape());
+							module, design->twines.unescaped_str(mem->memid));
 			}
 
 			int data_sid = get_bv_sid(mem->width);
@@ -901,7 +901,7 @@ struct BtorWorker
 			if (mem->memid[0] == '$')
 				btorf("%d state %d\n", nid, sid);
 			else
-				btorf("%d state %d %s\n", nid, sid, mem->memid.unescape());
+				btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(mem->memid));
 
 			ywmap_state(cell);
 
@@ -976,15 +976,15 @@ struct BtorWorker
 			goto okay;
 		}
 
-		if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
+		if (cell->type.in(TW($dffe), TW($sdff), TW($sdffe), TW($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
 			log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_btor`.\n",
 					cell->type.unescape(), module, cell);
 		}
-		if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
+		if (cell->type.in(TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
 			log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_btor`.\n",
 					cell->type.unescape(), module, cell);
 		}
-		if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
+		if (cell->type.in(TW($sr), TW($dlatch), TW($adlatch), TW($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
 			log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_btor`.\n",
 					cell->type.unescape(), module, cell);
 		}
@@ -1296,7 +1296,7 @@ struct BtorWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type == ID($assume))
+			if (cell->type == TW($assume))
 			{
 				btorf_push(cell->module->design->twines.str(cell->meta_->name));
 
@@ -1316,7 +1316,7 @@ struct BtorWorker
 				btorf_pop(cell->module->design->twines.str(cell->meta_->name));
 			}
 
-			if (cell->type == ID($assert))
+			if (cell->type == TW($assert))
 			{
 				btorf_push(cell->module->design->twines.str(cell->meta_->name));
 
@@ -1345,7 +1345,7 @@ struct BtorWorker
 				btorf_pop(cell->module->design->twines.str(cell->meta_->name));
 			}
 
-			if (cell->type == ID($cover) && cover_mode)
+			if (cell->type == TW($cover) && cover_mode)
 			{
 				btorf_push(cell->module->design->twines.str(cell->meta_->name));
 
@@ -1417,7 +1417,7 @@ struct BtorWorker
 				int nid = it.first;
 				Mem *mem = it.second;
 
-				btorf_push(stringf("next %s", mem->memid.unescape()));
+				btorf_push(stringf("next %s", design->twines.unescaped_str(mem->memid)));
 
 				int abits = ceil_log2(mem->size);
 
@@ -1465,7 +1465,7 @@ struct BtorWorker
 				int nid2 = next_nid++;
 				btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(mem));
 
-				btorf_pop(stringf("next %s", mem->memid.unescape()));
+				btorf_pop(stringf("next %s", design->twines.unescaped_str(mem->memid)));
 			}
 		}
 
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index e910731cd..c320c6d17 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -177,39 +177,39 @@ struct Scheduler {
 bool is_unary_cell(TwineRef type)
 {
 	return type.in(
-		ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
-		ID($pos), ID($neg));
+		TW($not), TW($logic_not), TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool),
+		TW($pos), TW($neg));
 }
 
 bool is_binary_cell(TwineRef type)
 {
 	return type.in(
-		ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
-		ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
-		ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le),
-		ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($modfloor), ID($divfloor));
+		TW($and), TW($or), TW($xor), TW($xnor), TW($logic_and), TW($logic_or),
+		TW($shl), TW($sshl), TW($shr), TW($sshr), TW($shift), TW($shiftx),
+		TW($eq), TW($ne), TW($eqx), TW($nex), TW($gt), TW($ge), TW($lt), TW($le),
+		TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($modfloor), TW($divfloor));
 }
 
 bool is_extending_cell(TwineRef type)
 {
 	return !type.in(
-		ID($logic_not), ID($logic_and), ID($logic_or),
-		ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
+		TW($logic_not), TW($logic_and), TW($logic_or),
+		TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool));
 }
 
 bool is_inlinable_cell(TwineRef type)
 {
 	return is_unary_cell(type) || is_binary_cell(type) || type.in(
-		ID($mux), ID($concat), ID($slice), ID($pmux), ID($bmux), ID($demux), ID($bwmux));
+		TW($mux), TW($concat), TW($slice), TW($pmux), TW($bmux), TW($demux), TW($bwmux));
 }
 
 bool is_ff_cell(TwineRef type)
 {
 	return type.in(
-		ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
-		ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
-		ID($aldff), ID($aldffe),
-		ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
+		TW($dff), TW($dffe), TW($sdff), TW($sdffe), TW($sdffce),
+		TW($adff), TW($adffe), TW($dffsr), TW($dffsre),
+		TW($aldff), TW($aldffe),
+		TW($dlatch), TW($adlatch), TW($dlatchsr), TW($sr));
 }
 
 bool is_internal_cell(TwineRef type)
@@ -219,7 +219,7 @@ bool is_internal_cell(TwineRef type)
 
 bool is_effectful_cell(TwineRef type)
 {
-	return type.in(ID($print), ID($check));
+	return type.in(TW($print), TW($check));
 }
 
 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
@@ -1169,7 +1169,7 @@ struct CxxrtlWorker {
 			dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
 			f << ")";
 		// Muxes
-		} else if (cell->type == ID($mux)) {
+		} else if (cell->type == TW($mux)) {
 			f << "(";
 			dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
 			f << " ? ";
@@ -1178,7 +1178,7 @@ struct CxxrtlWorker {
 			dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
 			f << ")";
 		// Parallel (one-hot) muxes
-		} else if (cell->type == ID($pmux)) {
+		} else if (cell->type == TW($pmux)) {
 			int width = cell->getParam(ID::WIDTH).as_int();
 			int s_width = cell->getParam(ID::S_WIDTH).as_int();
 			for (int part = 0; part < s_width; part++) {
@@ -1193,7 +1193,7 @@ struct CxxrtlWorker {
 				f << ")";
 			}
 		// Big muxes
-		} else if (cell->type == ID($bmux)) {
+		} else if (cell->type == TW($bmux)) {
 			dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
 			f << ".bmux<";
 			f << cell->getParam(ID::WIDTH).as_int();
@@ -1201,7 +1201,7 @@ struct CxxrtlWorker {
 			dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
 			f << ").val()";
 		// Bitwise muxes
-		} else if (cell->type == ID($bwmux)) {
+		} else if (cell->type == TW($bwmux)) {
 			dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
 			f << ".bwmux(";
 			dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
@@ -1209,7 +1209,7 @@ struct CxxrtlWorker {
 			dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
 			f << ").val()";
 		// Demuxes
-		} else if (cell->type == ID($demux)) {
+		} else if (cell->type == TW($demux)) {
 			dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
 			f << ".demux<";
 			f << GetSize(cell->getPort(TW::Y));
@@ -1217,13 +1217,13 @@ struct CxxrtlWorker {
 			dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
 			f << ").val()";
 		// Concats
-		} else if (cell->type == ID($concat)) {
+		} else if (cell->type == TW($concat)) {
 			dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
 			f << ".concat(";
 			dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
 			f << ").val()";
 		// Slices
-		} else if (cell->type == ID($slice)) {
+		} else if (cell->type == TW($slice)) {
 			dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
 			f << ".slice<";
 			f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
@@ -1333,9 +1333,9 @@ struct CxxrtlWorker {
 				f << indent << "static const metadata_map attributes = ";
 				dump_metadata_map(cell->attributes);
 				f << ";\n";
-				if (cell->type == ID($print)) {
+				if (cell->type == TW($print)) {
 					f << indent << "performer->on_print(formatter, attributes);\n";
-				} else if (cell->type == ID($check)) {
+				} else if (cell->type == TW($check)) {
 					std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
 					f << indent << "performer->on_check(";
 					if (flavor == "assert")
@@ -1354,9 +1354,9 @@ struct CxxrtlWorker {
 			dec_indent();
 			f << indent << "} else {\n";
 			inc_indent();
-				if (cell->type == ID($print)) {
+				if (cell->type == TW($print)) {
 					f << indent << print_output << " << formatter();\n";
-				} else if (cell->type == ID($check)) {
+				} else if (cell->type == TW($check)) {
 					std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
 					if (flavor == "assert" || flavor == "assume") {
 						f << indent << "if (!condition) {\n";
@@ -1397,9 +1397,9 @@ struct CxxrtlWorker {
 				f << indent << "auto " << mangle(cell) << "_next = ";
 				dump_sigspec_rhs(cell->getPort(TW::EN));
 				f << ".concat(";
-				if (cell->type == ID($print))
+				if (cell->type == TW($print))
 					dump_sigspec_rhs(cell->getPort(TW::ARGS));
-				else if (cell->type == ID($check))
+				else if (cell->type == TW($check))
 					dump_sigspec_rhs(cell->getPort(TW::A));
 				else log_assert(false);
 				f << ").val();\n";
@@ -1444,7 +1444,7 @@ struct CxxrtlWorker {
 					f << " = ";
 					dump_sigspec_rhs(cell->getPort(TW::D));
 					f << ";\n";
-					if (cell->hasPort(TW::EN) && cell->type != ID($sdffce)) {
+					if (cell->hasPort(TW::EN) && cell->type != TW($sdffce)) {
 						dec_indent();
 						f << indent << "}\n";
 					}
@@ -1461,7 +1461,7 @@ struct CxxrtlWorker {
 						dec_indent();
 						f << indent << "}\n";
 					}
-					if (cell->hasPort(TW::EN) && cell->type == ID($sdffce)) {
+					if (cell->hasPort(TW::EN) && cell->type == TW($sdffce)) {
 						dec_indent();
 						f << indent << "}\n";
 					}
@@ -1534,7 +1534,7 @@ struct CxxrtlWorker {
 				f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
 			}
 		// Internal cells
-		} else if (cell->type.in(ID($input_port), ID($output_port), ID($public))) {
+		} else if (cell->type.in(TW($input_port), TW($output_port), TW($public))) {
 		} else if (is_internal_cell(cell->type)) {
 			log_cmd_error("Unsupported internal cell `%s'.\n", cell->type);
 		// User cells
@@ -2412,7 +2412,7 @@ struct CxxrtlWorker {
 				count_scopes++;
 				// If there were any submodules that were flattened, the module is also responsible for adding them.
 				for (auto cell : module->cells()) {
-					if (cell->type != ID($scopeinfo)) continue;
+					if (cell->type != TW($scopeinfo)) continue;
 					if (cell->getParam(ID::TYPE).decode_string() == "module") {
 						auto module_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Module);
 						auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell);
@@ -2697,9 +2697,9 @@ struct CxxrtlWorker {
 					if (is_effectful_cell(cell->type)) {
 						if (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
 							f << indent << "value<1> " << mangle(cell) << ";\n"; // async initial cell
-						if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($print))
+						if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($print))
 							f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n"; // {EN, ARGS}
-						if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($check))
+						if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($check))
 							f << indent << "value<2> " << mangle(cell) << ";\n"; // {EN, A}
 					}
 					if (is_internal_cell(cell->type))
@@ -3017,7 +3017,7 @@ struct CxxrtlWorker {
 				if (cell_module &&
 				    cell_module->get_blackbox_attribute() &&
 				    !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
-					log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", cell->type.unescape());
+					log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", cell->type.unescaped());
 
 				if (cell_module &&
 				    cell_module->get_bool_attribute(ID(cxxrtl_blackbox)) &&
@@ -3027,7 +3027,7 @@ struct CxxrtlWorker {
 				flow.add_node(cell);
 
 				// Various DFF cells are treated like posedge/negedge processes, see above for details.
-				if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
+				if (cell->type.in(TW($dff), TW($dffe), TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre), TW($sdff), TW($sdffe), TW($sdffce))) {
 					if (is_valid_clock(cell->getPort(TW::CLK)))
 						register_edge_signal(sigmap, cell->getPort(TW::CLK),
 							cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 12d6953b4..0c3bbb7b4 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -30,9 +30,9 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#define EDIF_DEF(_id) edif_names(_id.unescape(), true)
-#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(_id.unescape(), true, _ren, _bl, _br)
-#define EDIF_REF(_id) edif_names(_id.unescape(), false)
+#define EDIF_DEF(_id) design->twines.unescaped_str(edif_names(_id), true)
+#define EDIF_DEFR(_id, _ren, _bl, _br) design->twines.unescaped_str(edif_names(_id), true, _ren, _bl, _br)
+#define EDIF_REF(_id) design->twines.unescaped_str(edif_names(_id), false)
 #define EDIF_DEF_STR(_id) edif_names(RTLIL::unescape_id(_id), true)
 #define EDIF_REF_STR(_id) edif_names(RTLIL::unescape_id(_id), false)
 
@@ -216,7 +216,7 @@ struct EdifBackend : public Backend {
 
 			for (auto cell : module->cells())
 			{
-				if (cell->type == ID($scopeinfo))
+				if (cell->type == TW($scopeinfo))
 					continue;
 
 				if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
@@ -321,7 +321,7 @@ struct EdifBackend : public Backend {
 				for (auto &dep : it.second)
 					if (module_deps.count(dep) > 0)
 						goto not_ready_yet;
-				// log("Next in topological sort: %s\n", it.first->name.unescape());
+				// log("Next in topological sort: %s\n", design->twines.unescaped_str(it.first->name));
 				sorted_modules.push_back(it.first);
 			not_ready_yet:;
 			}
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 720af21f4..d02bac969 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -82,7 +82,7 @@ const char *make_id(IdString id)
 	if (namecache.count(id) != 0)
 		return namecache.at(id).c_str();
 
-	string new_id = id.unescape();
+	string new_id = design->twines.unescaped_str(id);
 
 	for (int i = 0; i < GetSize(new_id); i++)
 	{
@@ -599,7 +599,7 @@ struct FirrtlWorker
 			string y_id = make_id(cell->name);
 			std::string cellFileinfo = getFileinfo(cell);
 
-			if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
+			if (cell->type.in(TW($not), TW($logic_not), TW($_NOT_), TW($neg), TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_bool), TW($reduce_xnor)))
 			{
 				string a_expr = make_expr(cell->getPort(TW::A));
 				wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo));
@@ -609,29 +609,29 @@ struct FirrtlWorker
 				}
 
 				// Don't use the results of logical operations (a single bit) to control padding
-				if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) {
+				if (!(cell->type.in(TW($eq), TW($eqx), TW($gt), TW($ge), TW($lt), TW($le), TW($ne), TW($nex), TW($reduce_bool), TW($logic_not)) && y_width == 1) ) {
 					a_expr = stringf("pad(%s, %d)", a_expr, y_width);
 				}
 
 				// Assume the FIRRTL width is a single bit.
 				firrtl_width = 1;
-				if (cell->type.in(ID($not), ID($_NOT_))) primop = "not";
-				else if (cell->type == ID($neg)) {
+				if (cell->type.in(TW($not), TW($_NOT_))) primop = "not";
+				else if (cell->type == TW($neg)) {
 					primop = "neg";
 					firrtl_is_signed = true;	// Result of "neg" is signed (an SInt).
 					firrtl_width = a_width;
-				} else if (cell->type == ID($logic_not)) {
+				} else if (cell->type == TW($logic_not)) {
 					primop = "eq";
 					a_expr = stringf("%s, UInt(0)", a_expr);
 				}
-				else if (cell->type == ID($reduce_and)) primop = "andr";
-				else if (cell->type == ID($reduce_or)) primop = "orr";
-				else if (cell->type == ID($reduce_xor)) primop = "xorr";
-				else if (cell->type == ID($reduce_xnor)) {
+				else if (cell->type == TW($reduce_and)) primop = "andr";
+				else if (cell->type == TW($reduce_or)) primop = "orr";
+				else if (cell->type == TW($reduce_xor)) primop = "xorr";
+				else if (cell->type == TW($reduce_xnor)) {
 					primop = "not";
 					a_expr = stringf("xorr(%s)", a_expr);
 				}
-				else if (cell->type == ID($reduce_bool)) {
+				else if (cell->type == TW($reduce_bool)) {
 					primop = "neq";
 					// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
 					a_expr = stringf("%s, %cInt<%d>(0)", a_expr, a_signed ? 'S' : 'U', a_width);
@@ -647,9 +647,9 @@ struct FirrtlWorker
 
 				continue;
 			}
-			if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_), ID($eq), ID($eqx),
-                                        ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
-                                        ID($logic_and), ID($logic_or), ID($pow)))
+			if (cell->type.in(TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($xor), TW($_XOR_), TW($xnor), TW($and), TW($_AND_), TW($or), TW($_OR_), TW($eq), TW($eqx),
+                                        TW($gt), TW($ge), TW($lt), TW($le), TW($ne), TW($nex), TW($shr), TW($sshr), TW($sshl), TW($shl),
+                                        TW($logic_and), TW($logic_or), TW($pow)))
 			{
 				string a_expr = make_expr(cell->getPort(TW::A));
 				string b_expr = make_expr(cell->getPort(TW::B));
@@ -666,7 +666,7 @@ struct FirrtlWorker
 				}
 				// Shift amount is always unsigned, and needn't be padded to result width,
 				//  otherwise, we need to cast the b_expr appropriately
-				if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) {
+				if (b_signed && !cell->type.in(TW($shr), TW($sshr), TW($shl), TW($sshl), TW($pow))) {
 					b_expr = "asSInt(" + b_expr + ")";
 					// Expand the "B" operand to the result width
 					if (b_width < y_width) {
@@ -677,7 +677,7 @@ struct FirrtlWorker
 
 				// For the arithmetic ops, expand operand widths to result widths befor performing the operation.
 				// This corresponds (according to iverilog) to what verilog compilers implement.
-				if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_)))
+				if (cell->type.in(TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($xor), TW($_XOR_), TW($xnor), TW($and), TW($_AND_), TW($or), TW($_OR_)))
 				{
 					if (a_width < y_width) {
 						a_expr = stringf("pad(%s, %d)", a_expr, y_width);
@@ -692,79 +692,79 @@ struct FirrtlWorker
 				firrtl_width = a_width;
 				auto a_sig = cell->getPort(TW::A);
 
-				if (cell->type == ID($add)) {
+				if (cell->type == TW($add)) {
 					primop = "add";
 					firrtl_is_signed = a_signed | b_signed;
 					firrtl_width = max(a_width, b_width);
-				} else if (cell->type == ID($sub)) {
+				} else if (cell->type == TW($sub)) {
 					primop = "sub";
 					firrtl_is_signed = true;
 					int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
 					int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
 					firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
-				} else if (cell->type == ID($mul)) {
+				} else if (cell->type == TW($mul)) {
 					primop = "mul";
 					firrtl_is_signed = a_signed | b_signed;
 					firrtl_width = a_width + b_width;
-				} else if (cell->type == ID($div)) {
+				} else if (cell->type == TW($div)) {
 					primop = "div";
 					firrtl_is_signed = a_signed | b_signed;
 					firrtl_width = a_width;
-				} else if (cell->type == ID($mod)) {
+				} else if (cell->type == TW($mod)) {
 					// "rem" = truncating modulo
 					primop = "rem";
 					firrtl_width = min(a_width, b_width);
-				} else if (cell->type.in(ID($and), ID($_AND_))) {
+				} else if (cell->type.in(TW($and), TW($_AND_))) {
 					primop = "and";
 					always_uint = true;
 					firrtl_width = max(a_width, b_width);
 				}
-				else if (cell->type.in(ID($or), ID($_OR_))) {
+				else if (cell->type.in(TW($or), TW($_OR_))) {
 					primop =  "or";
 					always_uint = true;
 					firrtl_width = max(a_width, b_width);
 				}
-				else if (cell->type.in(ID($xor), ID($_XOR_))) {
+				else if (cell->type.in(TW($xor), TW($_XOR_))) {
 					primop = "xor";
 					always_uint = true;
 					firrtl_width = max(a_width, b_width);
 				}
-				else if (cell->type == ID($xnor)) {
+				else if (cell->type == TW($xnor)) {
 					primop = "xnor";
 					always_uint = true;
 					firrtl_width = max(a_width, b_width);
 				}
-				else if ((cell->type == ID($eq)) || (cell->type == ID($eqx))) {
+				else if ((cell->type == TW($eq)) || (cell->type == TW($eqx))) {
 					primop = "eq";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if ((cell->type == ID($ne)) || (cell->type == ID($nex))) {
+				else if ((cell->type == TW($ne)) || (cell->type == TW($nex))) {
 					primop = "neq";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if (cell->type == ID($gt)) {
+				else if (cell->type == TW($gt)) {
 					primop = "gt";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if (cell->type == ID($ge)) {
+				else if (cell->type == TW($ge)) {
 					primop = "geq";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if (cell->type == ID($lt)) {
+				else if (cell->type == TW($lt)) {
 					primop = "lt";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if (cell->type == ID($le)) {
+				else if (cell->type == TW($le)) {
 					primop = "leq";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if ((cell->type == ID($shl)) || (cell->type == ID($sshl))) {
+				else if ((cell->type == TW($shl)) || (cell->type == TW($sshl))) {
 					// FIRRTL will widen the result (y) by the amount of the shift.
 					// We'll need to offset this by extracting the un-widened portion as Verilog would do.
 					extract_y_bits = true;
@@ -782,7 +782,7 @@ struct FirrtlWorker
 						firrtl_width = a_width + (1 << b_width) - 1;
 					}
 				}
-				else if ((cell->type == ID($shr)) || (cell->type == ID($sshr))) {
+				else if ((cell->type == TW($shr)) || (cell->type == TW($sshr))) {
 					// We don't need to extract a specific range of bits.
 					extract_y_bits = false;
 					// Is the shift amount constant?
@@ -799,26 +799,26 @@ struct FirrtlWorker
 					// We'll need to do some special fixups if the source (and thus result) is signed.
 					if (firrtl_is_signed) {
 						// If this is a "logical" shift right, pretend the source is unsigned.
-						if (cell->type == ID($shr)) {
+						if (cell->type == TW($shr)) {
 							a_expr = "asUInt(" + a_expr + ")";
 						}
 					}
 				}
-				else if ((cell->type == ID($logic_and))) {
+				else if ((cell->type == TW($logic_and))) {
 					primop = "and";
 					a_expr = "neq(" + a_expr + ", UInt(0))";
 					b_expr = "neq(" + b_expr + ", UInt(0))";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if ((cell->type == ID($logic_or))) {
+				else if ((cell->type == TW($logic_or))) {
 					primop = "or";
 					a_expr = "neq(" + a_expr + ", UInt(0))";
 					b_expr = "neq(" + b_expr + ", UInt(0))";
 					always_uint = true;
 					firrtl_width = 1;
 				}
-				else if ((cell->type == ID($pow))) {
+				else if ((cell->type == TW($pow))) {
 					if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
 						// We'll convert this to a shift. To simplify things, change the a_expr to "1"
 						//	so we can use b_expr directly as a shift amount.
@@ -878,7 +878,7 @@ struct FirrtlWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($mux), ID($_MUX_)))
+			if (cell->type.in(TW($mux), TW($_MUX_)))
 			{
 				auto it = cell->parameters.find(ID::WIDTH);
 				int width = it == cell->parameters.end()? 1 : it->second.as_int();
@@ -901,7 +901,7 @@ struct FirrtlWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($dff)))
+			if (cell->type.in(TW($dff)))
 			{
 				bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool();
 				if (clkpol == false)
@@ -919,7 +919,7 @@ struct FirrtlWorker
 				continue;
 			}
 
-			if (cell->type == ID($shiftx)) {
+			if (cell->type == TW($shiftx)) {
 				// assign y = a[b +: y_width];
 				// We'll extract the correct bits as part of the primop.
 
@@ -940,7 +940,7 @@ struct FirrtlWorker
 				register_reverse_wire_map(y_id, cell->getPort(TW::Y));
 				continue;
 			}
-			if (cell->type == ID($shift)) {
+			if (cell->type == TW($shift)) {
 				// assign y = a >> b;
 				//  where b may be negative
 
@@ -966,7 +966,7 @@ struct FirrtlWorker
 				register_reverse_wire_map(y_id, cell->getPort(TW::Y));
 				continue;
 			}
-			if (cell->type == ID($pos)) {
+			if (cell->type == TW($pos)) {
 				// assign y = a;
 //				printCell(cell);
 				string a_expr = make_expr(cell->getPort(TW::A));
@@ -981,9 +981,9 @@ struct FirrtlWorker
 				continue;
 			}
 
-			if (cell->type == ID($scopeinfo))
+			if (cell->type == TW($scopeinfo))
 				continue;
-			log_error("Cell type not supported: %s (%s.%s)\n", cell->type.unescape(), module, cell);
+			log_error("Cell type not supported: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
 		}
 
 		for (auto &mem : memories) {
@@ -991,10 +991,10 @@ struct FirrtlWorker
 
 			Const init_data = mem.get_init_data();
 			if (!init_data.is_fully_undef())
-				log_error("Memory with initialization data: %s.%s\n", module, mem.memid.unescape());
+				log_error("Memory with initialization data: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
 
 			if (mem.start_offset != 0)
-				log_error("Memory with nonzero offset: %s.%s\n", module, mem.memid.unescape());
+				log_error("Memory with nonzero offset: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
 
 			for (int i = 0; i < GetSize(mem.rd_ports); i++)
 			{
@@ -1002,7 +1002,7 @@ struct FirrtlWorker
 				string port_name(stringf("%s.r%d", mem_id, i));
 
 				if (port.clk_enable)
-					log_error("Clocked read port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
+					log_error("Clocked read port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
 
 				std::ostringstream rpe;
 
@@ -1023,12 +1023,12 @@ struct FirrtlWorker
 				string port_name(stringf("%s.w%d", mem_id, i));
 
 				if (!port.clk_enable)
-					log_error("Unclocked write port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
+					log_error("Unclocked write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
 				if (!port.clk_polarity)
-					log_error("Negedge write port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
+					log_error("Negedge write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
 				for (int i = 1; i < GetSize(port.en); i++)
 					if (port.en[0] != port.en[i])
-						log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, mem.memid.unescape());
+						log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
 
 				std::ostringstream wpe;
 
diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc
index d67bc9143..40d0e6e8e 100644
--- a/backends/functional/cxx.cc
+++ b/backends/functional/cxx.cc
@@ -89,7 +89,7 @@ struct CxxStruct {
 		}
 		f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
 		for (auto p : types) {
-			f.print("\t\t\tfn(\"{}\", {});\n", p.first.unescape(), scope(p.first, p.first));
+			f.print("\t\t\tfn(\"{}\", {});\n", design->twines.unescaped_str(p.first), scope(p.first, p.first));
 		}
 		f.print("\t\t}}\n");
 		f.print("\t}};\n\n");
@@ -151,8 +151,8 @@ template<class NodePrinter> struct CxxPrintVisitor : public Functional::Abstract
 	void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
 	void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
 	void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); }
-	void input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); print("input.{}", input_struct[name]); }
-	void state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); print("current_state.{}", state_struct[name]); }
+	void input(Node, IdString name, IdString kind) override { log_assert(kind == TW($input)); print("input.{}", input_struct[name]); }
+	void state(Node, IdString name, IdString kind) override { log_assert(kind == TW($state)); print("current_state.{}", state_struct[name]); }
 	void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
 	void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
 };
diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc
index 0451af4c7..00555bc6c 100644
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@@ -80,7 +80,7 @@ public:
 	SmtStruct(std::string name, SmtScope &scope) : scope(scope), name(name) {}
 	void insert(IdString field_name, SmtSort sort) {
 		field_names(field_name);
-		auto accessor = scope.unique_name("\\" + name + "_" + field_name.unescape());
+		auto accessor = scope.unique_name("\\" + name + "_" + design->twines.unescaped_str(field_name));
 		fields.emplace_back(Field{sort, accessor});
 	}
 	void write_definition(SExprWriter &w) {
@@ -179,8 +179,8 @@ struct SmtPrintVisitor : public Functional::AbstractVisitor<SExpr> {
 	SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
 	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
 
-	SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); }
-	SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); }
+	SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == TW($input)); return input_struct.access("inputs", name); }
+	SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == TW($state)); return state_struct.access("state", name); }
 };
 
 struct SmtModule {
diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc
index b37f948b6..7b6275d48 100644
--- a/backends/functional/smtlib_rosette.cc
+++ b/backends/functional/smtlib_rosette.cc
@@ -180,8 +180,8 @@ struct SmtrPrintVisitor : public Functional::AbstractVisitor<SExpr> {
 	SExpr memory_read(Node, Node mem, Node addr) override { return list("list-ref-bv", n(mem), n(addr)); }
 	SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("list-set-bv", n(mem), n(addr), n(data)); }
 
-	SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); }
-	SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); }
+	SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == TW($input)); return input_struct.access("inputs", name); }
+	SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == TW($state)); return state_struct.access("state", name); }
 };
 
 struct SmtrModule {
@@ -281,7 +281,7 @@ struct SmtrModule {
 			w.push();
 			w.open(list());
 			w.open(list("assoc-result"));
-			w << list("assoc", "\"" + input->name.unescape() + "\"", inputs_name);
+			w << list("assoc", "\"" + design->twines.unescaped_str(input->name) + "\"", inputs_name);
 			w.pop();
 			w.open(list("if", "assoc-result"));
 			w << list("cdr", "assoc-result");
@@ -298,7 +298,7 @@ struct SmtrModule {
 		w << list(*output_helper_name, outputs_name);
 		w.open(list("list"));
 		for (auto output : ir.outputs()) {
-			w << list("cons", "\"" + output->name.unescape() + "\"", output_struct.access("outputs", output->name));
+			w << list("cons", "\"" + design->twines.unescaped_str(output->name) + "\"", output_struct.access("outputs", output->name));
 		}
 		w.pop();
 	}
diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc
index 343fcfc0f..0c6336b92 100644
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@@ -146,11 +146,11 @@ struct FunctionalTestGeneric : public Pass
             log("Dumping module `%s'.\n", module->name);
 			auto fir = Functional::IR::from_module(module);
 			for(auto node : fir)
-				std::cout << node.name().unescape() << " = " << node.to_string([](auto n) { return n.name().unescape(); }) << "\n";
+				std::cout << design->twines.unescaped_str(node.name()) << " = " << node.to_string([](auto n) { return design->twines.unescaped_str(n.name()); }) << "\n";
 			for(auto output : fir.all_outputs())
-				std::cout << output->kind.unescape() << " " << output->name.unescape() << " = " << output->value().name().unescape() << "\n";
+				std::cout << design->twines.unescaped_str(output->kind) << " " << design->twines.unescaped_str(output->name) << " = " << design->twines.unescaped_str(output->value().name()) << "\n";
 			for(auto state : fir.all_states())
-				std::cout << state->kind.unescape() << " " << state->name.unescape() << " = " << state->next_value().name().unescape() << "\n";
+				std::cout << design->twines.unescaped_str(state->kind) << " " << design->twines.unescaped_str(state->name) << " = " << design->twines.unescaped_str(state->next_value().name()) << "\n";
 		}
 	}
 } FunctionalCxxBackend;
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 1d48e49fd..678157493 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -41,7 +41,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
 		return stringf("CONST_%d_0x%x", sig.size(), sig.as_int());
 	}
 
-	return sig.as_wire()->name.unescape();
+	return design->twines.unescaped_str(sig.as_wire()->name);
 }
 
 struct IntersynthBackend : public Backend {
@@ -151,8 +151,8 @@ struct IntersynthBackend : public Backend {
 				if (wire->port_input || wire->port_output) {
 					celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
 							wire->name.unescape(), wire->width, wire->port_input ? "*" : "",
-							wire->port_input ? "input" : "output", wire->name.unescape(), wire->width, wire->name.unescape()));
-					netlists_code += stringf("node %s %s PORT %s\n", wire->name.unescape(), wire->name.unescape(),
+							wire->port_input ? "input" : "output", design->twines.unescaped_str(wire->name), wire->width, design->twines.unescaped_str(wire->name)));
+					netlists_code += stringf("node %s %s PORT %s\n", design->twines.unescaped_str(wire->name), design->twines.unescaped_str(wire->name),
 							netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
 				}
 			}
@@ -162,28 +162,28 @@ struct IntersynthBackend : public Backend {
 			{
 				std::string celltype_code, node_code;
 
-				if (!ct.cell_known(cell->type))
-					log_error("Found unknown cell type %s in module!\n", cell->type.unescape());
+				if (!ct.cell_known(cell->type_impl))
+					log_error("Found unknown cell type %s in module!\n", cell->type.unescaped());
 
-				celltype_code = stringf("celltype %s", cell->type.unescape());
-				node_code = stringf("node %s %s", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
+				celltype_code = stringf("celltype %s", cell->type.unescaped());
+				node_code = stringf("node %s %s", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
 				for (auto &port : cell->connections()) {
 					RTLIL::SigSpec sig = sigmap(port.second);
 					if (sig.size() != 0) {
 						conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
 						std::string port_name = design->twines.str(port.first);
-						celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", port_name.c_str());
+						celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type_impl, port.first) ? "*" : "", port_name.c_str());
 						node_code += stringf(" %s %s", port_name.c_str(), netname(conntypes_code, celltypes_code, constcells_code, sig));
 					}
 				}
 				for (auto &param : cell->parameters) {
-					celltype_code += stringf(" cfg:%d %s", int(param.second.size()), param.first.unescape());
+					celltype_code += stringf(" cfg:%d %s", int(param.second.size()), design->twines.unescaped_str(param.first));
 					if (param.second.size() != 32) {
-						node_code += stringf(" %s '", param.first.unescape());
+						node_code += stringf(" %s '", design->twines.unescaped_str(param.first));
 						for (int i = param.second.size()-1; i >= 0; i--)
 							node_code += param.second[i] == State::S1 ? "1" : "0";
 					} else
-						node_code += stringf(" %s 0x%x", param.first.unescape(), param.second.as_int());
+						node_code += stringf(" %s 0x%x", design->twines.unescaped_str(param.first), param.second.as_int());
 				}
 
 				celltypes_code.insert(celltype_code + "\n");
diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc
index cd7138c46..cbda7729c 100644
--- a/backends/jny/jny.cc
+++ b/backends/jny/jny.cc
@@ -91,7 +91,7 @@ struct JnyWriter
         {
             _cells.clear();
             for (auto cell : mod->cells()) {
-                const auto cell_type = escape_string(cell->type.unescape());
+                const auto cell_type = design->twines.unescaped_str(escape_string(cell->type));
 
                 if (_cells.find(cell_type) == _cells.end())
                     _cells.emplace(cell_type, std::vector<Cell*>());
@@ -353,10 +353,10 @@ struct JnyWriter
                 f << stringf(",\n");
             const auto param_val = param.second;
             if (!param_val.empty()) {
-                f << stringf("  %s\"%s\": ", _indent, escape_string(param.first.unescape()));
+                f << stringf("  %s\"%s\": ", _indent, design->twines.unescaped_str(escape_string(param.first)));
                 write_param_val(param_val);
             } else {
-                f << stringf("  %s\"%s\": true", _indent, escape_string(param.first.unescape()));
+                f << stringf("  %s\"%s\": true", _indent, design->twines.unescaped_str(escape_string(param.first)));
             }
 
             first_param = false;
diff --git a/backends/json/json.cc b/backends/json/json.cc
index a9c2e6dac..408fdc14b 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -76,7 +76,7 @@ struct JsonWriter
 
 	string get_name(IdString name)
 	{
-		return get_string(name.unescape());
+		return design->twines.unescaped_str(get_string(name));
 	}
 
 	string get_name(TwineRef name)
@@ -205,7 +205,7 @@ struct JsonWriter
 		for (auto c : module->cells()) {
 			if (use_selection && !module->selected(c))
 				continue;
-			if (!scopeinfo_mode && c->type == ID($scopeinfo))
+			if (!scopeinfo_mode && c->type == TW($scopeinfo))
 				continue;
 			f << stringf("%s\n", first ? "" : ",");
 			f << stringf("        %s: {\n", get_name(c->name));
diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc
index 7e5ab5f3e..a150d9b92 100644
--- a/backends/simplec/simplec.cc
+++ b/backends/simplec/simplec.cc
@@ -378,7 +378,7 @@ struct SimplecWorker
 
 	void eval_cell(HierDirtyFlags *work, Cell *cell)
 	{
-		if (cell->type.in(ID($_BUF_), ID($_NOT_)))
+		if (cell->type.in(TW($_BUF_), TW($_NOT_)))
 		{
 			SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
 			SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
@@ -386,18 +386,18 @@ struct SimplecWorker
 			string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
 			string expr;
 
-			if (cell->type == ID($_BUF_))  expr = a_expr;
-			if (cell->type == ID($_NOT_))  expr = "!" + a_expr;
+			if (cell->type == TW($_BUF_))  expr = a_expr;
+			if (cell->type == TW($_NOT_))  expr = "!" + a_expr;
 
 			log_assert(y.wire);
 			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
-					stringf(" // %s (%s)", cell, cell->type.unescape()));
+					stringf(" // %s (%s)", cell, cell->type.unescaped()));
 
 			work->set_dirty(y);
 			return;
 		}
 
-		if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
+		if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
 		{
 			SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
 			SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@@ -407,24 +407,24 @@ struct SimplecWorker
 			string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
 			string expr;
 
-			if (cell->type == ID($_AND_))    expr = stringf("%s & %s",    a_expr, b_expr);
-			if (cell->type == ID($_NAND_))   expr = stringf("!(%s & %s)", a_expr, b_expr);
-			if (cell->type == ID($_OR_))     expr = stringf("%s | %s",    a_expr, b_expr);
-			if (cell->type == ID($_NOR_))    expr = stringf("!(%s | %s)", a_expr, b_expr);
-			if (cell->type == ID($_XOR_))    expr = stringf("%s ^ %s",    a_expr, b_expr);
-			if (cell->type == ID($_XNOR_))   expr = stringf("!(%s ^ %s)", a_expr, b_expr);
-			if (cell->type == ID($_ANDNOT_)) expr = stringf("%s & (!%s)", a_expr, b_expr);
-			if (cell->type == ID($_ORNOT_))  expr = stringf("%s | (!%s)", a_expr, b_expr);
+			if (cell->type == TW($_AND_))    expr = stringf("%s & %s",    a_expr, b_expr);
+			if (cell->type == TW($_NAND_))   expr = stringf("!(%s & %s)", a_expr, b_expr);
+			if (cell->type == TW($_OR_))     expr = stringf("%s | %s",    a_expr, b_expr);
+			if (cell->type == TW($_NOR_))    expr = stringf("!(%s | %s)", a_expr, b_expr);
+			if (cell->type == TW($_XOR_))    expr = stringf("%s ^ %s",    a_expr, b_expr);
+			if (cell->type == TW($_XNOR_))   expr = stringf("!(%s ^ %s)", a_expr, b_expr);
+			if (cell->type == TW($_ANDNOT_)) expr = stringf("%s & (!%s)", a_expr, b_expr);
+			if (cell->type == TW($_ORNOT_))  expr = stringf("%s | (!%s)", a_expr, b_expr);
 
 			log_assert(y.wire);
 			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
-					stringf(" // %s (%s)", cell, cell->type.unescape()));
+					stringf(" // %s (%s)", cell, cell->type.unescaped()));
 
 			work->set_dirty(y);
 			return;
 		}
 
-		if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
+		if (cell->type.in(TW($_AOI3_), TW($_OAI3_)))
 		{
 			SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
 			SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@@ -436,18 +436,18 @@ struct SimplecWorker
 			string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
 			string expr;
 
-			if (cell->type == ID($_AOI3_)) expr = stringf("!((%s & %s) | %s)", a_expr, b_expr, c_expr);
-			if (cell->type == ID($_OAI3_)) expr = stringf("!((%s | %s) & %s)", a_expr, b_expr, c_expr);
+			if (cell->type == TW($_AOI3_)) expr = stringf("!((%s & %s) | %s)", a_expr, b_expr, c_expr);
+			if (cell->type == TW($_OAI3_)) expr = stringf("!((%s | %s) & %s)", a_expr, b_expr, c_expr);
 
 			log_assert(y.wire);
 			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
-					stringf(" // %s (%s)", cell, cell->type.unescape()));
+					stringf(" // %s (%s)", cell, cell->type.unescaped()));
 
 			work->set_dirty(y);
 			return;
 		}
 
-		if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
+		if (cell->type.in(TW($_AOI4_), TW($_OAI4_)))
 		{
 			SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
 			SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@@ -461,18 +461,18 @@ struct SimplecWorker
 			string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0";
 			string expr;
 
-			if (cell->type == ID($_AOI4_)) expr = stringf("!((%s & %s) | (%s & %s))", a_expr, b_expr, c_expr, d_expr);
-			if (cell->type == ID($_OAI4_)) expr = stringf("!((%s | %s) & (%s | %s))", a_expr, b_expr, c_expr, d_expr);
+			if (cell->type == TW($_AOI4_)) expr = stringf("!((%s & %s) | (%s & %s))", a_expr, b_expr, c_expr, d_expr);
+			if (cell->type == TW($_OAI4_)) expr = stringf("!((%s | %s) & (%s | %s))", a_expr, b_expr, c_expr, d_expr);
 
 			log_assert(y.wire);
 			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
-					stringf(" // %s (%s)", cell, cell->type.unescape()));
+					stringf(" // %s (%s)", cell, cell->type.unescaped()));
 
 			work->set_dirty(y);
 			return;
 		}
 
-		if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
+		if (cell->type.in(TW($_MUX_), TW($_NMUX_)))
 		{
 			SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
 			SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
@@ -485,18 +485,18 @@ struct SimplecWorker
 
 			// casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933)
 			string expr = stringf("%s ? %s(bool)%s : %s(bool)%s", s_expr,
-					cell->type == ID($_NMUX_) ? "!" : "", b_expr,
-					cell->type == ID($_NMUX_) ? "!" : "", a_expr);
+					cell->type == TW($_NMUX_) ? "!" : "", b_expr,
+					cell->type == TW($_NMUX_) ? "!" : "", a_expr);
 
 			log_assert(y.wire);
 			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
-					stringf(" // %s (%s)", cell, cell->type.unescape()));
+					stringf(" // %s (%s)", cell, cell->type.unescaped()));
 
 			work->set_dirty(y);
 			return;
 		}
 
-		log_error("No C model for %s available at the moment (FIXME).\n", cell->type.unescape());
+		log_error("No C model for %s available at the moment (FIXME).\n", cell->type.unescaped());
 	}
 
 	void eval_dirty(HierDirtyFlags *work)
@@ -579,7 +579,7 @@ struct SimplecWorker
 					string hiername = work->log_prefix + "." + cell->module->design->twines.str(cell->meta_->name);
 
 					if (verbose)
-						log("    Evaluating %s (%s, best of %d).\n", hiername, cell->type.unescape(), GetSize(work->dirty_cells));
+						log("    Evaluating %s (%s, best of %d).\n", hiername, cell->type.unescaped(), GetSize(work->dirty_cells));
 
 					if (activated_cells.count(hiername))
 						reactivated_cells.insert(hiername);
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 67b4216b9..288e1c091 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -60,7 +60,7 @@ struct Smt2Worker
 	const char *get_id(IdString n)
 	{
 		if (ids.count(n) == 0) {
-			std::string str = n.unescape();
+			std::string str = design->twines.unescaped_str(n);
 			for (int i = 0; i < GetSize(str); i++) {
 				if (str[i] == '\\')
 					str[i] = '/';
@@ -196,8 +196,8 @@ struct Smt2Worker
 				continue;
 			}
 
-			bool is_input = ct.cell_input(cell->type, conn.first);
-			bool is_output = ct.cell_output(cell->type, conn.first);
+			bool is_input = ct.cell_input(cell->type_impl, conn.first);
+			bool is_output = ct.cell_output(cell->type_impl, conn.first);
 
 			if (is_output && !is_input)
 				for (auto bit : sigmap(conn.second)) {
@@ -207,11 +207,11 @@ struct Smt2Worker
 				}
 			else if (is_output || !is_input)
 				log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
-						module->design->twines.str(conn.first).c_str(), module, cell, cell->type.unescape());
+						module->design->twines.str(conn.first).c_str(), module, cell, cell->type.unescaped());
 
-			if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && (conn.first == TW::CLK || conn.first == TW::C))
+			if (cell->type.in(TW($dff), TW($_DFF_P_), TW($_DFF_N_)) && (conn.first == TW::CLK || conn.first == TW::C))
 			{
-				bool posedge = (cell->type == ID($_DFF_N_)) || (cell->type == ID($dff) && cell->getParam(ID::CLK_POLARITY).as_bool());
+				bool posedge = (cell->type == TW($_DFF_N_)) || (cell->type == TW($dff) && cell->getParam(ID::CLK_POLARITY).as_bool());
 				for (auto bit : sigmap(conn.second)) {
 					if (posedge)
 						clock_posedge.insert(bit);
@@ -546,7 +546,7 @@ struct Smt2Worker
 	{
 		if (verbose)
 			log("%*s=> export_cell %s (%s) [%s]\n", 2+2*GetSize(recursive_cells), "",
-					cell, cell->type.unescape(), exported_cells.count(cell) ? "old" : "new");
+					cell, cell->type.unescaped(), exported_cells.count(cell) ? "old" : "new");
 
 		if (recursive_cells.count(cell))
 			log_error("Found logic loop in module %s! See cell %s.\n", get_id(module), get_id(cell));
@@ -557,7 +557,7 @@ struct Smt2Worker
 		exported_cells.insert(cell);
 		recursive_cells.insert(cell);
 
-		if (cell->type == ID($initstate))
+		if (cell->type == TW($initstate))
 		{
 			SigBit bit = sigmap(cell->getPort(TW::Y).as_bit());
 			decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
@@ -567,7 +567,7 @@ struct Smt2Worker
 			return;
 		}
 
-		if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
+		if (cell->type.in(TW($_FF_), TW($_DFF_P_), TW($_DFF_N_)))
 		{
 			registers.insert(cell);
 			SigBit q_bit = cell->getPort(TW::Q);
@@ -579,28 +579,28 @@ struct Smt2Worker
 			return;
 		}
 
-		if (cell->type == ID($_BUF_)) return export_gate(cell, "A");
-		if (cell->type == ID($_NOT_)) return export_gate(cell, "(not A)");
-		if (cell->type == ID($_AND_)) return export_gate(cell, "(and A B)");
-		if (cell->type == ID($_NAND_)) return export_gate(cell, "(not (and A B))");
-		if (cell->type == ID($_OR_)) return export_gate(cell, "(or A B)");
-		if (cell->type == ID($_NOR_)) return export_gate(cell, "(not (or A B))");
-		if (cell->type == ID($_XOR_)) return export_gate(cell, "(xor A B)");
-		if (cell->type == ID($_XNOR_)) return export_gate(cell, "(not (xor A B))");
-		if (cell->type == ID($_ANDNOT_)) return export_gate(cell, "(and A (not B))");
-		if (cell->type == ID($_ORNOT_)) return export_gate(cell, "(or A (not B))");
-		if (cell->type == ID($_MUX_)) return export_gate(cell, "(ite S B A)");
-		if (cell->type == ID($_NMUX_)) return export_gate(cell, "(not (ite S B A))");
-		if (cell->type == ID($_AOI3_)) return export_gate(cell, "(not (or (and A B) C))");
-		if (cell->type == ID($_OAI3_)) return export_gate(cell, "(not (and (or A B) C))");
-		if (cell->type == ID($_AOI4_)) return export_gate(cell, "(not (or (and A B) (and C D)))");
-		if (cell->type == ID($_OAI4_)) return export_gate(cell, "(not (and (or A B) (or C D)))");
+		if (cell->type == TW($_BUF_)) return export_gate(cell, "A");
+		if (cell->type == TW($_NOT_)) return export_gate(cell, "(not A)");
+		if (cell->type == TW($_AND_)) return export_gate(cell, "(and A B)");
+		if (cell->type == TW($_NAND_)) return export_gate(cell, "(not (and A B))");
+		if (cell->type == TW($_OR_)) return export_gate(cell, "(or A B)");
+		if (cell->type == TW($_NOR_)) return export_gate(cell, "(not (or A B))");
+		if (cell->type == TW($_XOR_)) return export_gate(cell, "(xor A B)");
+		if (cell->type == TW($_XNOR_)) return export_gate(cell, "(not (xor A B))");
+		if (cell->type == TW($_ANDNOT_)) return export_gate(cell, "(and A (not B))");
+		if (cell->type == TW($_ORNOT_)) return export_gate(cell, "(or A (not B))");
+		if (cell->type == TW($_MUX_)) return export_gate(cell, "(ite S B A)");
+		if (cell->type == TW($_NMUX_)) return export_gate(cell, "(not (ite S B A))");
+		if (cell->type == TW($_AOI3_)) return export_gate(cell, "(not (or (and A B) C))");
+		if (cell->type == TW($_OAI3_)) return export_gate(cell, "(not (and (or A B) C))");
+		if (cell->type == TW($_AOI4_)) return export_gate(cell, "(not (or (and A B) (and C D)))");
+		if (cell->type == TW($_OAI4_)) return export_gate(cell, "(not (and (or A B) (or C D)))");
 
 		// FIXME: $lut
 
 		if (bvmode)
 		{
-			if (cell->type.in(ID($ff), ID($dff)))
+			if (cell->type.in(TW($ff), TW($dff)))
 			{
 				registers.insert(cell);
 				int smtoffset = 0;
@@ -615,9 +615,9 @@ struct Smt2Worker
 				return;
 			}
 
-			if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq)))
+			if (cell->type.in(TW($anyconst), TW($anyseq), TW($anyinit), TW($allconst), TW($allseq)))
 			{
-				auto QY = cell->type == ID($anyinit) ? TW::Q : TW::Y;
+				auto QY = cell->type == TW($anyinit) ? TW::Q : TW::Y;
 				registers.insert(cell);
 				string infostr;
 				if (cell->has_attribute(ID::src)) {
@@ -637,8 +637,8 @@ struct Smt2Worker
 					log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str());
 				}
 
-				bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst));
-				bool clk2fflogic = cell->type == ID($anyinit) && cell->get_bool_attribute(ID(clk2fflogic));
+				bool init_only = cell->type.in(TW($anyconst), TW($anyinit), TW($allconst));
+				bool clk2fflogic = cell->type == TW($anyinit) && cell->get_bool_attribute(ID(clk2fflogic));
 				int smtoffset = 0;
 				for (auto chunk : cell->getPort(clk2fflogic ? TW::D : QY).chunks()) {
 					if (chunk.is_wire())
@@ -647,27 +647,27 @@ struct Smt2Worker
 				}
 
 				makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(QY)), log_signal(cell->getPort(QY)));
-				if (cell->type == ID($anyseq))
+				if (cell->type == TW($anyseq))
 					ex_input_eq.push_back(stringf("  (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
 				register_bv(cell->getPort(QY), idcounter++);
 				recursive_cells.erase(cell);
 				return;
 			}
 
-			if (cell->type == ID($and)) return export_bvop(cell, "(bvand A B)");
-			if (cell->type == ID($or)) return export_bvop(cell, "(bvor A B)");
-			if (cell->type == ID($xor)) return export_bvop(cell, "(bvxor A B)");
-			if (cell->type == ID($xnor)) return export_bvop(cell, "(bvxnor A B)");
+			if (cell->type == TW($and)) return export_bvop(cell, "(bvand A B)");
+			if (cell->type == TW($or)) return export_bvop(cell, "(bvor A B)");
+			if (cell->type == TW($xor)) return export_bvop(cell, "(bvxor A B)");
+			if (cell->type == TW($xnor)) return export_bvop(cell, "(bvxnor A B)");
 
-			if (cell->type == ID($bweqx)) return export_bvop(cell, "(bvxnor A B)", 'U');
-			if (cell->type == ID($bwmux)) return export_bvop(cell, "(bvor (bvand A (bvnot S)) (bvand B S))", 'U');
+			if (cell->type == TW($bweqx)) return export_bvop(cell, "(bvxnor A B)", 'U');
+			if (cell->type == TW($bwmux)) return export_bvop(cell, "(bvor (bvand A (bvnot S)) (bvand B S))", 'U');
 
-			if (cell->type == ID($shl)) return export_bvop(cell, "(bvshl A B)", 's');
-			if (cell->type == ID($shr)) return export_bvop(cell, "(bvlshr A B)", 's');
-			if (cell->type == ID($sshl)) return export_bvop(cell, "(bvshl A B)", 's');
-			if (cell->type == ID($sshr)) return export_bvop(cell, "(bvLshr A B)", 's');
+			if (cell->type == TW($shl)) return export_bvop(cell, "(bvshl A B)", 's');
+			if (cell->type == TW($shr)) return export_bvop(cell, "(bvlshr A B)", 's');
+			if (cell->type == TW($sshl)) return export_bvop(cell, "(bvshl A B)", 's');
+			if (cell->type == TW($sshr)) return export_bvop(cell, "(bvLshr A B)", 's');
 
-			if (cell->type.in(ID($shift), ID($shiftx))) {
+			if (cell->type.in(TW($shift), TW($shiftx))) {
 				if (cell->getParam(ID::B_SIGNED).as_bool()) {
 					return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
 							"(bvlshr A B) (bvshl A (bvneg B)))",
@@ -677,28 +677,28 @@ struct Smt2Worker
 				}
 			}
 
-			if (cell->type == ID($lt)) return export_bvop(cell, "(bvUlt A B)", 'b');
-			if (cell->type == ID($le)) return export_bvop(cell, "(bvUle A B)", 'b');
-			if (cell->type == ID($ge)) return export_bvop(cell, "(bvUge A B)", 'b');
-			if (cell->type == ID($gt)) return export_bvop(cell, "(bvUgt A B)", 'b');
+			if (cell->type == TW($lt)) return export_bvop(cell, "(bvUlt A B)", 'b');
+			if (cell->type == TW($le)) return export_bvop(cell, "(bvUle A B)", 'b');
+			if (cell->type == TW($ge)) return export_bvop(cell, "(bvUge A B)", 'b');
+			if (cell->type == TW($gt)) return export_bvop(cell, "(bvUgt A B)", 'b');
 
-			if (cell->type == ID($ne)) return export_bvop(cell, "(distinct A B)", 'b');
-			if (cell->type == ID($nex)) return export_bvop(cell, "(distinct A B)", 'b');
-			if (cell->type == ID($eq)) return export_bvop(cell, "(= A B)", 'b');
-			if (cell->type == ID($eqx)) return export_bvop(cell, "(= A B)", 'b');
+			if (cell->type == TW($ne)) return export_bvop(cell, "(distinct A B)", 'b');
+			if (cell->type == TW($nex)) return export_bvop(cell, "(distinct A B)", 'b');
+			if (cell->type == TW($eq)) return export_bvop(cell, "(= A B)", 'b');
+			if (cell->type == TW($eqx)) return export_bvop(cell, "(= A B)", 'b');
 
-			if (cell->type == ID($not)) return export_bvop(cell, "(bvnot A)");
-			if (cell->type == ID($pos)) return export_bvop(cell, "A");
-			if (cell->type == ID($neg)) return export_bvop(cell, "(bvneg A)");
+			if (cell->type == TW($not)) return export_bvop(cell, "(bvnot A)");
+			if (cell->type == TW($pos)) return export_bvop(cell, "A");
+			if (cell->type == TW($neg)) return export_bvop(cell, "(bvneg A)");
 
-			if (cell->type == ID($add)) return export_bvop(cell, "(bvadd A B)");
-			if (cell->type == ID($sub)) return export_bvop(cell, "(bvsub A B)");
-			if (cell->type == ID($mul)) return export_bvop(cell, "(bvmul A B)");
-			if (cell->type == ID($div)) return export_bvop(cell, "(bvUdiv A B)", 'd');
+			if (cell->type == TW($add)) return export_bvop(cell, "(bvadd A B)");
+			if (cell->type == TW($sub)) return export_bvop(cell, "(bvsub A B)");
+			if (cell->type == TW($mul)) return export_bvop(cell, "(bvmul A B)");
+			if (cell->type == TW($div)) return export_bvop(cell, "(bvUdiv A B)", 'd');
 			// "rem" = truncating modulo
-			if (cell->type == ID($mod)) return export_bvop(cell, "(bvUrem A B)", 'd');
+			if (cell->type == TW($mod)) return export_bvop(cell, "(bvUrem A B)", 'd');
 			// "mod" = flooring modulo
-			if (cell->type == ID($modfloor)) {
+			if (cell->type == TW($modfloor)) {
 				// bvumod doesn't exist because it's the same as bvurem
 				if (cell->getParam(ID::A_SIGNED).as_bool()) {
 					return export_bvop(cell, "(bvsmod A B)", 'd');
@@ -707,7 +707,7 @@ struct Smt2Worker
 				}
 			}
 			// "div" = flooring division
-			if (cell->type == ID($divfloor)) {
+			if (cell->type == TW($divfloor)) {
 				if (cell->getParam(ID::A_SIGNED).as_bool()) {
 					// bvsdiv is truncating division, so we can't use it here.
 					int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
@@ -728,24 +728,24 @@ struct Smt2Worker
 				}
 			}
 
-			if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) &&
+			if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool)) &&
 					2*GetSize(cell->getPort(TW::A).chunks()) < GetSize(cell->getPort(TW::A))) {
-				bool is_and = cell->type == ID($reduce_and);
+				bool is_and = cell->type == TW($reduce_and);
 				string bits(GetSize(cell->getPort(TW::A)), is_and ? '1' : '0');
 				return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits), 'b');
 			}
 
-			if (cell->type == ID($reduce_and)) return export_reduce(cell, "(and A)", true);
-			if (cell->type == ID($reduce_or)) return export_reduce(cell, "(or A)", false);
-			if (cell->type == ID($reduce_xor)) return export_reduce(cell, "(xor A)", false);
-			if (cell->type == ID($reduce_xnor)) return export_reduce(cell, "(not (xor A))", false);
-			if (cell->type == ID($reduce_bool)) return export_reduce(cell, "(or A)", false);
+			if (cell->type == TW($reduce_and)) return export_reduce(cell, "(and A)", true);
+			if (cell->type == TW($reduce_or)) return export_reduce(cell, "(or A)", false);
+			if (cell->type == TW($reduce_xor)) return export_reduce(cell, "(xor A)", false);
+			if (cell->type == TW($reduce_xnor)) return export_reduce(cell, "(not (xor A))", false);
+			if (cell->type == TW($reduce_bool)) return export_reduce(cell, "(or A)", false);
 
-			if (cell->type == ID($logic_not)) return export_reduce(cell, "(not (or A))", false);
-			if (cell->type == ID($logic_and)) return export_reduce(cell, "(and (or A) (or B))", false);
-			if (cell->type == ID($logic_or)) return export_reduce(cell, "(or A B)", false);
+			if (cell->type == TW($logic_not)) return export_reduce(cell, "(not (or A))", false);
+			if (cell->type == TW($logic_and)) return export_reduce(cell, "(and (or A) (or B))", false);
+			if (cell->type == TW($logic_or)) return export_reduce(cell, "(or A B)", false);
 
-			if (cell->type.in(ID($mux), ID($pmux)))
+			if (cell->type.in(TW($mux), TW($pmux)))
 			{
 				int width = GetSize(cell->getPort(TW::Y));
 				std::string processed_expr = get_bv(cell->getPort(TW::A));
@@ -798,7 +798,7 @@ struct Smt2Worker
 			if (has_async_wr && has_sync_wr)
 				log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", cell, module);
 
-			decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", mem->memid.unescape(), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
+			decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", design->twines.unescaped_str(mem->memid), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
 			decls.push_back(witness_memory(get_id(mem->memid), cell, mem));
 
 			string memstate;
@@ -823,7 +823,7 @@ struct Smt2Worker
 
 					if (port.clk_enable)
 						log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
-								"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), mem->memid.unescape(), module);
+								"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), design->twines.unescaped_str(mem->memid), module);
 
 					decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
 							get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
@@ -867,7 +867,7 @@ struct Smt2Worker
 
 					if (port.clk_enable)
 						log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
-								"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), mem->memid.unescape(), module);
+								"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), design->twines.unescaped_str(mem->memid), module);
 
 					decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
 							get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
@@ -936,15 +936,15 @@ struct Smt2Worker
 			return;
 		}
 
-		if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
+		if (cell->type.in(TW($dffe), TW($sdff), TW($sdffe), TW($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
 			log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smt2`.\n",
 					cell->type.unescape(), module, cell);
 		}
-		if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
+		if (cell->type.in(TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
 			log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smt2`.\n",
 					cell->type.unescape(), module, cell);
 		}
-		if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
+		if (cell->type.in(TW($sr), TW($dlatch), TW($adlatch), TW($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
 			log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_smt2`.\n",
 					cell->type, module, cell);
 		}
@@ -973,7 +973,7 @@ struct Smt2Worker
 
 		pool<SigBit> reg_bits;
 		for (auto cell : module->cells())
-			if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_), ID($anyinit))) {
+			if (cell->type.in(TW($ff), TW($dff), TW($_FF_), TW($_DFF_P_), TW($_DFF_N_), TW($anyinit))) {
 				// not using sigmap -- we want the net directly at the dff output
 				for (auto bit : cell->getPort(TW::Q))
 					reg_bits.insert(bit);
@@ -1117,15 +1117,15 @@ struct Smt2Worker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($assert), ID($assume), ID($cover)))
+			if (cell->type.in(TW($assert), TW($assume), TW($cover)))
 			{
-				int &id = cell->type == ID($assert) ? assert_id :
-						cell->type == ID($assume) ? assume_id :
-						cell->type == ID($cover) ? cover_id : *(int*)nullptr;
+				int &id = cell->type == TW($assert) ? assert_id :
+						cell->type == TW($assume) ? assume_id :
+						cell->type == TW($cover) ? cover_id : *(int*)nullptr;
 
-				char postfix = cell->type == ID($assert) ? 'a' :
-						cell->type == ID($assume) ? 'u' :
-						cell->type == ID($cover) ? 'c' : 0;
+				char postfix = cell->type == TW($assert) ? 'a' :
+						cell->type == TW($assume) ? 'u' :
+						cell->type == TW($cover) ? 'c' : 0;
 
 				string name_a = get_bool(cell->getPort(TW::A));
 				string name_en = get_bool(cell->getPort(TW::EN));
@@ -1147,16 +1147,16 @@ struct Smt2Worker
 				else
 					decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, get_id(cell)));
 
-				if (cell->type == ID($cover))
+				if (cell->type == TW($cover))
 					decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
 							get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
 				else
 					decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n",
 							get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
 
-				if (cell->type == ID($assert))
+				if (cell->type == TW($assert))
 					assert_list.push_back(stringf("(|%s_a %d| state)", get_id(module), id));
-				else if (cell->type == ID($assume))
+				else if (cell->type == TW($assume))
 					assume_list.push_back(stringf("(|%s_u %d| state)", get_id(module), id));
 
 				id++;
@@ -1212,7 +1212,7 @@ struct Smt2Worker
 
 			for (auto cell : this_regs)
 			{
-				if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
+				if (cell->type.in(TW($_FF_), TW($_DFF_P_), TW($_DFF_N_)))
 				{
 					std::string expr_d = get_bool(cell->getPort(TW::D));
 					std::string expr_q = get_bool(cell->getPort(TW::Q), "next_state");
@@ -1220,7 +1220,7 @@ struct Smt2Worker
 					ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(TW::Q)), get_bool(cell->getPort(TW::Q), "other_state")));
 				}
 
-				if (cell->type.in(ID($ff), ID($dff), ID($anyinit)))
+				if (cell->type.in(TW($ff), TW($dff), TW($anyinit)))
 				{
 					std::string expr_d = get_bv(cell->getPort(TW::D));
 					std::string expr_q = get_bv(cell->getPort(TW::Q), "next_state");
@@ -1228,12 +1228,12 @@ struct Smt2Worker
 					ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Q)), get_bv(cell->getPort(TW::Q), "other_state")));
 				}
 
-				if (cell->type.in(ID($anyconst), ID($allconst)))
+				if (cell->type.in(TW($anyconst), TW($allconst)))
 				{
 					std::string expr_d = get_bv(cell->getPort(TW::Y));
 					std::string expr_q = get_bv(cell->getPort(TW::Y), "next_state");
 					trans.push_back(stringf("  (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Y))));
-					if (cell->type == ID($anyconst))
+					if (cell->type == TW($anyconst))
 						ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Y)), get_bv(cell->getPort(TW::Y), "other_state")));
 				}
 			}
@@ -1882,7 +1882,7 @@ struct Smt2Backend : public Backend {
 				for (auto &dep : it.second)
 					if (module_deps.count(dep) > 0)
 						goto not_ready_yet;
-				// log("Next in topological sort: %s\n", it.first->name.unescape());
+				// log("Next in topological sort: %s\n", design->twines.unescaped_str(it.first->name));
 				sorted_modules.push_back(it.first);
 			not_ready_yet:;
 			}
@@ -1899,7 +1899,7 @@ struct Smt2Backend : public Backend {
 
 		for (auto module : sorted_modules)
 			for (auto cell : module->cells())
-				if (cell->type.in(ID($allconst), ID($allseq)))
+				if (cell->type.in(TW($allconst), TW($allseq)))
 					goto found_forall;
 		if (0) {
 	found_forall:
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index b9133eeff..629a13036 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -227,7 +227,7 @@ struct SmvWorker
 		{
 			// FIXME: $slice, $concat, $mem
 
-			if (cell->type.in(ID($assert)))
+			if (cell->type.in(TW($assert)))
 			{
 				SigSpec sig_a = cell->getPort(TW::A);
 				SigSpec sig_en = cell->getPort(TW::EN);
@@ -237,7 +237,7 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
+			if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
 			{
 				SigSpec sig_a = cell->getPort(TW::A);
 				SigSpec sig_b = cell->getPort(TW::B);
@@ -256,10 +256,10 @@ struct SmvWorker
 
 				bool signed_a = cell->getParam(ID::A_SIGNED).as_bool();
 				bool signed_b = cell->getParam(ID::B_SIGNED).as_bool();
-				string op = cell->type.in(ID($shl), ID($sshl)) ? "<<" : ">>";
+				string op = cell->type.in(TW($shl), TW($sshl)) ? "<<" : ">>";
 				string expr, expr_a;
 
-				if (cell->type == ID($sshr) && signed_a)
+				if (cell->type == TW($sshr) && signed_a)
 				{
 					expr_a = rvalue_s(sig_a, width);
 					expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a, op, rvalue(sig_b.extract(0, shift_b_width)), width_y);
@@ -268,7 +268,7 @@ struct SmvWorker
 								rvalue(sig_b.extract(shift_b_width, GetSize(sig_b) - shift_b_width)), GetSize(sig_b) - shift_b_width,
 								rvalue(sig_a[GetSize(sig_a)-1]), width_y, width_y, expr.c_str());
 				}
-				else if (cell->type.in(ID($shift), ID($shiftx)) && signed_b)
+				else if (cell->type.in(TW($shift), TW($shiftx)) && signed_b)
 				{
 					expr_a = rvalue_u(sig_a, width);
 
@@ -292,7 +292,7 @@ struct SmvWorker
 				}
 				else
 				{
-					if (cell->type.in(ID($shift), ID($shiftx)) || !signed_a)
+					if (cell->type.in(TW($shift), TW($shiftx)) || !signed_a)
 						expr_a = rvalue_u(sig_a, width);
 					else
 						expr_a = stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a, width_ay), width);
@@ -308,14 +308,14 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($not), ID($pos), ID($neg)))
+			if (cell->type.in(TW($not), TW($pos), TW($neg)))
 			{
 				int width = GetSize(cell->getPort(TW::Y));
 				string expr_a, op;
 
-				if (cell->type == ID($not))  op = "!";
-				if (cell->type == ID($pos))  op = "";
-				if (cell->type == ID($neg))  op = "-";
+				if (cell->type == TW($not))  op = "!";
+				if (cell->type == TW($pos))  op = "";
+				if (cell->type == TW($neg))  op = "-";
 
 				if (cell->getParam(ID::A_SIGNED).as_bool())
 				{
@@ -331,18 +331,18 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor)))
+			if (cell->type.in(TW($add), TW($sub), TW($mul), TW($and), TW($or), TW($xor), TW($xnor)))
 			{
 				int width = GetSize(cell->getPort(TW::Y));
 				string expr_a, expr_b, op;
 
-				if (cell->type == ID($add))  op = "+";
-				if (cell->type == ID($sub))  op = "-";
-				if (cell->type == ID($mul))  op = "*";
-				if (cell->type == ID($and))  op = "&";
-				if (cell->type == ID($or))   op = "|";
-				if (cell->type == ID($xor))  op = "xor";
-				if (cell->type == ID($xnor)) op = "xnor";
+				if (cell->type == TW($add))  op = "+";
+				if (cell->type == TW($sub))  op = "-";
+				if (cell->type == TW($mul))  op = "*";
+				if (cell->type == TW($and))  op = "&";
+				if (cell->type == TW($or))   op = "|";
+				if (cell->type == TW($xor))  op = "xor";
+				if (cell->type == TW($xnor)) op = "xnor";
 
 				if (cell->getParam(ID::A_SIGNED).as_bool())
 				{
@@ -359,15 +359,15 @@ struct SmvWorker
 			}
 
 			// SMV has a "mod" operator, but its semantics don't seem to be well-defined - to be safe, don't generate it at all
-			if (cell->type.in(ID($div)/*, ID($mod), ID($modfloor)*/))
+			if (cell->type.in(TW($div)/*, TW($mod), TW($modfloor)*/))
 			{
 				int width_y = GetSize(cell->getPort(TW::Y));
 				int width = max(width_y, GetSize(cell->getPort(TW::A)));
 				width = max(width, GetSize(cell->getPort(TW::B)));
 				string expr_a, expr_b, op;
 
-				if (cell->type == ID($div))  op = "/";
-				//if (cell->type == ID($mod))  op = "mod";
+				if (cell->type == TW($div))  op = "/";
+				//if (cell->type == TW($mod))  op = "mod";
 
 				if (cell->getParam(ID::A_SIGNED).as_bool())
 				{
@@ -383,19 +383,19 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt)))
+			if (cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex), TW($lt), TW($le), TW($ge), TW($gt)))
 			{
 				int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
 				string expr_a, expr_b, op;
 
-				if (cell->type == ID($eq))  op = "=";
-				if (cell->type == ID($ne))  op = "!=";
-				if (cell->type == ID($eqx)) op = "=";
-				if (cell->type == ID($nex)) op = "!=";
-				if (cell->type == ID($lt))  op = "<";
-				if (cell->type == ID($le))  op = "<=";
-				if (cell->type == ID($ge))  op = ">=";
-				if (cell->type == ID($gt))  op = ">";
+				if (cell->type == TW($eq))  op = "=";
+				if (cell->type == TW($ne))  op = "!=";
+				if (cell->type == TW($eqx)) op = "=";
+				if (cell->type == TW($nex)) op = "!=";
+				if (cell->type == TW($lt))  op = "<";
+				if (cell->type == TW($le))  op = "<=";
+				if (cell->type == TW($ge))  op = ">=";
+				if (cell->type == TW($gt))  op = ">";
 
 				if (cell->getParam(ID::A_SIGNED).as_bool())
 				{
@@ -414,7 +414,7 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)))
+			if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool)))
 			{
 				int width_a = GetSize(cell->getPort(TW::A));
 				int width_y = GetSize(cell->getPort(TW::Y));
@@ -422,15 +422,15 @@ struct SmvWorker
 				const char *expr_y = lvalue(cell->getPort(TW::Y));
 				string expr;
 
-				if (cell->type == ID($reduce_and))  expr = stringf("%s = !0ub%d_0", expr_a, width_a);
-				if (cell->type == ID($reduce_or))   expr = stringf("%s != 0ub%d_0", expr_a, width_a);
-				if (cell->type == ID($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
+				if (cell->type == TW($reduce_and))  expr = stringf("%s = !0ub%d_0", expr_a, width_a);
+				if (cell->type == TW($reduce_or))   expr = stringf("%s != 0ub%d_0", expr_a, width_a);
+				if (cell->type == TW($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
 
 				definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr, width_y));
 				continue;
 			}
 
-			if (cell->type.in(ID($reduce_xor), ID($reduce_xnor)))
+			if (cell->type.in(TW($reduce_xor), TW($reduce_xnor)))
 			{
 				int width_y = GetSize(cell->getPort(TW::Y));
 				const char *expr_y = lvalue(cell->getPort(TW::Y));
@@ -442,14 +442,14 @@ struct SmvWorker
 					expr += rvalue(bit);
 				}
 
-				if (cell->type == ID($reduce_xnor))
+				if (cell->type == TW($reduce_xnor))
 					expr = "!(" + expr + ")";
 
 				definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr, width_y));
 				continue;
 			}
 
-			if (cell->type.in(ID($logic_and), ID($logic_or)))
+			if (cell->type.in(TW($logic_and), TW($logic_or)))
 			{
 				int width_a = GetSize(cell->getPort(TW::A));
 				int width_b = GetSize(cell->getPort(TW::B));
@@ -460,14 +460,14 @@ struct SmvWorker
 				const char *expr_y = lvalue(cell->getPort(TW::Y));
 
 				string expr;
-				if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b;
-				if (cell->type == ID($logic_or))  expr = expr_a + " | " + expr_b;
+				if (cell->type == TW($logic_and)) expr = expr_a + " & " + expr_b;
+				if (cell->type == TW($logic_or))  expr = expr_a + " | " + expr_b;
 
 				definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr, width_y));
 				continue;
 			}
 
-			if (cell->type.in(ID($logic_not)))
+			if (cell->type.in(TW($logic_not)))
 			{
 				int width_a = GetSize(cell->getPort(TW::A));
 				int width_y = GetSize(cell->getPort(TW::Y));
@@ -479,7 +479,7 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($mux), ID($pmux)))
+			if (cell->type.in(TW($mux), TW($pmux)))
 			{
 				int width = GetSize(cell->getPort(TW::Y));
 				SigSpec sig_a = cell->getPort(TW::A);
@@ -495,34 +495,34 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type == ID($dff))
+			if (cell->type == TW($dff))
 			{
 				vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(TW::Q)), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q))));
 				assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(TW::Q)), rvalue(cell->getPort(TW::D))));
 				continue;
 			}
 
-			if (cell->type.in(ID($_BUF_), ID($_NOT_)))
+			if (cell->type.in(TW($_BUF_), TW($_NOT_)))
 			{
-				string op = cell->type == ID($_NOT_) ? "!" : "";
+				string op = cell->type == TW($_NOT_) ? "!" : "";
 				definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)), op, rvalue(cell->getPort(TW::A))));
 				continue;
 			}
 
-			if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
+			if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
 			{
 				string op;
 
-				if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_))) op = "&";
-				if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_))) op = "|";
-				if (cell->type.in(ID($_XOR_)))  op = "xor";
-				if (cell->type.in(ID($_XNOR_)))  op = "xnor";
+				if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_ANDNOT_))) op = "&";
+				if (cell->type.in(TW($_OR_), TW($_NOR_), TW($_ORNOT_))) op = "|";
+				if (cell->type.in(TW($_XOR_)))  op = "xor";
+				if (cell->type.in(TW($_XNOR_)))  op = "xnor";
 
-				if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+				if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 					definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(TW::Y)),
 							rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
 				else
-				if (cell->type.in(ID($_NAND_), ID($_NOR_)))
+				if (cell->type.in(TW($_NAND_), TW($_NOR_)))
 					definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(TW::Y)),
 							rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
 				else
@@ -531,61 +531,61 @@ struct SmvWorker
 				continue;
 			}
 
-			if (cell->type == ID($_MUX_))
+			if (cell->type == TW($_MUX_))
 			{
 				definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(TW::Y)),
 						rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
 				continue;
 			}
 
-			if (cell->type == ID($_NMUX_))
+			if (cell->type == TW($_NMUX_))
 			{
 				definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(TW::Y)),
 						rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
 				continue;
 			}
 
-			if (cell->type == ID($_AOI3_))
+			if (cell->type == TW($_AOI3_))
 			{
 				definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(TW::Y)),
 						rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
 				continue;
 			}
 
-			if (cell->type == ID($_OAI3_))
+			if (cell->type == TW($_OAI3_))
 			{
 				definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(TW::Y)),
 						rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
 				continue;
 			}
 
-			if (cell->type == ID($_AOI4_))
+			if (cell->type == TW($_AOI4_))
 			{
 				definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(TW::Y)),
 						rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
 				continue;
 			}
 
-			if (cell->type == ID($_OAI4_))
+			if (cell->type == TW($_OAI4_))
 			{
 				definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(TW::Y)),
 						rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
 				continue;
 			}
 
-			if (cell->type == ID($scopeinfo))
+			if (cell->type == TW($scopeinfo))
 				continue;
 
 			if (cell->type[0] == '$') {
-				if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
+				if (cell->type.in(TW($dffe), TW($sdff), TW($sdffe), TW($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
 					log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smv`.\n",
 							cell->type.unescape(), module, cell);
 				}
-				if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
+				if (cell->type.in(TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($dffsr), TW($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
 					log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smv`.\n",
 							cell->type.unescape(), module, cell);
 				}
-				if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
+				if (cell->type.in(TW($sr), TW($dlatch), TW($adlatch), TW($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
 					log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_smv`.\n",
 							cell->type.unescape(), module, cell);
 				}
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 340c72081..daf39bd73 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
 static string spice_id2str(IdString id)
 {
 	static const char *escape_chars = "$\\[]()<>=";
-	string s = id.unescape();
+	string s = design->twines.unescaped_str(id);
 
 	for (auto &ch : s)
 		if (strchr(escape_chars, ch) != nullptr) ch = '_';
@@ -72,7 +72,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 
 	for (auto cell : module->cells())
 	{
-		if (cell->type == ID($scopeinfo))
+		if (cell->type == TW($scopeinfo))
 			continue;
 
 		f << stringf("X%d", cell_counter++);
diff --git a/backends/table/table.cc b/backends/table/table.cc
index 546f2488a..74b18f2cf 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -78,7 +78,7 @@ struct TableBackend : public Backend {
 					continue;
 
 				*f << design->twines.str(module->meta_->name) << "\t";
-				*f << wire->name.unescape() << "\t";
+				*f << design->twines.unescaped_str(wire->name) << "\t";
 				*f << "-" << "\t";
 				*f << "-" << "\t";
 
@@ -99,7 +99,7 @@ struct TableBackend : public Backend {
 			{
 				*f << design->twines.str(module->meta_->name) << "\t";
 				*f << cell->module->design->twines.str(cell->meta_->name) << "\t";
-				*f << cell->type.unescape() << "\t";
+				*f << cell->type.unescaped() << "\t";
 				*f << design->twines.str(conn.first) << "\t";
 
 				if (cell->input(conn.first) && cell->output(conn.first))
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6f3e199c7..d514320fc 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -992,7 +992,7 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b
 
 std::string cellname(RTLIL::Cell *cell)
 {
-	if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(ID($ff), ID($_FF_)))
+	if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(TW($ff), TW($_FF_)))
 	{
 		RTLIL::SigSpec sig = cell->getPort(TW::Q);
 		if (GetSize(sig) != 1 || sig.is_fully_const())
@@ -1109,7 +1109,7 @@ void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell
 
 bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 {
-	if (cell->type == ID($_NOT_)) {
+	if (cell->type == TW($_NOT_)) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
 		f << stringf(" = ");
@@ -1120,8 +1120,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($_BUF_), ID($buf))) {
-		if (cell->type == ID($buf) && cell->getPort(TW::A).has_const(State::Sz)) {
+	if (cell->type.in(TW($_BUF_), TW($buf))) {
+		if (cell->type == TW($buf) && cell->getPort(TW::A).has_const(State::Sz)) {
 			RTLIL::SigSpec a = cell->getPort(TW::A);
 			RTLIL::SigSpec y = cell->getPort(TW::Y);
 			a.extend_u0(GetSize(y));
@@ -1156,32 +1156,32 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
+	if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_))) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
 		f << stringf(" = ");
-		if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_)))
+		if (cell->type.in(TW($_NAND_), TW($_NOR_), TW($_XNOR_)))
 			f << stringf("~(");
 		dump_cell_expr_port(f, cell, "A", false);
 		f << stringf(" ");
-		if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_)))
+		if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_ANDNOT_)))
 			f << stringf("&");
-		if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
+		if (cell->type.in(TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
 			f << stringf("|");
-		if (cell->type.in(ID($_XOR_), ID($_XNOR_)))
+		if (cell->type.in(TW($_XOR_), TW($_XNOR_)))
 			f << stringf("^");
 		dump_attributes(f, "", cell->attributes, " ");
 		f << stringf(" ");
-		if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+		if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 			f << stringf("~(");
 		dump_cell_expr_port(f, cell, "B", false);
-		if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
+		if (cell->type.in(TW($_NAND_), TW($_NOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
 			f << stringf(")");
 		f << stringf(";\n");
 		return true;
 	}
 
-	if (cell->type == ID($_MUX_)) {
+	if (cell->type == TW($_MUX_)) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
 		f << stringf(" = ");
@@ -1195,7 +1195,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($_NMUX_)) {
+	if (cell->type == TW($_NMUX_)) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
 		f << stringf(" = !(");
@@ -1209,14 +1209,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) {
+	if (cell->type.in(TW($_AOI3_), TW($_OAI3_))) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
 		f << stringf(" = ~((");
 		dump_cell_expr_port(f, cell, "A", false);
-		f << (cell->type == ID($_AOI3_) ? " & " : " | ");
+		f << (cell->type == TW($_AOI3_) ? " & " : " | ");
 		dump_cell_expr_port(f, cell, "B", false);
-		f << (cell->type == ID($_AOI3_) ? ") |" : ") &");
+		f << (cell->type == TW($_AOI3_) ? ") |" : ") &");
 		dump_attributes(f, "", cell->attributes, " ");
 		f << stringf(" ");
 		dump_cell_expr_port(f, cell, "C", false);
@@ -1224,18 +1224,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) {
+	if (cell->type.in(TW($_AOI4_), TW($_OAI4_))) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
 		f << stringf(" = ~((");
 		dump_cell_expr_port(f, cell, "A", false);
-		f << (cell->type == ID($_AOI4_) ? " & " : " | ");
+		f << (cell->type == TW($_AOI4_) ? " & " : " | ");
 		dump_cell_expr_port(f, cell, "B", false);
-		f << (cell->type == ID($_AOI4_) ? ") |" : ") &");
+		f << (cell->type == TW($_AOI4_) ? ") |" : ") &");
 		dump_attributes(f, "", cell->attributes, " ");
 		f << stringf(" (");
 		dump_cell_expr_port(f, cell, "C", false);
-		f << (cell->type == ID($_AOI4_) ? " & " : " | ");
+		f << (cell->type == TW($_AOI4_) ? " & " : " | ");
 		dump_cell_expr_port(f, cell, "D", false);
 		f << stringf("));\n");
 		return true;
@@ -1246,50 +1246,50 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 #define HANDLE_BINOP(_type, _operator) \
 	if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator); return true; }
 
-	HANDLE_UNIOP(ID($not), "~")
-	HANDLE_UNIOP(ID($pos), "+")
-	HANDLE_UNIOP(ID($neg), "-")
+	HANDLE_UNIOP(TW($not), "~")
+	HANDLE_UNIOP(TW($pos), "+")
+	HANDLE_UNIOP(TW($neg), "-")
 
-	HANDLE_BINOP(ID($and),  "&")
-	HANDLE_BINOP(ID($or),   "|")
-	HANDLE_BINOP(ID($xor),  "^")
-	HANDLE_BINOP(ID($xnor), "~^")
+	HANDLE_BINOP(TW($and),  "&")
+	HANDLE_BINOP(TW($or),   "|")
+	HANDLE_BINOP(TW($xor),  "^")
+	HANDLE_BINOP(TW($xnor), "~^")
 
-	HANDLE_UNIOP(ID($reduce_and),  "&")
-	HANDLE_UNIOP(ID($reduce_or),   "|")
-	HANDLE_UNIOP(ID($reduce_xor),  "^")
-	HANDLE_UNIOP(ID($reduce_xnor), "~^")
-	HANDLE_UNIOP(ID($reduce_bool), "|")
+	HANDLE_UNIOP(TW($reduce_and),  "&")
+	HANDLE_UNIOP(TW($reduce_or),   "|")
+	HANDLE_UNIOP(TW($reduce_xor),  "^")
+	HANDLE_UNIOP(TW($reduce_xnor), "~^")
+	HANDLE_UNIOP(TW($reduce_bool), "|")
 
-	HANDLE_BINOP(ID($shl),  "<<")
-	HANDLE_BINOP(ID($shr),  ">>")
-	HANDLE_BINOP(ID($sshl), "<<<")
-	HANDLE_BINOP(ID($sshr), ">>>")
+	HANDLE_BINOP(TW($shl),  "<<")
+	HANDLE_BINOP(TW($shr),  ">>")
+	HANDLE_BINOP(TW($sshl), "<<<")
+	HANDLE_BINOP(TW($sshr), ">>>")
 
-	HANDLE_BINOP(ID($lt),  "<")
-	HANDLE_BINOP(ID($le),  "<=")
-	HANDLE_BINOP(ID($eq),  "==")
-	HANDLE_BINOP(ID($ne),  "!=")
-	HANDLE_BINOP(ID($eqx), "===")
-	HANDLE_BINOP(ID($nex), "!==")
-	HANDLE_BINOP(ID($ge),  ">=")
-	HANDLE_BINOP(ID($gt),  ">")
+	HANDLE_BINOP(TW($lt),  "<")
+	HANDLE_BINOP(TW($le),  "<=")
+	HANDLE_BINOP(TW($eq),  "==")
+	HANDLE_BINOP(TW($ne),  "!=")
+	HANDLE_BINOP(TW($eqx), "===")
+	HANDLE_BINOP(TW($nex), "!==")
+	HANDLE_BINOP(TW($ge),  ">=")
+	HANDLE_BINOP(TW($gt),  ">")
 
-	HANDLE_BINOP(ID($add), "+")
-	HANDLE_BINOP(ID($sub), "-")
-	HANDLE_BINOP(ID($mul), "*")
-	HANDLE_BINOP(ID($div), "/")
-	HANDLE_BINOP(ID($mod), "%")
-	HANDLE_BINOP(ID($pow), "**")
+	HANDLE_BINOP(TW($add), "+")
+	HANDLE_BINOP(TW($sub), "-")
+	HANDLE_BINOP(TW($mul), "*")
+	HANDLE_BINOP(TW($div), "/")
+	HANDLE_BINOP(TW($mod), "%")
+	HANDLE_BINOP(TW($pow), "**")
 
-	HANDLE_UNIOP(ID($logic_not), "!")
-	HANDLE_BINOP(ID($logic_and), "&&")
-	HANDLE_BINOP(ID($logic_or),  "||")
+	HANDLE_UNIOP(TW($logic_not), "!")
+	HANDLE_BINOP(TW($logic_and), "&&")
+	HANDLE_BINOP(TW($logic_or),  "||")
 
 #undef HANDLE_UNIOP
 #undef HANDLE_BINOP
 
-	if (cell->type == ID($divfloor))
+	if (cell->type == TW($divfloor))
 	{
 		// wire [MAXLEN+1:0] _0_, _1_, _2_;
 		// assign _0_ = $signed(A);
@@ -1344,7 +1344,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		}
 	}
 
-	if (cell->type == ID($modfloor))
+	if (cell->type == TW($modfloor))
 	{
 		// wire truncated = $signed(A) % $signed(B);
 		// assign Y = (A[-1] == B[-1]) || truncated == 0 ? $signed(truncated) : $signed(B) + $signed(truncated);
@@ -1378,7 +1378,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		}
 	}
 
-	if (cell->type == ID($shift))
+	if (cell->type == TW($shift))
 	{
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
@@ -1405,7 +1405,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($shiftx))
+	if (cell->type == TW($shiftx))
 	{
 		std::string temp_id = next_auto_id();
 		f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id);
@@ -1425,7 +1425,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($mux))
+	if (cell->type == TW($mux))
 	{
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
@@ -1440,7 +1440,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($pmux))
+	if (cell->type == TW($pmux))
 	{
 		int width = cell->parameters[ID::WIDTH].as_int();
 		int s_width = cell->getPort(TW::S).size();
@@ -1500,7 +1500,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($tribuf))
+	if (cell->type == TW($tribuf))
 	{
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
@@ -1512,7 +1512,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($slice))
+	if (cell->type == TW($slice))
 	{
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
@@ -1522,7 +1522,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($concat))
+	if (cell->type == TW($concat))
 	{
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
@@ -1534,7 +1534,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($lut))
+	if (cell->type == TW($lut))
 	{
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, cell->getPort(TW::Y));
@@ -1547,10 +1547,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+	if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 		return true;
 
-	if (cell->type == ID($connect))
+	if (cell->type == TW($connect))
 	{
 		int width = cell->getParam(ID::WIDTH).as_int() ;
 		if (width == 1) {
@@ -1794,7 +1794,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($assert), ID($assume), ID($cover)))
+	if (cell->type.in(TW($assert), TW($assume), TW($cover)))
 	{
 		f << stringf("%s" "always%s if (", indent, systemverilog ? "_comb" : " @*");
 		dump_sigspec(f, cell->getPort(TW::EN));
@@ -1804,7 +1804,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($specify2), ID($specify3)))
+	if (cell->type.in(TW($specify2), TW($specify3)))
 	{
 		f << stringf("%s" "specify\n%s  ", indent, indent);
 
@@ -1816,7 +1816,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		}
 
 		f << "(";
-		if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
+		if (cell->type == TW($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
 			f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge ");
 
 		dump_sigspec(f, cell->getPort(TW::SRC));
@@ -1826,7 +1826,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			f << (cell->getParam(ID::SRC_DST_POL).as_bool() ? "+": "-");
 		f << (cell->getParam(ID::FULL).as_bool() ? "*> ": "=> ");
 
-		if (cell->type == ID($specify3)) {
+		if (cell->type == TW($specify3)) {
 			f << "(";
 			dump_sigspec(f, cell->getPort(TW::DST));
 			f << " ";
@@ -1862,7 +1862,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($specrule))
+	if (cell->type == TW($specrule))
 	{
 		f << stringf("%s" "specify\n%s  ", indent, indent);
 
@@ -1898,7 +1898,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << ": ";
 		dump_const(f, cell->getParam(ID::T_LIMIT_MAX));
 
-		if (spec_type.in(ID($setuphold), ID($recrem), ID($fullskew))) {
+		if (spec_type.in(TW($setuphold), TW($recrem), TW($fullskew))) {
 			f << ", ";
 			dump_const(f, cell->getParam(ID::T_LIMIT2_MIN));
 			f << ": ";
@@ -1914,7 +1914,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($print))
+	if (cell->type == TW($print))
 	{
 		// Sync $print cells are accumulated and handled in dump_module.
 		if (cell->getParam(ID::TRG_ENABLE).as_bool())
@@ -1930,7 +1930,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($check))
+	if (cell->type == TW($check))
 	{
 		// Sync $check cells are accumulated and handled in dump_module.
 		if (cell->getParam(ID::TRG_ENABLE).as_bool())
@@ -1974,7 +1974,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	// cells that exist only to hold metadata. If in the future that metadata
 	// should be exposed as part of the write_verilog output it should be
 	// opt-in and/or represented as something else than a $scopeinfo cell.
-	if (cell->type == ID($scopeinfo))
+	if (cell->type == TW($scopeinfo))
 		return;
 
 	// Handled by dump_memory
@@ -2052,7 +2052,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		}
 	}
 
-	if (siminit && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(ID($ff), ID($_FF_))) {
+	if (siminit && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(TW($ff), TW($_FF_))) {
 		std::stringstream ss;
 		dump_reg_init(ss, cell->getPort(TW::Q));
 		if (!ss.str().empty()) {
@@ -2089,9 +2089,9 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec
 		dump_sigspec(f, cell->getPort(TW::EN));
 		f << stringf(") begin\n");
 
-		if (cell->type == ID($print)) {
+		if (cell->type == TW($print)) {
 			dump_cell_expr_print(f, indent + "    ", cell);
-		} else if (cell->type == ID($check)) {
+		} else if (cell->type == TW($check)) {
 			std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
 			if (flavor == "assert" || flavor == "assume") {
 				Fmt fmt;
@@ -2408,12 +2408,12 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($print), ID($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
+			if (cell->type.in(TW($print), TW($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
 				sync_effect_cells[make_pair(cell->getPort(TW::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell);
 				continue;
 			}
 
-			if (!cell->is_builtin_ff() || !cell->hasPort(TW::Q) || cell->type.in(ID($ff), ID($_FF_)))
+			if (!cell->is_builtin_ff() || !cell->hasPort(TW::Q) || cell->type.in(TW($ff), TW($_FF_)))
 				continue;
 
 			RTLIL::SigSpec sig = cell->getPort(TW::Q);
diff --git a/docs/source/code_examples/functional/dummy.cc b/docs/source/code_examples/functional/dummy.cc
index a339bc275..3aaa5825a 100644
--- a/docs/source/code_examples/functional/dummy.cc
+++ b/docs/source/code_examples/functional/dummy.cc
@@ -24,19 +24,19 @@ struct FunctionalDummyBackend : public Backend {
 
 			// write node functions
 			for (auto node : ir)
-				*f << "  assign " << node.name().unescape()
+				*f << "  assign " << design->twines.unescaped_str(node.name())
 				   << " = " << node.to_string() << "\n";
 			*f << "\n";
 
 			// write outputs and next state
 			for (auto output : ir.outputs())
-				*f << " " << output->kind.unescape()
-				   << " " << output->name.unescape()
-				   << " = " << output->value().name().unescape() << "\n";
+				*f << " " << design->twines.unescaped_str(output->kind)
+				   << " " << design->twines.unescaped_str(output->name)
+				   << " = " << design->twines.unescaped_str(output->value().name()) << "\n";
 			for (auto state : ir.states())
-				*f << " " << state->kind.unescape()
-				   << " " << state->name.unescape()
-				   << " = " << state->next_value().name().unescape() << "\n";
+				*f << " " << design->twines.unescaped_str(state->kind)
+				   << " " << design->twines.unescaped_str(state->name)
+				   << " = " << design->twines.unescaped_str(state->next_value().name()) << "\n";
 		}
 	}
 } FunctionalDummyBackend;
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index fe49814d5..c9dddd649 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -76,10 +76,10 @@ struct ConstEvalAig
 	ConstEvalAig(RTLIL::Module *module) : module(module)
 	{
 		for (auto &it : module->cells_) {
-			if (!yosys_celltypes.cell_known(it.second->type))
+			if (!yosys_celltypes.cell_known(it.second->type.ref()))
 				continue;
 			for (auto &it2 : it.second->connections())
-				if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
+				if (yosys_celltypes.cell_output(it.second->type.ref(), it2.first)) {
 					auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
 					log_assert(r.second);
 				}
@@ -138,7 +138,7 @@ struct ConstEvalAig
 		if (!inputs.count(sig_a))
 			compute_deps(sig_a, inputs);
 
-		if (cell->type == ID($_AND_)) {
+		if (cell->type == TW($_AND_)) {
 			RTLIL::SigSpec sig_b = cell->getPort(TW::B);
 			sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
 												   // that may occur does so here, and
@@ -148,7 +148,7 @@ struct ConstEvalAig
 			if (!inputs.count(sig_b))
 				compute_deps(sig_b, inputs);
 		}
-		else if (cell->type == ID($_NOT_)) {
+		else if (cell->type == TW($_NOT_)) {
 		}
 		else log_abort();
 	}
@@ -164,11 +164,11 @@ struct ConstEvalAig
 			return false;
 
 		RTLIL::State eval_ret = RTLIL::Sx;
-		if (cell->type == ID($_NOT_)) {
+		if (cell->type == TW($_NOT_)) {
 			if (sig_a == State::S0) eval_ret = State::S1;
 			else if (sig_a == State::S1) eval_ret = State::S0;
 		}
-		else if (cell->type == ID($_AND_)) {
+		else if (cell->type == TW($_AND_)) {
 			if (sig_a == State::S0) {
 				eval_ret = State::S0;
 				goto eval_end;
@@ -504,7 +504,8 @@ void AigerReader::parse_xaiger()
 				uint32_t boxUniqueId = parse_xaiger_literal(f);
 				log_assert(boxUniqueId > 0);
 				uint32_t oldBoxNum = parse_xaiger_literal(f);
-				RTLIL::Cell* cell = module->addCell(Twine{stringf("$box%u", oldBoxNum)}, ID(stringf("$__boxid%u", boxUniqueId)));
+				TwineRef _type = module->design->twines.add(Twine{stringf("$__boxid%u", boxUniqueId)});
+				RTLIL::Cell* cell = module->addCell(Twine{stringf("$box%u", oldBoxNum)}, _type);
 				cell->setPort(TW::I, SigSpec(State::S0, boxInputs));
 				cell->setPort(TW::O, SigSpec(State::S0, boxOutputs));
 				cell->attributes[ID::abc9_box_seq] = oldBoxNum;
@@ -836,7 +837,7 @@ void AigerReader::post_process()
 						wire->port_input = false;
 						module->connect(wire, existing);
 					}
-					log_debug(" -> %s\n", escaped_s.unescape());
+					log_debug(" -> %s\n", design->twines.unescaped_str(escaped_s));
 				}
 				else {
 					RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
@@ -847,7 +848,7 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire->port_input = false;
 					}
-					log_debug(" -> %s\n", indexed_name.unescape());
+					log_debug(" -> %s\n", design->twines.unescaped_str(indexed_name));
 				}
 
 				if (wideports && !existing) {
@@ -883,7 +884,7 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire = existing;
 					}
-					log_debug(" -> %s\n", escaped_s.unescape());
+					log_debug(" -> %s\n", design->twines.unescaped_str(escaped_s));
 				}
 				else {
 					RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
@@ -895,7 +896,7 @@ void AigerReader::post_process()
 						existing->port_output = true;
 						module->connect(wire, existing);
 					}
-					log_debug(" -> %s\n", indexed_name.unescape());
+					log_debug(" -> %s\n", design->twines.unescaped_str(indexed_name));
 				}
 
 				if (wideports && !existing) {
@@ -913,7 +914,7 @@ void AigerReader::post_process()
 			else if (type == "box") {
 				RTLIL::Cell* cell = module->cell(design->twines.lookup(stringf("$box%d", variable)));
 				if (!cell)
-					log_debug("Box %d (%s) no longer exists.\n", variable, escaped_s.unescape());
+					log_debug("Box %d (%s) no longer exists.\n", variable, design->twines.unescaped_str(escaped_s));
 				else
 					module->rename(cell, design->twines.add(Twine{escaped_s.str()}));
 			}
@@ -977,7 +978,7 @@ void AigerReader::post_process()
 	design->add(module);
 
 	for (auto cell : module->cells().to_vector()) {
-		if (cell->type != ID($lut)) continue;
+		if (cell->type != TW($lut)) continue;
 		auto y_port = cell->getPort(TW::Y).as_bit();
 		if (y_port.wire->width == 1)
 			module->rename(cell, design->twines.add(Twine{stringf("$lut%s", design->twines.str(y_port.wire->meta_->name).c_str())}));
diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc
index 8499b711f..7decbe916 100644
--- a/frontends/aiger2/xaiger.cc
+++ b/frontends/aiger2/xaiger.cc
@@ -28,7 +28,7 @@ uint32_t read_be32(std::istream &f) {
 		((uint32_t) f.get() << 8) | (uint32_t) f.get();
 }
 
-IdString read_idstring(std::istream &f)
+std::string read_idstring(std::istream &f)
 {
 	std::string str;
 	std::getline(f, str, '\0');
@@ -61,14 +61,15 @@ struct Xaiger2Frontend : public Frontend {
 
 	void read_sc_mapping(std::istream *&f, std::string filename, std::vector<std::string> args, Design *design)
 	{
-		IdString module_name;
+		std::optional<TwineRef> module_name;
+		TwineSearch search(&design->twines);
 		std::string map_filename;
 
 		size_t argidx;
 		for (argidx = 2; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
 			if (arg == "-module_name" && argidx + 1 < args.size()) {
-				module_name = RTLIL::escape_id(args[++argidx]);
+				module_name = search.find(RTLIL::escape_id(args[++argidx]));
 				continue;
 			}
 			if (arg == "-map2" && argidx + 1 < args.size()) {
@@ -81,12 +82,12 @@ struct Xaiger2Frontend : public Frontend {
 
 		if (map_filename.empty())
 			log_error("A '-map2' argument is required\n");
-		if (module_name.empty())
+		if (!module_name)
 			log_error("A '-module_name' argument is required\n");
 
-		Module *module = design->module(module_name);
+		Module *module = design->module(*module_name);
 		if (!module)
-			log_error("Module '%s' not found\n", module_name.unescape());
+			log_error("Module '%s' not found\n", design->twines.unescaped_str(*module_name));
 
 		std::ifstream map_file;
 		map_file.open(map_filename);
@@ -122,7 +123,6 @@ struct Xaiger2Frontend : public Frontend {
 		bits[1] = RTLIL::S1;
 
 		std::string type;
-		TwineSearch search(&design->twines);
 		while (map_file >> type) {
 			if (type == "pi") {
 				int pi_idx;
@@ -159,7 +159,7 @@ struct Xaiger2Frontend : public Frontend {
 				}
 
 				if (!def)
-					log_error("Bad map file: no module found for box type '%s'\n", box->type.unescape());
+					log_error("Bad map file: no module found for box type '%s'\n", design->twines.unescaped_str(box->type_impl));
 
 				if (box_seq >= (int) boxes.size()) {
 					boxes.resize(box_seq + 1);
@@ -265,22 +265,22 @@ struct Xaiger2Frontend : public Frontend {
 
 				struct MappingCell {
 					TwineRef type;
-					RTLIL::IdString out;
-					std::vector<TwineRef ins;
+					TwineRef out;
+					std::vector<TwineRef> ins;
 				};
 				std::vector<MappingCell> cells;
 				cells.resize(no_cells);
 
 				for (unsigned i = 0; i < no_cells; ++i) {
 					auto &cell = cells[i];
-					cell.type = read_idstring(*f);
-					cell.out = read_idstring(*f);
+					cell.type = design->twines.add(Twine{read_idstring(*f)});
+					cell.out = design->twines.add(Twine{read_idstring(*f)});
 					uint32_t nins = read_be32(*f);
 					for (uint32_t j = 0; j < nins; j++)
-						cell.ins.push_back(read_idstring(*f));
-					log_debug("M: Cell %s (out %s, ins", cell.type.unescape(), cell.out.unescape());
+						cell.ins.push_back(design->twines.add(Twine{read_idstring(*f)}));
+					log_debug("M: Cell %s (out %s, ins", design->twines.str(cell.type).c_str(), design->twines.unescaped_str(cell.out));
 					for (auto in : cell.ins)
-						log_debug(" %s", in.unescape());
+						log_debug(" %s", design->twines.str(in).c_str());
 					log_debug(")\n");
 				}
 
@@ -294,13 +294,13 @@ struct Xaiger2Frontend : public Frontend {
 					auto &cell = cells[cell_id];
 					Cell *instance = module->addCell(module->uniquify(design->twines.add(Twine{stringf("$sc%d", out_lit)})), cell.type);
 					auto out_w = module->addWire(module->uniquify(design->twines.add(Twine{stringf("$lit%d", out_lit)})));
-					instance->setPort(design->twines.add(Twine{cell.out.str()}), out_w);
+					instance->setPort(cell.out, out_w);
 					bits[out_lit] = out_w;
 					for (auto in : cell.ins) {
 						uint32_t in_lit = read_be32(*f);
 						log_assert(out_lit < bits.size());
 						log_assert(bits[in_lit] != RTLIL::Sm);
-						instance->setPort(design->twines.add(Twine{in.str()}), bits[in_lit]);
+						instance->setPort(in, bits[in_lit]);
 					}
 				}
 			} else if (c == '\n') {
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index c5488fdb4..7d93ad5b3 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1573,7 +1573,7 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
 	for (auto w : intfmodule->wires()){
 		auto loc = module_ast->location;
 		auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
-		std::string origname = w->name.unescape();
+		std::string origname = intfmodule->design->twines.unescaped_str(w->meta_->name);
 		std::string newname = intfname + "." + origname;
 		wire->str = newname;
 		if (modport != NULL) {
@@ -1637,7 +1637,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
 		RTLIL::Module *intfmodule = intf.second;
 		for (auto w : intfmodule->wires()){
 			auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
-			std::string newname = w->name.unescape();
+			std::string newname = design->twines.unescaped_str(w->meta_->name);
 			newname = intfname + "." + newname;
 			wire->str = newname;
 			new_ast->children.push_back(std::move(wire));
@@ -1698,7 +1698,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
 
 // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
 // This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/)
+TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<TwineRef, RTLIL::Module*> &interfaces, const dict<TwineRef, TwineRef> &modports, bool /*mayfail*/)
 {
 	std::unique_ptr<AstNode> new_ast = NULL;
 	std::string modname = derive_common(design, parameters, &new_ast);
@@ -1731,11 +1731,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 		// Iterate over all interfaces which are ports in this module:
 		for(auto &intf : interfaces) {
 			RTLIL::Module * intfmodule = intf.second;
-			std::string intfname = intf.first.str();
+			std::string intfname = design->twines.str(intf.first);
 			// Check if a modport applies for the interface port:
 			AstNode *modport = NULL;
-			if (modports.count(intfname) > 0) {
-				std::string interface_modport = modports.at(intfname).str();
+			if (modports.count(intf.first) > 0) {
+				std::string interface_modport = design->twines.str(modports.at(intf.first));
 				AstModule *ast_module_of_interface = (AstModule*)intfmodule;
 				AstNode *ast_node_of_interface = ast_module_of_interface->ast.get();
 				modport = find_modport(ast_node_of_interface, interface_modport);
@@ -1751,7 +1751,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 
 		// Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
 		for(auto &intf : interfaces) {
-			TwineRef intf_name = design->twines.lookup(intf.first.str());
+			TwineRef intf_name = design->twines.lookup(design->twines.str(intf.first));
 			if(mod->wire(intf_name) != nullptr) {
 				// Normally, removing wires would be batched together as it's an
 				//   expensive operation, however, in this case doing so would mean
@@ -1764,7 +1764,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 				mod->fixup_ports();
 				// We copy the cell of the interface to the sub-module such that it
 				//   can further be found if it is propagated down to sub-sub-modules etc.
-				RTLIL::Cell *new_subcell = mod->addCell(Twine{intf.first.str()}, RTLIL::IdString(design->twines.str(intf.second->meta_->name)));
+				RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->meta_->name);
 				new_subcell->set_bool_attribute(ID::is_interface);
 			}
 			else {
@@ -1782,11 +1782,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 		log("Found cached RTLIL representation for module `%s'.\n", modname);
 	}
 
-	return modname;
+	return design->twines.add(Twine{modname});
 }
 
 // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
+TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
 {
 	bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
 
@@ -1802,7 +1802,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 		log("Found cached RTLIL representation for module `%s'.\n", modname);
 	}
 
-	return modname;
+	return design->twines.add(Twine{modname});
 }
 
 static std::string serialize_param_value(const RTLIL::Const &val) {
@@ -1979,11 +1979,11 @@ RTLIL::Module *AstModule::clone(RTLIL::Design *dst, bool src_id_verbatim) const
 	return new_mod;
 }
 
-RTLIL::Module *AstModule::clone(RTLIL::Design *dst, RTLIL::IdString target_name, bool src_id_verbatim) const
+RTLIL::Module *AstModule::clone(RTLIL::Design *dst, TwineRef target_name, bool src_id_verbatim) const
 {
 	AstModule *new_mod = new AstModule;
 	new_mod->design = dst;
-	new_mod->meta_->name = dst->twines.add(Twine{target_name.str()});
+	new_mod->meta_->name = target_name;
 	cloneInto(new_mod, src_id_verbatim);
 	dst->add(new_mod);
 
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index b31594442..100376125 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -397,7 +397,7 @@ namespace AST
 		std::unique_ptr<AstNode> ast;
 		bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
 		TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
-		TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<TwineRef, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
+		TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<TwineRef, RTLIL::Module*> &interfaces, const dict<TwineRef, TwineRef> &modports, bool mayfail) override;
 		std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, std::unique_ptr<AstNode>* new_ast_out, bool quiet = false);
 		void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
 		bool reprocess_if_necessary(RTLIL::Design *design) override;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index cdf3ad91a..5018abfe8 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -27,6 +27,7 @@
  */
 
 #include "kernel/log.h"
+#include "kernel/twine.h"
 #include "kernel/utils.h"
 #include "kernel/binding.h"
 #include "libs/sha1/sha1.h"
@@ -43,13 +44,13 @@ using namespace AST;
 using namespace AST_INTERNAL;
 
 // helper function for creating RTLIL code for unary operations
-static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
+static RTLIL::SigSpec uniop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
 {
 	IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
 	RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
 	set_src_attr(cell, that);
 
-	RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width);
+	RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
 	set_src_attr(wire, that);
 	wire->is_signed = that->is_signed;
 
@@ -78,7 +79,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 	}
 
 	IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
-	RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, ID($pos));
+	RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, TW::$pos);
 	set_src_attr(cell, that);
 
 	RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, width);
@@ -102,13 +103,13 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 }
 
 // helper function for creating RTLIL code for binary operations
-static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
+static RTLIL::SigSpec binop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
 	IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
 	RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
 	set_src_attr(cell, that);
 
-	RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width);
+	RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
 	set_src_attr(wire, that);
 	wire->is_signed = that->is_signed;
 
@@ -140,7 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 	std::stringstream sstr;
 	sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++);
 
-	RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($mux));
+	RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$mux);
 	set_src_attr(cell, that);
 
 	RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, left.size());
@@ -837,7 +838,7 @@ struct AST_INTERNAL::ProcessGenerator
 				}
 				RTLIL::Const polarity = polarity_builder.build();
 
-				RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($print));
+				RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$print);
 				set_src_attr(cell, ast);
 				cell->setParam(ID::TRG_WIDTH, triggers.size());
 				cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
@@ -935,7 +936,7 @@ struct AST_INTERNAL::ProcessGenerator
 				}
 				RTLIL::Const polarity = polarity_builder.build();
 
-				RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check));
+				RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
 				set_src_attr(cell, ast);
 				cell->set_bool_attribute(ID(keep));
 				for (auto &attr : ast->attributes) {
@@ -1443,7 +1444,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
 	// cases this variable is used to hold the type of the cell that should
 	// be instantiated for this type of AST node.
-	IdString type_name;
+	TwineRef type_name;
 
 	switch (type)
 	{
@@ -1735,7 +1736,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					}
 					if (GetSize(shift_val) >= 32)
 						fake_ast->children[1]->is_signed = true;
-					RTLIL::SigSpec sig = binop2rtlil(fake_ast.get(), ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
+					RTLIL::SigSpec sig = binop2rtlil(fake_ast.get(), TW($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
 					return sig;
 				} else {
 					chunk.width = children[0]->range_left - children[0]->range_right + 1;
@@ -1841,9 +1842,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		input_error("Assignment pattern is only supported for whole unpacked array assignments.\n");
 
 	// generate cells for unary operations: $not, $pos, $neg
-	if (0) { case AST_BIT_NOT: type_name = ID($not); }
-	if (0) { case AST_POS:     type_name = ID($pos); }
-	if (0) { case AST_NEG:     type_name = ID($neg); }
+	if (0) { case AST_BIT_NOT: type_name = TW($not); }
+	if (0) { case AST_POS:     type_name = TW($pos); }
+	if (0) { case AST_NEG:     type_name = TW($neg); }
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
 			is_signed = children[0]->is_signed;
@@ -1856,10 +1857,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $and, $or, $xor, $xnor
-	if (0) { case AST_BIT_AND:  type_name = ID($and); }
-	if (0) { case AST_BIT_OR:   type_name = ID($or); }
-	if (0) { case AST_BIT_XOR:  type_name = ID($xor); }
-	if (0) { case AST_BIT_XNOR: type_name = ID($xnor); }
+	if (0) { case AST_BIT_AND:  type_name = TW($and); }
+	if (0) { case AST_BIT_OR:   type_name = TW($or); }
+	if (0) { case AST_BIT_XOR:  type_name = TW($xor); }
+	if (0) { case AST_BIT_XNOR: type_name = TW($xnor); }
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
@@ -1873,10 +1874,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
-	if (0) { case AST_REDUCE_AND:  type_name = ID($reduce_and); }
-	if (0) { case AST_REDUCE_OR:   type_name = ID($reduce_or); }
-	if (0) { case AST_REDUCE_XOR:  type_name = ID($reduce_xor); }
-	if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); }
+	if (0) { case AST_REDUCE_AND:  type_name = TW($reduce_and); }
+	if (0) { case AST_REDUCE_OR:   type_name = TW($reduce_or); }
+	if (0) { case AST_REDUCE_XOR:  type_name = TW($reduce_xor); }
+	if (0) { case AST_REDUCE_XNOR: type_name = TW($reduce_xnor); }
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL();
 			RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
@@ -1885,7 +1886,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 	// generate cells for unary operations: $reduce_bool
 	// (this is actually just an $reduce_or, but for clarity a different cell type is used)
-	if (0) { case AST_REDUCE_BOOL:  type_name = ID($reduce_bool); }
+	if (0) { case AST_REDUCE_BOOL:  type_name = TW($reduce_bool); }
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL();
 			RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
@@ -1893,12 +1894,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $shl, $shr, $sshl, $sshr
-	if (0) { case AST_SHIFT_LEFT:   type_name = ID($shl); }
-	if (0) { case AST_SHIFT_RIGHT:  type_name = ID($shr); }
-	if (0) { case AST_SHIFT_SLEFT:  type_name = ID($sshl); }
-	if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); }
-	if (0) { case AST_SHIFTX:       type_name = ID($shiftx); }
-	if (0) { case AST_SHIFT:        type_name = ID($shift); }
+	if (0) { case AST_SHIFT_LEFT:   type_name = TW($shl); }
+	if (0) { case AST_SHIFT_RIGHT:  type_name = TW($shr); }
+	if (0) { case AST_SHIFT_SLEFT:  type_name = TW($sshl); }
+	if (0) { case AST_SHIFT_SRIGHT: type_name = TW($sshr); }
+	if (0) { case AST_SHIFTX:       type_name = TW($shiftx); }
+	if (0) { case AST_SHIFT:        type_name = TW($shift); }
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
@@ -1923,19 +1924,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			int width = width_hint > 0 ? width_hint : left.size();
 			is_signed = children[0]->is_signed;
 			if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
-				return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right);
-			return binop2rtlil(this, ID($pow), width, left, right);
+				return binop2rtlil(this, TW($shl), width, RTLIL::SigSpec(1, left.size()), right);
+			return binop2rtlil(this, TW($pow), width, left, right);
 		}
 
 	// generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
-	if (0) { case AST_LT:  type_name = ID($lt); }
-	if (0) { case AST_LE:  type_name = ID($le); }
-	if (0) { case AST_EQ:  type_name = ID($eq); }
-	if (0) { case AST_NE:  type_name = ID($ne); }
-	if (0) { case AST_EQX: type_name = ID($eqx); }
-	if (0) { case AST_NEX: type_name = ID($nex); }
-	if (0) { case AST_GE:  type_name = ID($ge); }
-	if (0) { case AST_GT:  type_name = ID($gt); }
+	if (0) { case AST_LT:  type_name = TW($lt); }
+	if (0) { case AST_LE:  type_name = TW($le); }
+	if (0) { case AST_EQ:  type_name = TW($eq); }
+	if (0) { case AST_NE:  type_name = TW($ne); }
+	if (0) { case AST_EQX: type_name = TW($eqx); }
+	if (0) { case AST_NEX: type_name = TW($nex); }
+	if (0) { case AST_GE:  type_name = TW($ge); }
+	if (0) { case AST_GT:  type_name = TW($gt); }
 		{
 			int width = max(width_hint, 1);
 			width_hint = -1, sign_hint = true;
@@ -1948,11 +1949,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $add, $sub, $mul, $div, $mod
-	if (0) { case AST_ADD: type_name = ID($add); }
-	if (0) { case AST_SUB: type_name = ID($sub); }
-	if (0) { case AST_MUL: type_name = ID($mul); }
-	if (0) { case AST_DIV: type_name = ID($div); }
-	if (0) { case AST_MOD: type_name = ID($mod); }
+	if (0) { case AST_ADD: type_name = TW($add); }
+	if (0) { case AST_SUB: type_name = TW($sub); }
+	if (0) { case AST_MUL: type_name = TW($mul); }
+	if (0) { case AST_DIV: type_name = TW($div); }
+	if (0) { case AST_MOD: type_name = TW($mod); }
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
@@ -1978,8 +1979,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $logic_and, $logic_or
-	if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); }
-	if (0) { case AST_LOGIC_OR:  type_name = ID($logic_or); }
+	if (0) { case AST_LOGIC_AND: type_name = TW($logic_and); }
+	if (0) { case AST_LOGIC_OR:  type_name = TW($logic_or); }
 		{
 			RTLIL::SigSpec left = children[0]->genRTLIL();
 			RTLIL::SigSpec right = children[1]->genRTLIL();
@@ -1990,7 +1991,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_LOGIC_NOT:
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL();
-			return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg);
+			return uniop2rtlil(this, TW($logic_not), max(width_hint, 1), arg);
 		}
 
 	// generate multiplexer for ternary operator (aka ?:-operator)
@@ -2021,7 +2022,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
 
 				if (cond.size() > 1)
-					cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
+					cond = uniop2rtlil(this, TW($reduce_bool), 1, cond, false);
 
 				int width = max(val1.size(), val2.size());
 				log_assert(is_signed == children[1]->is_signed);
@@ -2043,7 +2044,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			std::stringstream sstr;
 			sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
 
-			RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($memrd));
+			RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$memrd);
 			set_src_attr(cell, this);
 
 			RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_DATA"}, current_module->memories[current_module->design->twines.lookup(str)]->width);
@@ -2083,7 +2084,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			SigSpec en_sig = children[2]->genRTLIL();
 
-			RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($meminit_v2));
+			RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$meminit_v2);
 			set_src_attr(cell, this);
 
 			int mem_width, mem_size, addr_bits;
@@ -2133,7 +2134,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (GetSize(check) != 1)
 				check = current_module->ReduceBool(NEW_TWINE, check);
 
-			RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check));
+			RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
 			set_src_attr(cell, this);
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
@@ -2185,7 +2186,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			RTLIL::IdString id = str;
 			check_unique_id(current_module, id, this, "cell");
-			RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, "");
+			RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, Twine::Null);
 			set_src_attr(cell, this);
 
 			for (auto it = children.begin(); it != children.end(); it++) {
@@ -2202,10 +2203,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					const auto* value = child->children[0].get();
 					if (value->type == AST_REALVALUE)
 						log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
-								cell, paraname.unescape(), value->realvalue);
+								cell, design->twines.unescaped_str(paraname), value->realvalue);
 					else if (value->type != AST_CONSTANT)
 						input_error("Parameter %s.%s with non-constant value!\n",
-								cell, paraname.unescape());
+								cell, design->twines.unescaped_str(paraname));
 					cell->parameters[paraname] = value->asParaConst();
 					continue;
 				}
@@ -2260,7 +2261,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					input_error("Attribute `%s' with non-constant value.\n", attr.first);
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
-			if (cell->type == ID($specify2)) {
+			if (cell->type == TW($specify2)) {
 				int src_width = GetSize(cell->getPort(TW::SRC));
 				int dst_width = GetSize(cell->getPort(TW::DST));
 				bool full = cell->getParam(ID::FULL).as_bool();
@@ -2269,7 +2270,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				cell->setParam(ID::SRC_WIDTH, Const(src_width));
 				cell->setParam(ID::DST_WIDTH, Const(dst_width));
 			}
-			else if (cell->type ==  ID($specify3)) {
+			else if (cell->type ==  TW($specify3)) {
 				int dat_width = GetSize(cell->getPort(TW::DAT));
 				int dst_width = GetSize(cell->getPort(TW::DST));
 				if (dat_width != dst_width)
@@ -2278,7 +2279,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				cell->setParam(ID::SRC_WIDTH, Const(src_width));
 				cell->setParam(ID::DST_WIDTH, Const(dst_width));
 			}
-			else if (cell->type == ID($specrule)) {
+			else if (cell->type == TW($specrule)) {
 				int src_width = GetSize(cell->getPort(TW::SRC));
 				int dst_width = GetSize(cell->getPort(TW::DST));
 				cell->setParam(ID::SRC_WIDTH, Const(src_width));
@@ -2356,7 +2357,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (width <= 0)
 					input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str));
 
-				Cell *cell = current_module->addCell(Twine{myid}, str.substr(1));
+				TwineRef _type = current_module->design->twines.add(Twine{str.substr(1)});
+				Cell *cell = current_module->addCell(Twine{myid}, _type);
 				set_src_attr(cell, this);
 				cell->parameters[ID::WIDTH] = width;
 
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 18b742b84..3cba1b939 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -228,7 +228,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 					vector<Cell*> remove_cells;
 
 					for (auto cell : module->cells())
-						if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
+						if (cell->type == TW($lut) && cell->getParam(ID::LUT) == buffer_lut) {
 							module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
 							remove_cells.push_back(cell);
 						}
@@ -381,7 +381,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 					if (dff_name.empty()) {
 						cell = module->addFfGate(NEW_TWINE, blif_wire(d), blif_wire(q));
 					} else {
-						cell = module->addCell(NEW_TWINE, dff_name);
+						cell = module->addCell(NEW_TWINE, design->twines.add(Twine{dff_name.str()}));
 						cell->setPort(TW::D, blif_wire(d));
 						cell->setPort(TW::Q, blif_wire(q));
 					}
@@ -400,7 +400,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 					goto error;
 
 				IdString celltype = RTLIL::escape_id(p);
-				RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype);
+				RTLIL::Cell *cell = module->addCell(NEW_TWINE, design->twines.add(Twine{celltype.str()}));
 				RTLIL::Module *cell_mod = design->module(celltype);
 
 				dict<TwineRef, dict<int, SigBit>> cell_wideports_cache;
@@ -542,7 +542,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				finished_parsing_constval:
 					if (state == RTLIL::State::Sa)
 						state = RTLIL::State::S0;
-					if (output_sig.as_wire()->name == ID($undef))
+					if (output_sig.as_wire()->name == TW($undef))
 						state = RTLIL::State::Sx;
 					module->connect(RTLIL::SigSig(output_sig, state));
 					goto continue_without_read;
@@ -550,7 +550,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 
 				if (sop_mode)
 				{
-					sopcell = module->addCell(NEW_TWINE, ID($sop));
+					sopcell = module->addCell(NEW_TWINE, TW::$sop);
 					sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
 					sopcell->parameters[ID::DEPTH] = 0;
 					sopcell->parameters[ID::TABLE] = RTLIL::Const();
@@ -566,7 +566,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				}
 				else
 				{
-					RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($lut));
+					RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$lut);
 					cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
 					cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
 					cell->setPort(TW::A, input_sig);
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc
index 64a2c8bee..04feeb74d 100644
--- a/frontends/json/jsonparse.cc
+++ b/frontends/json/jsonparse.cc
@@ -532,7 +532,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
 
 			IdString cell_type = RTLIL::escape_id(type_node->data_string.c_str());
 
-			Cell *cell = module->addCell(Twine{cell_name.str()}, cell_type);
+			Cell *cell = module->addCell(Twine{cell_name.str()}, Twine{cell_type.str()});
 
 			if (cell_node->data_dict.count("connections") == 0)
 				log_error("JSON cells node '%s' has no connections attribute.\n", cell_name.unescape());
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index f096720f7..7da45363f 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -186,7 +186,7 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
 {
 	RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
 
-	RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($tribuf));
+	RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$tribuf);
 	cell->setParam(ID::WIDTH, GetSize(func));
 	cell->setPort(TW::A, func);
 	cell->setPort(TW::EN, module->NotGate(NEW_TWINE, three_state));
@@ -246,17 +246,17 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells_) {
-			if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clk_sig) {
+			if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == clk_sig) {
 				clk_sig = it.second->getPort(TW::A);
 				clk_polarity = !clk_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
+			if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
 				clear_sig = it.second->getPort(TW::A);
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
+			if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
 				preset_sig = it.second->getPort(TW::A);
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
@@ -271,7 +271,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
 			module->addNotGate(NEW_TWINE, q_sig, out_sig);
 		}
 
-		RTLIL::Cell* cell = module->addCell(NEW_TWINE, "");
+		RTLIL::Cell* cell = module->addCell(NEW_TWINE, Twine::Null);
 		cell->setPort(TW::D, data_sig);
 		cell->setPort(TW::Q, q_sig);
 		cell->setPort(TW::C, clk_sig);
@@ -355,17 +355,17 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells_) {
-			if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == enable_sig) {
+			if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == enable_sig) {
 				enable_sig = it.second->getPort(TW::A);
 				enable_polarity = !enable_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
+			if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
 				clear_sig = it.second->getPort(TW::A);
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
+			if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
 				preset_sig = it.second->getPort(TW::A);
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
@@ -373,7 +373,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 		}
 	}
 
-	RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($_NOT_));
+	RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$_NOT_);
 	cell->setPort(TW::A, iq_sig);
 	cell->setPort(TW::Y, iqn_sig);
 
@@ -384,7 +384,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 
 		if (clear_polarity == true || clear_polarity != enable_polarity)
 		{
-			RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
+			RTLIL::Cell *inv = module->addCell(NEW_TWINE, TW::$_NOT_);
 			inv->setPort(TW::A, clear_sig);
 			inv->setPort(TW::Y, module->addWire(NEW_TWINE));
 
@@ -394,12 +394,12 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 				clear_enable = inv->getPort(TW::Y);
 		}
 
-		RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_AND_));
+		RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, TW::$_AND_);
 		data_gate->setPort(TW::A, data_sig);
 		data_gate->setPort(TW::B, clear_negative);
 		data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
 
-		RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
+		RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? TW::$_OR_ : TW::$_AND_);
 		enable_gate->setPort(TW::A, enable_sig);
 		enable_gate->setPort(TW::B, clear_enable);
 		enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
@@ -412,7 +412,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 
 		if (preset_polarity == false || preset_polarity != enable_polarity)
 		{
-			RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
+			RTLIL::Cell *inv = module->addCell(NEW_TWINE, TW::$_NOT_);
 			inv->setPort(TW::A, preset_sig);
 			inv->setPort(TW::Y, module->addWire(NEW_TWINE));
 
@@ -422,18 +422,19 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 				preset_enable = inv->getPort(TW::Y);
 		}
 
-		RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_OR_));
+		RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, TW::$_OR_);
 		data_gate->setPort(TW::A, data_sig);
 		data_gate->setPort(TW::B, preset_positive);
 		data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
 
-		RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
+		RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? TW::$_OR_ : TW::$_AND_);
 		enable_gate->setPort(TW::A, enable_sig);
 		enable_gate->setPort(TW::B, preset_enable);
 		enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
 	}
 
-	cell = module->addCell(NEW_TWINE, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
+	TwineRef _t = module->design->twines.add(Twine{stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')});
+	cell = module->addCell(NEW_TWINE, _t);
 	cell->setPort(TW::D, data_sig);
 	cell->setPort(TW::Q, iq_sig);
 	cell->setPort(TW::E, enable_sig);
@@ -798,7 +799,7 @@ struct LibertyFrontend : public Frontend {
 					if (wi->port_input) {
 						for (auto wo : module->wires())
 						if (wo->port_output) {
-							RTLIL::Cell *spec = module->addCell(NEW_TWINE, ID($specify2));
+							RTLIL::Cell *spec = module->addCell(NEW_TWINE, TW::$specify2);
 							spec->setParam(ID::SRC_WIDTH, wi->width);
 							spec->setParam(ID::DST_WIDTH, wo->width);
 							spec->setParam(ID::T_FALL_MAX, 1000);
diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc
index 697d2e8ea..8f41c79f7 100644
--- a/frontends/rpc/rpc_frontend.cc
+++ b/frontends/rpc/rpc_frontend.cc
@@ -157,7 +157,7 @@ struct RpcServer {
 struct RpcModule : RTLIL::Module {
 	std::shared_ptr<RpcServer> server;
 
-	RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
+	TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
 		std::string stripped_name = design->twines.str(meta_->name);
 		if (stripped_name.compare(0, 9, "$abstract") == 0)
 			stripped_name = stripped_name.substr(9);
@@ -215,7 +215,7 @@ struct RpcModule : RTLIL::Module {
 				log("Importing `%s' as `%s'.\n", derived_design->twines.str(module.first), mangled_name);
 
 				RTLIL::IdString original_name = RTLIL::IdString(derived_design->twines.str(module.first));
-				RTLIL::Module *t = module.second->clone(design, RTLIL::IdString(mangled_name));
+				RTLIL::Module *t = module.second->clone(design, design->twines.add(Twine{mangled_name}));
 				t->attributes.erase(ID::top);
 				if (!t->has_attribute(ID::hdlname))
 					t->set_string_attribute(ID::hdlname, original_name.str());
@@ -224,7 +224,7 @@ struct RpcModule : RTLIL::Module {
 			delete derived_design;
 		}
 
-		return derived_name;
+		return design->twines.add(Twine{derived_name});
 	}
 
 	RTLIL::Module *clone() const override {
diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc
index aaaa1fafa..64fcef407 100644
--- a/frontends/rtlil/rtlil_frontend.cc
+++ b/frontends/rtlil/rtlil_frontend.cc
@@ -341,7 +341,7 @@ struct RTLILFrontendWorker {
 			error("No wires found for legalization");
 		int hash = hash_ops<RTLIL::IdString>::hash(id).yield();
 		RTLIL::Wire *wire = current_module->wire_at(abs(hash % wires_size));
-		log("Legalizing wire `%s' to `%s'.\n", id.unescape(), wire->name.unescape());
+		log("Legalizing wire `%s' to `%s'.\n", design->twines.unescaped_str(id), design->twines.unescaped_str(wire->name));
 		return wire;
 	}
 
@@ -748,7 +748,7 @@ struct RTLILFrontendWorker {
 			} else
 				error("RTLIL error: redefinition of cell %s.", cell_name_str);
 		}
-		RTLIL::Cell *cell = current_module->addCell(Twine{cell_name_str}, cell_type);
+		RTLIL::Cell *cell = current_module->addCell(cell_name_ref, design->twines.add(Twine{cell_type.str()}));
 		cell->absorb_attrs(std::move(attrbuf));
 
 		while (true)
diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc
index ab8900991..f3ecd2b27 100644
--- a/kernel/cellaigs.cc
+++ b/kernel/cellaigs.cc
@@ -302,60 +302,60 @@ Aig::Aig(Cell *cell)
 		}
 	}
 
-	if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
+	if (cell->type.in(TW($not), TW($_NOT_), TW($pos), TW($buf), TW($_BUF_)))
 	{
 		for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
 			int A = mk.inport(TW::A, i);
-			int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A;
+			int Y = cell->type.in(TW($not), TW($_NOT_)) ? mk.not_gate(A) : A;
 			mk.outport(Y, TW::Y, i);
 		}
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
+	if (cell->type.in(TW($and), TW($_AND_), TW($_NAND_), TW($or), TW($_OR_), TW($_NOR_), TW($xor), TW($xnor), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
 	{
 		for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
 			int A = mk.inport(TW::A, i);
 			int B = mk.inport(TW::B, i);
-			int Y = cell->type.in(ID($and), ID($_AND_))   ? mk.and_gate(A, B) :
-			        cell->type.in(ID($_NAND_))            ? mk.nand_gate(A, B) :
-			        cell->type.in(ID($or), ID($_OR_))     ? mk.or_gate(A, B) :
-			        cell->type.in(ID($_NOR_))             ? mk.nor_gate(A, B) :
-			        cell->type.in(ID($xor), ID($_XOR_))   ? mk.xor_gate(A, B) :
-			        cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) :
-			        cell->type.in(ID($_ANDNOT_))          ? mk.andnot_gate(A, B) :
-			        cell->type.in(ID($_ORNOT_))           ? mk.ornot_gate(A, B) : -1;
+			int Y = cell->type.in(TW($and), TW($_AND_))   ? mk.and_gate(A, B) :
+			        cell->type.in(TW($_NAND_))            ? mk.nand_gate(A, B) :
+			        cell->type.in(TW($or), TW($_OR_))     ? mk.or_gate(A, B) :
+			        cell->type.in(TW($_NOR_))             ? mk.nor_gate(A, B) :
+			        cell->type.in(TW($xor), TW($_XOR_))   ? mk.xor_gate(A, B) :
+			        cell->type.in(TW($xnor), TW($_XNOR_)) ? mk.xnor_gate(A, B) :
+			        cell->type.in(TW($_ANDNOT_))          ? mk.andnot_gate(A, B) :
+			        cell->type.in(TW($_ORNOT_))           ? mk.ornot_gate(A, B) : -1;
 			mk.outport(Y, TW::Y, i);
 		}
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
+	if (cell->type.in(TW($mux), TW($_MUX_), TW($_NMUX_)))
 	{
 		int S = mk.inport(TW::S);
 		for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
 			int A = mk.inport(TW::A, i);
 			int B = mk.inport(TW::B, i);
 			int Y = mk.mux_gate(A, B, S);
-			if (cell->type == ID($_NMUX_))
+			if (cell->type == TW($_NMUX_))
 				Y = mk.not_gate(Y);
 			mk.outport(Y, TW::Y, i);
 		}
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)))
+	if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool)))
 	{
 		int Y = mk.inport(TW::A, 0);
 		for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++) {
 			int A = mk.inport(TW::A, i);
-			if (cell->type == ID($reduce_and))  Y = mk.and_gate(A, Y);
-			if (cell->type == ID($reduce_or))   Y = mk.or_gate(A, Y);
-			if (cell->type == ID($reduce_bool)) Y = mk.or_gate(A, Y);
-			if (cell->type == ID($reduce_xor))  Y = mk.xor_gate(A, Y);
-			if (cell->type == ID($reduce_xnor)) Y = mk.xor_gate(A, Y);
+			if (cell->type == TW($reduce_and))  Y = mk.and_gate(A, Y);
+			if (cell->type == TW($reduce_or))   Y = mk.or_gate(A, Y);
+			if (cell->type == TW($reduce_bool)) Y = mk.or_gate(A, Y);
+			if (cell->type == TW($reduce_xor))  Y = mk.xor_gate(A, Y);
+			if (cell->type == TW($reduce_xnor)) Y = mk.xor_gate(A, Y);
 		}
-		if (cell->type == ID($reduce_xnor))
+		if (cell->type == TW($reduce_xnor))
 			Y = mk.not_gate(Y);
 		mk.outport(Y, TW::Y, 0);
 		for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++)
@@ -363,31 +363,31 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or)))
+	if (cell->type.in(TW($logic_not), TW($logic_and), TW($logic_or)))
 	{
 		int A = mk.inport(TW::A, 0), Y = -1;
 		for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++)
 			A = mk.or_gate(mk.inport(TW::A, i), A);
-		if (cell->type.in(ID($logic_and), ID($logic_or))) {
+		if (cell->type.in(TW($logic_and), TW($logic_or))) {
 			int B = mk.inport(TW::B, 0);
 			for (int i = 1; i < GetSize(cell->getPort(TW::B)); i++)
 				B = mk.or_gate(mk.inport(TW::B, i), B);
-			if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B);
-			if (cell->type == ID($logic_or))  Y = mk.or_gate(A, B);
+			if (cell->type == TW($logic_and)) Y = mk.and_gate(A, B);
+			if (cell->type == TW($logic_or))  Y = mk.or_gate(A, B);
 		} else {
-			if (cell->type == ID($logic_not)) Y = mk.not_gate(A);
+			if (cell->type == TW($logic_not)) Y = mk.not_gate(A);
 		}
 		mk.outport_bool(Y, TW::Y);
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($add), ID($sub)))
+	if (cell->type.in(TW($add), TW($sub)))
 	{
 		int width = GetSize(cell->getPort(TW::Y));
 		vector<int> A = mk.inport_vec(TW::A, width);
 		vector<int> B = mk.inport_vec(TW::B, width);
 		int carry = mk.bool_node(false);
-		if (cell->type == ID($sub)) {
+		if (cell->type == TW($sub)) {
 			for (auto &n : B)
 				n = mk.not_gate(n);
 			carry = mk.not_gate(carry);
@@ -397,17 +397,17 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge)))
+	if (cell->type.in(TW($lt), TW($gt), TW($le), TW($ge)))
 	{
 		int width = std::max(GetSize(cell->getPort(TW::A)),
 							 GetSize(cell->getPort(TW::B))) + 1;
 		vector<int> A = mk.inport_vec(TW::A, width);
 		vector<int> B = mk.inport_vec(TW::B, width);
 
-		if (cell->type.in(ID($gt), ID($ge)))
+		if (cell->type.in(TW($gt), TW($ge)))
 			std::swap(A, B);
 
-		int carry = mk.bool_node(!cell->type.in(ID($le), ID($ge)));
+		int carry = mk.bool_node(!cell->type.in(TW($le), TW($ge)));
 		for (auto &n : B)
 			n = mk.not_gate(n);
 		vector<int> Y = mk.adder(A, B, carry);
@@ -417,7 +417,7 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type == ID($alu))
+	if (cell->type == TW($alu))
 	{
 		int width = GetSize(cell->getPort(TW::Y));
 		vector<int> A = mk.inport_vec(TW::A, width);
@@ -436,7 +436,7 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($eq), ID($ne)))
+	if (cell->type.in(TW($eq), TW($ne)))
 	{
 		int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
 		vector<int> A = mk.inport_vec(TW::A, width);
@@ -444,13 +444,13 @@ Aig::Aig(Cell *cell)
 		int Y = mk.bool_node(false);
 		for (int i = 0; i < width; i++)
 			Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i]));
-		if (cell->type == ID($eq))
+		if (cell->type == TW($eq))
 			Y = mk.not_gate(Y);
 		mk.outport_bool(Y, TW::Y);
 		goto optimize;
 	}
 
-	if (cell->type == ID($_AOI3_))
+	if (cell->type == TW($_AOI3_))
 	{
 		int A = mk.inport(TW::A);
 		int B = mk.inport(TW::B);
@@ -460,7 +460,7 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type == ID($_OAI3_))
+	if (cell->type == TW($_OAI3_))
 	{
 		int A = mk.inport(TW::A);
 		int B = mk.inport(TW::B);
@@ -470,7 +470,7 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type == ID($_AOI4_))
+	if (cell->type == TW($_AOI4_))
 	{
 		int A = mk.inport(TW::A);
 		int B = mk.inport(TW::B);
@@ -482,7 +482,7 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type == ID($_OAI4_))
+	if (cell->type == TW($_OAI4_))
 	{
 		int A = mk.inport(TW::A);
 		int B = mk.inport(TW::B);
diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 488bfeb0e..f622753ec 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool();
+	bool is_signed = (cell->type != TW($buf)) && cell->getParam(ID::A_SIGNED).as_bool();
 	int a_width = GetSize(cell->getPort(TW::A));
 	int y_width = GetSize(cell->getPort(TW::Y));
 
@@ -44,7 +44,7 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 	int b_width = GetSize(cell->getPort(TW::B));
 	int y_width = GetSize(cell->getPort(TW::Y));
 
-	if (cell->type == ID($and) && !is_signed) {
+	if (cell->type == TW($and) && !is_signed) {
 		if (a_width > b_width)
 			a_width = b_width;
 		else
@@ -86,7 +86,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 	int b_width = GetSize(cell->getPort(TW::B));
 	int y_width = GetSize(cell->getPort(TW::Y));
 
-	if (!is_signed && cell->type != ID($sub)) {
+	if (!is_signed && cell->type != TW($sub)) {
 		int ab_width = std::max(a_width, b_width);
 		y_width = std::min(y_width, ab_width+1);
 	}
@@ -252,16 +252,16 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 		// lowest position of A that can be moved to Y[i]
 		int a_range_lower;
 
-		if (cell->type.in(ID($shl), ID($sshl))) {
+		if (cell->type.in(TW($shl), TW($sshl))) {
 			b_range_upper = a_width + b_high;
 			if (is_signed) b_range_upper -= 1;
 			a_range_lower = max(0, i - b_high);
 			a_range_upper = min(i+1, a_width);
-		} else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) {
+		} else if (cell->type.in(TW($shr), TW($sshr)) || (cell->type.in(TW($shift), TW($shiftx)) && !is_b_signed)) {
 			b_range_upper = a_width;
 			a_range_lower = min(i, a_width - 1);
 			a_range_upper = min(i+1 + b_high, a_width);
-		} else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) {
+		} else if (cell->type.in(TW($shift), TW($shiftx)) && is_b_signed) {
 			// can go both ways depending on sign of B
 			// 2's complement range is different depending on direction
 			b_range_upper = a_width - b_low;
@@ -284,7 +284,7 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 		for (int k = 0; k < b_width_capped; k++) {
 			// left shifts
-			if (cell->type.in(ID($shl), ID($sshl))) {
+			if (cell->type.in(TW($shl), TW($sshl))) {
 				if (a_width == 1 && is_signed) {
 					int skip = 1 << (k + 1);
 					int base = skip -1;
@@ -298,21 +298,21 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 						db->add_edge(cell, TW::B, k, TW::Y, i, -1);
 				}
 			// right shifts
-			} else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) {
+			} else if (cell->type.in(TW($shr), TW($sshr)) || (cell->type.in(TW($shift), TW($shiftx)) && !is_b_signed)) {
 				if (is_signed) {
 					bool shift_in_bulk = i < a_width - 1;
 					// can we jump into the zero-padding by toggling B[k]?
 					bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \
 									&& (((y_width - i) & ~(1 << k)) < (1 << b_width_capped)));
 
-					if (shift_in_bulk || (cell->type.in(ID($shr), ID($shift), ID($shiftx)) && zpad_jump))
+					if (shift_in_bulk || (cell->type.in(TW($shr), TW($shift), TW($shiftx)) && zpad_jump))
 						db->add_edge(cell, TW::B, k, TW::Y, i, -1);
 				} else {
 					if (i < a_width)
 						db->add_edge(cell, TW::B, k, TW::Y, i, -1);
 				}
 			// bidirectional shifts (positive B shifts right, negative left)
-			} else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) {
+			} else if (cell->type.in(TW($shift), TW($shiftx)) && is_b_signed) {
 				if (is_signed) {
 					if (k != b_width_capped - 1) {
 						bool r_shift_in_bulk = i < a_width - 1;
@@ -344,7 +344,7 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	log_assert(cell->type == ID($mem_v2));
+	log_assert(cell->type == TW($mem_v2));
 	Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
 	int n_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
 	int abits = cell->getParam(ID::ABITS).as_int();
@@ -366,12 +366,12 @@ void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	log_assert(cell->type.in(ID($memrd), ID($memrd_v2)));
+	log_assert(cell->type.in(TW($memrd), TW($memrd_v2)));
 	int abits = cell->getParam(ID::ABITS).as_int();
 	int width = cell->getParam(ID::WIDTH).as_int();
 
 	if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
-		if (cell->type == ID($memrd_v2)) {
+		if (cell->type == TW($memrd_v2)) {
 			for (int k = 0; k < width; k++)
 				db->add_edge(cell, TW::ARST, 0, TW::DATA, k, -1);
 		}
@@ -385,11 +385,11 @@ void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	if (cell->type == ID($mem_v2))
+	if (cell->type == TW($mem_v2))
 		packed_mem_op(db, cell);
-	else if (cell->type.in(ID($memrd), ID($memrd_v2)))
+	else if (cell->type.in(TW($memrd), TW($memrd_v2)))
 		memrd_op(db, cell);
-	else if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit)))
+	else if (cell->type.in(TW($memwr), TW($memwr_v2), TW($meminit)))
 		return; /* no edges here */
 	else
 		log_abort();
@@ -399,7 +399,7 @@ void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
 	int width = cell->getPort(TW::Q).size();
 
-	if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
+	if (cell->type.in(TW($dlatch), TW($adlatch), TW($dlatchsr))) {
 		for (int k = 0; k < width; k++) {
 			db->add_edge(cell, TW::D, k, TW::Q, k, -1);
 			db->add_edge(cell, TW::EN, 0, TW::Q, k, -1);
@@ -485,82 +485,82 @@ PRIVATE_NAMESPACE_END
 
 bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
 {
-	if (cell->type.in(ID($not), ID($pos), ID($buf))) {
+	if (cell->type.in(TW($not), TW($pos), TW($buf))) {
 		bitwise_unary_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
+	if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
 		bitwise_binary_op(this, cell);
 		return true;
 	}
 
-	if (cell->type == ID($neg)) {
+	if (cell->type == TW($neg)) {
 		arith_neg_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($add), ID($sub))) {
+	if (cell->type.in(TW($add), TW($sub))) {
 		arith_binary_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not))) {
+	if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($logic_not))) {
 		reduce_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($logic_and), ID($logic_or))) {
+	if (cell->type.in(TW($logic_and), TW($logic_or))) {
 		logic_op(this, cell);
 		return true;
 	}
 
-	if (cell->type == ID($slice)) {
+	if (cell->type == TW($slice)) {
 		slice_op(this, cell);
 		return true;
 	}
 
-	if (cell->type == ID($concat)) {
+	if (cell->type == TW($concat)) {
 		concat_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
+	if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx))) {
 		shift_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
+	if (cell->type.in(TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt))) {
 		compare_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($mux), ID($pmux))) {
+	if (cell->type.in(TW($mux), TW($pmux))) {
 		mux_op(this, cell);
 		return true;
 	}
 
-	if (cell->type == ID($bmux)) {
+	if (cell->type == TW($bmux)) {
 		bmux_op(this, cell);
 		return true;
 	}
 
-	if (cell->type == ID($demux)) {
+	if (cell->type == TW($demux)) {
 		demux_op(this, cell);
 		return true;
 	}
 
-	if (cell->type == ID($bweqx)) {
+	if (cell->type == TW($bweqx)) {
 		bweqx_op(this, cell);
 		return true;
 	}
 
-	if (cell->type == ID($bwmux)) {
+	if (cell->type == TW($bwmux)) {
 		bwmux_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) {
+	if (cell->type.in(TW($mem_v2), TW($memrd), TW($memrd_v2), TW($memwr), TW($memwr_v2), TW($meminit))) {
 		mem_op(this, cell);
 		return true;
 	}
@@ -570,21 +570,21 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 		return true;
 	}
 
-	if (cell->type.in(ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
+	if (cell->type.in(TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow))) {
 		full_op(this, cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($lut), ID($sop), ID($alu), ID($lcu), ID($macc), ID($macc_v2))) {
+	if (cell->type.in(TW($lut), TW($sop), TW($alu), TW($lcu), TW($macc), TW($macc_v2))) {
 		full_op(this, cell);
 		return true;
 	}
 
 	if (cell->type.in(
-			ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
-			ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
-			ID($_MUX4_), ID($_MUX8_), ID($_MUX16_), ID($_AOI3_), ID($_OAI3_), ID($_AOI4_),
-			ID($_OAI4_), ID($_TBUF_))) {
+			TW($_BUF_), TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_),
+			TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_), TW($_MUX_), TW($_NMUX_),
+			TW($_MUX4_), TW($_MUX8_), TW($_MUX16_), TW($_AOI3_), TW($_OAI3_), TW($_AOI4_),
+			TW($_OAI4_), TW($_TBUF_))) {
 		full_op(this, cell);
 		return true;
 	}
@@ -592,7 +592,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 	// FIXME: $specify2 $specify3 $specrule ???
 	// FIXME: $equiv $set_tag $get_tag $overwrite_tag $original_tag
 
-	if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)))
+	if (cell->type.in(TW($assert), TW($assume), TW($live), TW($fair), TW($cover), TW($initstate), TW($anyconst), TW($anyseq), TW($allconst), TW($allseq)))
 		return true; // no-op: these have either no inputs or no outputs
 
 	return false;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index a49e09310..0ba213857 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -65,6 +65,11 @@ struct CellTypes
 		cell_types[ct.type] = ct;
 	}
 
+	void setup_type(const std::string &type_str, const pool<TwineRef> &inputs, const pool<TwineRef> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)
+	{
+		setup_type(TW::lookup(type_str), inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable);
+	}
+
 	void setup_module(RTLIL::Module *module)
 	{
 		pool<TwineRef> inputs, outputs;
@@ -230,77 +235,77 @@ struct CellTypes
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
-			setup_type(TW($1), {TW::S, TW::R}, {TW::Q});
+			setup_type(stringf("$_SR_%c%c_", c1, c2), {TW::S, TW::R}, {TW::Q});
 
 		setup_type(TW($_FF_), {TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
-			setup_type(TW($1), {TW::C, TW::D}, {TW::Q});
+			setup_type(stringf("$_DFF_%c_", c1), {TW::C, TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
-			setup_type(TW($1), {TW::C, TW::D, TW::E}, {TW::Q});
+			setup_type(stringf("$_DFFE_%c%c_", c1, c2), {TW::C, TW::D, TW::E}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
-			setup_type(TW($1), {TW::C, TW::R, TW::D}, {TW::Q});
+			setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
 		for (auto c4 : list_np)
-			setup_type(TW($1), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
+			setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
-			setup_type(TW($1), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q});
+			setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_np)
-			setup_type(TW($1), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q});
+			setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_np)
-			setup_type(TW($1), {TW::C, TW::S, TW::R, TW::D}, {TW::Q});
+			setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {TW::C, TW::S, TW::R, TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_np)
 		for (auto c4 : list_np)
-			setup_type(TW($1), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q});
+			setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
-			setup_type(TW($1), {TW::C, TW::R, TW::D}, {TW::Q});
+			setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
 		for (auto c4 : list_np)
-			setup_type(TW($1), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
+			setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
 		for (auto c4 : list_np)
-			setup_type(TW($1), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
+			setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
 
 		for (auto c1 : list_np)
-			setup_type(TW($1), {TW::E, TW::D}, {TW::Q});
+			setup_type(stringf("$_DLATCH_%c_", c1), {TW::E, TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
-			setup_type(TW($1), {TW::E, TW::R, TW::D}, {TW::Q});
+			setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {TW::E, TW::R, TW::D}, {TW::Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_np)
-			setup_type(TW($1), {TW::E, TW::S, TW::R, TW::D}, {TW::Q});
+			setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {TW::E, TW::S, TW::R, TW::D}, {TW::Q});
 	}
 
 	void clear()
diff --git a/kernel/consteval.h b/kernel/consteval.h
index b748d1cef..1a12a741f 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -49,10 +49,10 @@ struct ConstEval
 		ct.static_cell_types = StaticCellTypes::Compat::nomem_noff;
 
 		for (auto &it : module->cells_) {
-			if (!ct.cell_known(it.second->type))
+			if (!ct.cell_known(it.second->type_impl))
 				continue;
 			for (auto &it2 : it.second->connections())
-				if (ct.cell_output(it.second->type, it2.first))
+				if (ct.cell_output(it.second->type_impl, it2.first))
 					sig2driver.insert(assign_map(it2.second), it.second);
 		}
 	}
@@ -93,7 +93,7 @@ struct ConstEval
 
 	bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)
 	{
-		if (cell->type == ID($lcu))
+		if (cell->type == TW($lcu))
 		{
 			RTLIL::SigSpec sig_p = cell->getPort(TW::P);
 			RTLIL::SigSpec sig_g = cell->getPort(TW::G);
@@ -147,7 +147,7 @@ struct ConstEval
 		if (cell->hasPort(TW::B))
 			sig_b = cell->getPort(TW::B);
 
-		if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))
+		if (cell->type.in(TW($mux), TW($pmux), TW($_MUX_), TW($_NMUX_)))
 		{
 			std::vector<RTLIL::SigSpec> y_candidates;
 			int count_set_s_bits = 0;
@@ -176,7 +176,7 @@ struct ConstEval
 			for (auto &yc : y_candidates) {
 				if (!eval(yc, undef, cell))
 					return false;
-				if (cell->type == ID($_NMUX_))
+				if (cell->type == TW($_NMUX_))
 					y_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));
 				else
 					y_values.push_back(yc.as_const());
@@ -199,7 +199,7 @@ struct ConstEval
 			else
 				set(sig_y, y_values.front());
 		}
-		else if (cell->type == ID($bmux))
+		else if (cell->type == TW($bmux))
 		{
 			if (!eval(sig_s, undef, cell))
 				return false;
@@ -217,7 +217,7 @@ struct ConstEval
 				set(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));
 			}
 		}
-		else if (cell->type == ID($demux))
+		else if (cell->type == TW($demux))
 		{
 			if (!eval(sig_a, undef, cell))
 				return false;
@@ -229,7 +229,7 @@ struct ConstEval
 				set(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));
 			}
 		}
-		else if (cell->type == ID($fa))
+		else if (cell->type == TW($fa))
 		{
 			RTLIL::SigSpec sig_c = cell->getPort(TW::C);
 			RTLIL::SigSpec sig_x = cell->getPort(TW::X);
@@ -258,7 +258,7 @@ struct ConstEval
 			set(sig_y, val_y);
 			set(sig_x, val_x);
 		}
-		else if (cell->type == ID($alu))
+		else if (cell->type == TW($alu))
 		{
 			bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
 			bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
@@ -314,7 +314,7 @@ struct ConstEval
 				}
 			}
 		}
-		else if (cell->type.in(ID($macc), ID($macc_v2)))
+		else if (cell->type.in(TW($macc), TW($macc_v2)))
 		{
 			Macc macc;
 			macc.from_cell(cell);
@@ -336,7 +336,7 @@ struct ConstEval
 		{
 			RTLIL::SigSpec sig_c, sig_d;
 
-			if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
+			if (cell->type.in(TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_))) {
 				if (cell->hasPort(TW::C))
 					sig_c = cell->getPort(TW::C);
 				if (cell->hasPort(TW::D))
diff --git a/kernel/cost.cc b/kernel/cost.cc
index 77a34fb58..40bc7ad76 100644
--- a/kernel/cost.cc
+++ b/kernel/cost.cc
@@ -22,24 +22,24 @@ static unsigned int y_coef(TwineRef type)
 {
 	if (
 	  // equality
-	  type.in(ID($bweqx), ID($nex), ID($eqx)) ||
+	  type.in(TW($bweqx), TW($nex), TW($eqx)) ||
 	  // basic logic
-	  type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($not)) ||
+	  type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($not)) ||
 	  // mux
-	  type.in(ID($bwmux), ID($mux)) ||
+	  type.in(TW($bwmux), TW($mux)) ||
 	  // others
-	  type == ID($tribuf)) {
+	  type == TW($tribuf)) {
 		return 1;
-	} else if (type == ID($neg)) {
+	} else if (type == TW($neg)) {
 		return 4;
-	} else if (type == ID($demux)) {
+	} else if (type == TW($demux)) {
 		return 2;
-	} else if (type == ID($fa)) {
+	} else if (type == TW($fa)) {
 		return 5;
-	} else if (type.in(ID($add), ID($sub), ID($alu))) {
+	} else if (type.in(TW($add), TW($sub), TW($alu))) {
 		// multi-bit adders
 		return 8;
-	} else if (type.in(ID($shl), ID($sshl))) {
+	} else if (type.in(TW($shl), TW($sshl))) {
 		// left shift
 		return 10;
 	}
@@ -50,19 +50,19 @@ static unsigned int max_inp_coef(TwineRef type)
 {
 	if (
 	  // binop reduce
-	  type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)) ||
+	  type.in(TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool)) ||
 	  // others
-	  type.in(ID($logic_not), ID($pmux), ID($bmux))) {
+	  type.in(TW($logic_not), TW($pmux), TW($bmux))) {
 		return 1;
 	} else if (
 	  // equality
-	  type.in(ID($eq), ID($ne)) ||
+	  type.in(TW($eq), TW($ne)) ||
 	  // logic
-	  type.in(ID($logic_and), ID($logic_or))) {
+	  type.in(TW($logic_and), TW($logic_or))) {
 		return 2;
-	} else if (type == ID($lcu)) {
+	} else if (type == TW($lcu)) {
 		return 5;
-	} else if (type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
+	} else if (type.in(TW($lt), TW($le), TW($ge), TW($gt))) {
 		// comparison
 		return 7;
 	}
@@ -71,10 +71,10 @@ static unsigned int max_inp_coef(TwineRef type)
 
 static unsigned int sum_coef(TwineRef type)
 {
-	if (type.in(ID($shr), ID($sshr))) {
+	if (type.in(TW($shr), TW($sshr))) {
 		// right shift
 		return 4;
-	} else if (type.in(ID($shift), ID($shiftx))) {
+	} else if (type.in(TW($shift), TW($shiftx))) {
 		// shift
 		return 8;
 	}
@@ -83,23 +83,23 @@ static unsigned int sum_coef(TwineRef type)
 
 static unsigned int is_div_mod(TwineRef type)
 {
-	return (type == ID($div) || type == ID($divfloor) || type == ID($mod) || type == ID($modfloor));
+	return (type == TW($div) || type == TW($divfloor) || type == TW($mod) || type == TW($modfloor));
 }
 
 static bool is_free(TwineRef type)
 {
 	return (
 	  // tags
-	  type.in(ID($overwrite_tag), ID($set_tag), ID($original_tag), ID($get_tag)) ||
+	  type.in(TW($overwrite_tag), TW($set_tag), TW($original_tag), TW($get_tag)) ||
 	  // formal
-	  type.in(ID($check), ID($equiv), ID($initstate), ID($assert), ID($assume), ID($live), ID($cover), ID($fair)) ||
-	  type.in(ID($allseq), ID($allconst), ID($anyseq), ID($anyconst), ID($anyinit)) ||
+	  type.in(TW($check), TW($equiv), TW($initstate), TW($assert), TW($assume), TW($live), TW($cover), TW($fair)) ||
+	  type.in(TW($allseq), TW($allconst), TW($anyseq), TW($anyconst), TW($anyinit)) ||
 	  // utilities
-	  type.in(ID($scopeinfo), ID($print)) ||
+	  type.in(TW($scopeinfo), TW($print)) ||
 	  // real but free
-	  type.in(ID($concat), ID($slice), ID($pos)) ||
+	  type.in(TW($concat), TW($slice), TW($pos)) ||
 	  // specify
-	  type.in(ID($specrule), ID($specify2), ID($specify3)));
+	  type.in(TW($specrule), TW($specify2), TW($specify3)));
 }
 
 unsigned int max_inp_width(RTLIL::Cell *cell)
@@ -112,7 +112,7 @@ unsigned int max_inp_width(RTLIL::Cell *cell)
 	  ID::S_WIDTH,
 	};
 
-	if (cell->type == ID($bmux))
+	if (cell->type == TW($bmux))
 		return cell->getParam(ID::WIDTH).as_int() << cell->getParam(ID::S_WIDTH).as_int();
 
 	for (RTLIL::IdString param : input_width_params)
@@ -139,7 +139,7 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
 {
 
 	// simple 1-bit cells
-	if (cmos_gate_cost().count(cell->type))
+	if (cmos_gate_cost().count(cell->type_impl))
 		return 1;
 
 	if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
@@ -149,35 +149,35 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
 		log_assert(cell->hasPort(TW::Q) && "Weird flip flop");
 		log_debug("%s is ff\n", cell->name);
 		return cell->getParam(ID::WIDTH).as_int();
-	} else if (cell->type.in(ID($mem), ID($mem_v2))) {
+	} else if (cell->type.in(TW($mem), TW($mem_v2))) {
 		log_debug("%s is mem\n", cell->name);
 		return cell->getParam(ID::WIDTH).as_int() * cell->getParam(ID::SIZE).as_int();
-	} else if (y_coef(cell->type)) {
+	} else if (y_coef(cell->type.ref())) {
 		// linear with Y_WIDTH or WIDTH
 		log_assert((cell->hasParam(ID::Y_WIDTH) || cell->hasParam(ID::WIDTH)) && "Unknown width");
 		auto param = cell->hasParam(ID::Y_WIDTH) ? ID::Y_WIDTH : ID::WIDTH;
 		int width = cell->getParam(param).as_int();
-		if (cell->type == ID($demux))
+		if (cell->type == TW($demux))
 			width <<= cell->getParam(ID::S_WIDTH).as_int();
-		log_debug("%s Y*coef %d * %d\n", cell->name, width, y_coef(cell->type));
-		return width * y_coef(cell->type);
-	} else if (sum_coef(cell->type)) {
+		log_debug("%s Y*coef %d * %d\n", cell->name, width, y_coef(cell->type.ref()));
+		return width * y_coef(cell->type.ref());
+	} else if (sum_coef(cell->type.ref())) {
 		// linear with sum of port widths
 		unsigned int sum = port_width_sum(cell);
-		log_debug("%s sum*coef %d * %d\n", cell->name, sum, sum_coef(cell->type));
-		return sum * sum_coef(cell->type);
-	} else if (max_inp_coef(cell->type)) {
+		log_debug("%s sum*coef %d * %d\n", cell->name, sum, sum_coef(cell->type.ref()));
+		return sum * sum_coef(cell->type.ref());
+	} else if (max_inp_coef(cell->type.ref())) {
 		// linear with largest input width
 		unsigned int max = max_inp_width(cell);
-		log_debug("%s max*coef %d * %d\n", cell->name, max, max_inp_coef(cell->type));
-		return max * max_inp_coef(cell->type);
-	} else if (is_div_mod(cell->type) || cell->type == ID($mul)) {
+		log_debug("%s max*coef %d * %d\n", cell->name, max, max_inp_coef(cell->type.ref()));
+		return max * max_inp_coef(cell->type.ref());
+	} else if (is_div_mod(cell->type.ref()) || cell->type == TW($mul)) {
 		// quadratic with sum of port widths
 		unsigned int sum = port_width_sum(cell);
-		unsigned int coef = cell->type == ID($mul) ? 3 : 5;
+		unsigned int coef = cell->type == TW($mul) ? 3 : 5;
 		log_debug("%s coef*(sum**2) %d * %d\n", cell->name, coef, sum * sum);
 		return coef * sum * sum;
-	} else if (cell->type.in(ID($macc), ID($macc_v2))) {
+	} else if (cell->type.in(TW($macc), TW($macc_v2))) {
 		// quadratic per term
 		unsigned int cost_sum = 0;
 		Macc macc;
@@ -193,17 +193,17 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
 			cost_sum += 3 * sum * sum;
 		}
 		return cost_sum;
-	} else if (cell->type == ID($lut)) {
+	} else if (cell->type == TW($lut)) {
 		int width = cell->getParam(ID::WIDTH).as_int();
 		unsigned int cost = 1U << (unsigned int)width;
 		log_debug("%s is 2**%d\n", cell->name, width);
 		return cost;
-	} else if (cell->type == ID($sop)) {
+	} else if (cell->type == TW($sop)) {
 		int width = cell->getParam(ID::WIDTH).as_int();
 		int depth = cell->getParam(ID::DEPTH).as_int();
 		log_debug("%s is (2*%d + 1)*%d\n", cell->name, width, depth);
 		return (2 * width + 1) * depth;
-	} else if (is_free(cell->type)) {
+	} else if (is_free(cell->type.ref())) {
 		log_debug("%s is free\n", cell->name);
 		return 0;
 	}
diff --git a/kernel/cost.h b/kernel/cost.h
index 3c709be30..417bb1130 100644
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -34,52 +34,52 @@ struct CellCosts
 	public:
 	CellCosts(RTLIL::Design *design) : design_(design) { }
 
-	static const dict<RTLIL::IdString, int>& default_gate_cost() {
+	static const dict<TwineRef, int>& default_gate_cost() {
 		// Default size heuristics for several common PDK standard cells
 		// used by abc and stat
-		static const dict<RTLIL::IdString, int> db = {
-			{ ID($_BUF_),    1 },
-			{ ID($_NOT_),    2 },
-			{ ID($_AND_),    4 },
-			{ ID($_NAND_),   4 },
-			{ ID($_OR_),     4 },
-			{ ID($_NOR_),    4 },
-			{ ID($_ANDNOT_), 4 },
-			{ ID($_ORNOT_),  4 },
-			{ ID($_XOR_),    5 },
-			{ ID($_XNOR_),   5 },
-			{ ID($_AOI3_),   6 },
-			{ ID($_OAI3_),   6 },
-			{ ID($_AOI4_),   7 },
-			{ ID($_OAI4_),   7 },
-			{ ID($_MUX_),    4 },
-			{ ID($_NMUX_),   4 },
+		static const dict<TwineRef, int> db = {
+			{ TW($_BUF_),    1 },
+			{ TW($_NOT_),    2 },
+			{ TW($_AND_),    4 },
+			{ TW($_NAND_),   4 },
+			{ TW($_OR_),     4 },
+			{ TW($_NOR_),    4 },
+			{ TW($_ANDNOT_), 4 },
+			{ TW($_ORNOT_),  4 },
+			{ TW($_XOR_),    5 },
+			{ TW($_XNOR_),   5 },
+			{ TW($_AOI3_),   6 },
+			{ TW($_OAI3_),   6 },
+			{ TW($_AOI4_),   7 },
+			{ TW($_OAI4_),   7 },
+			{ TW($_MUX_),    4 },
+			{ TW($_NMUX_),   4 },
 		};
 		return db;
 	}
 
-	static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
+	static const dict<TwineRef, int>& cmos_gate_cost() {
 		// Estimated CMOS transistor counts for several common PDK standard cells
 		// used by stat and optionally by abc
-		static const dict<RTLIL::IdString, int> db = {
-			{ ID($_BUF_),     1 },
-			{ ID($_NOT_),     2 },
-			{ ID($_AND_),     6 },
-			{ ID($_NAND_),    4 },
-			{ ID($_OR_),      6 },
-			{ ID($_NOR_),     4 },
-			{ ID($_ANDNOT_),  6 },
-			{ ID($_ORNOT_),   6 },
-			{ ID($_XOR_),    12 },
-			{ ID($_XNOR_),   12 },
-			{ ID($_AOI3_),    6 },
-			{ ID($_OAI3_),    6 },
-			{ ID($_AOI4_),    8 },
-			{ ID($_OAI4_),    8 },
-			{ ID($_MUX_),    12 },
-			{ ID($_NMUX_),   10 },
-			{ ID($_DFF_P_),  16 },
-			{ ID($_DFF_N_),  16 },
+		static const dict<TwineRef, int> db = {
+			{ TW($_BUF_),     1 },
+			{ TW($_NOT_),     2 },
+			{ TW($_AND_),     6 },
+			{ TW($_NAND_),    4 },
+			{ TW($_OR_),      6 },
+			{ TW($_NOR_),     4 },
+			{ TW($_ANDNOT_),  6 },
+			{ TW($_ORNOT_),   6 },
+			{ TW($_XOR_),    12 },
+			{ TW($_XNOR_),   12 },
+			{ TW($_AOI3_),    6 },
+			{ TW($_OAI3_),    6 },
+			{ TW($_AOI4_),    8 },
+			{ TW($_OAI4_),    8 },
+			{ TW($_MUX_),    12 },
+			{ TW($_NMUX_),   10 },
+			{ TW($_DFF_P_),  16 },
+			{ TW($_DFF_N_),  16 },
 		};
 		return db;
 	}
diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc
index 6c2faa0c1..aa34bf731 100644
--- a/kernel/drivertools.cc
+++ b/kernel/drivertools.cc
@@ -537,8 +537,8 @@ DriverMap::BitMode DriverMap::bit_mode(DriveBit const &bit)
 		}
 		case DriveType::PORT: {
 			auto const &port = bit.port();
-			bool driver = celltypes.cell_output(port.cell->type, port.port);
-			bool driven = celltypes.cell_input(port.cell->type, port.port);
+			bool driver = celltypes.cell_output(port.cell->type.ref(), port.port);
+			bool driven = celltypes.cell_input(port.cell->type.ref(), port.port);
 			if (driver && !driven)
 				return BitMode::DRIVER;
 			else if (driven && !driver)
@@ -866,7 +866,7 @@ DriveSpec DriverMap::operator()(DriveSpec spec)
 
 std::string log_signal(DriveChunkWire const &chunk)
 {
-	std::string id = chunk.wire->name.unescape();
+	std::string id = design->twines.unescaped_str(chunk.wire->name);
 	if (chunk.is_whole())
 		return id;
 	if (chunk.width == 1)
diff --git a/kernel/ff.cc b/kernel/ff.cc
index 0a14c59d1..f7a0fbc80 100644
--- a/kernel/ff.cc
+++ b/kernel/ff.cc
@@ -54,19 +54,19 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
 
 	std::string type_str = type.str();
 
-	if (type.in(ID($anyinit), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
-		if (type.in(ID($anyinit), ID($ff))) {
+	if (type.in(TW($anyinit), TW($ff), TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($sdff), TW($sdffe), TW($sdffce), TW($dlatch), TW($adlatch), TW($dlatchsr), TW($sr))) {
+		if (type.in(TW($anyinit), TW($ff))) {
 			info.has_gclk = true;
 			if constexpr (have_cell)
 				info.sig_d = cell->getPort(TW::D);
-			if (type == ID($anyinit)) {
+			if (type == TW($anyinit)) {
 				info.is_anyinit = true;
 				if constexpr (have_cell)
 					log_assert(info.val_init.is_fully_undef());
 			}
-		} else if (type == ID($sr)) {
+		} else if (type == TW($sr)) {
 			// No data input at all.
-		} else if (type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
+		} else if (type.in(TW($dlatch), TW($adlatch), TW($dlatchsr))) {
 			info.has_aload = true;
 			if constexpr (have_cell) {
 				info.sig_aload = cell->getPort(TW::EN);
@@ -81,14 +81,14 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
 				info.sig_d = cell->getPort(TW::D);
 			}
 		}
-		if (type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
+		if (type.in(TW($dffe), TW($dffsre), TW($adffe), TW($aldffe), TW($sdffe), TW($sdffce))) {
 			info.has_ce = true;
 			if constexpr (have_cell) {
 				info.sig_ce = cell->getPort(TW::EN);
 				info.pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
 			}
 		}
-		if (type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
+		if (type.in(TW($dffsr), TW($dffsre), TW($dlatchsr), TW($sr))) {
 			info.has_sr = true;
 			if constexpr (have_cell) {
 				info.sig_clr = cell->getPort(TW::CLR);
@@ -97,7 +97,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
 				info.pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
 			}
 		}
-		if (type.in(ID($aldff), ID($aldffe))) {
+		if (type.in(TW($aldff), TW($aldffe))) {
 			info.has_aload = true;
 			if constexpr (have_cell) {
 				info.sig_aload = cell->getPort(TW::ALOAD);
@@ -105,7 +105,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
 				info.sig_ad = cell->getPort(TW::AD);
 			}
 		}
-		if (type.in(ID($adff), ID($adffe), ID($adlatch))) {
+		if (type.in(TW($adff), TW($adffe), TW($adlatch))) {
 			info.has_arst = true;
 			if constexpr (have_cell) {
 				info.sig_arst = cell->getPort(TW::ARST);
@@ -113,16 +113,16 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
 				info.val_arst = cell->getParam(ID::ARST_VALUE);
 			}
 		}
-		if (type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
+		if (type.in(TW($sdff), TW($sdffe), TW($sdffce))) {
 			info.has_srst = true;
 			if constexpr (have_cell) {
 				info.sig_srst = cell->getPort(TW::SRST);
 				info.pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
 				info.val_srst = cell->getParam(ID::SRST_VALUE);
 			}
-			info.ce_over_srst = type == ID($sdffce);
+			info.ce_over_srst = type == TW($sdffce);
 		}
-	} else if (type == ID($_FF_)) {
+	} else if (type == TW($_FF_)) {
 		info.is_fine = true;
 		info.has_gclk = true;
 		if constexpr (have_cell)
@@ -815,7 +815,7 @@ void FfData::flip_bits(const pool<int> &bits) {
 	Wire *new_q = module->addWire(NEW_TWINE, width);
 
 	if (has_sr && cell) {
-		log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->design->twines.str(module->meta_->name).c_str(), cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
+		log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->design->twines.str(module->meta_->name).c_str(), cell->name, cell->type.unescape());
 	}
 
 	if (is_fine) {
diff --git a/kernel/functional.cc b/kernel/functional.cc
index 535e98134..590b1d6ee 100644
--- a/kernel/functional.cc
+++ b/kernel/functional.cc
@@ -67,7 +67,7 @@ const char *fn_to_string(Fn fn) {
 	log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn);
 }
 
-vector<IRInput const*> IR::inputs(IdString kind) const {
+vector<IRInput const*> IR::inputs(TwineRef kind) const {
 	vector<IRInput const*> ret;
 	for (const auto &[name, input] : _inputs)
 		if(input.kind == kind)
@@ -75,7 +75,7 @@ vector<IRInput const*> IR::inputs(IdString kind) const {
 	return ret;
 }
 
-vector<IROutput const*> IR::outputs(IdString kind) const {
+vector<IROutput const*> IR::outputs(TwineRef kind) const {
 	vector<IROutput const*> ret;
 	for (const auto &[name, output] : _outputs)
 		if(output.kind == kind)
@@ -83,7 +83,7 @@ vector<IROutput const*> IR::outputs(IdString kind) const {
 	return ret;
 }
 
-vector<IRState const*> IR::states(IdString kind) const {
+vector<IRState const*> IR::states(TwineRef kind) const {
 	vector<IRState const*> ret;
 	for (const auto &[name, state] : _states)
 		if(state.kind == kind)
@@ -136,7 +136,7 @@ struct PrintVisitor : DefaultVisitor<std::string> {
 
 std::string Node::to_string()
 {
-	return to_string([](Node n) { return n.name().unescape(); });
+	return to_string([](Node n) { return design->twines.unescaped_str(n.name()); });
 }
 
 std::string Node::to_string(std::function<std::string(Node)> np)
@@ -253,87 +253,87 @@ public:
 		int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int();
 		bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool();
 		bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool();
-		if(cellType.in(ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul))){
+		if(cellType.in(TW($add), TW($sub), TW($and), TW($or), TW($xor), TW($xnor), TW($mul))){
 			bool is_signed = a_signed && b_signed;
 			Node a = factory.extend(inputs.at(TW::A), y_width, is_signed);
 			Node b = factory.extend(inputs.at(TW::B), y_width, is_signed);
-			if(cellType == ID($add))
+			if(cellType == TW($add))
 				return factory.add(a, b);
-			else if(cellType == ID($sub))
+			else if(cellType == TW($sub))
 				return factory.sub(a, b);
-			else if(cellType == ID($mul))
+			else if(cellType == TW($mul))
 				return factory.mul(a, b);
-			else if(cellType == ID($and))
+			else if(cellType == TW($and))
 				return factory.bitwise_and(a, b);
-			else if(cellType == ID($or))
+			else if(cellType == TW($or))
 				return factory.bitwise_or(a, b);
-			else if(cellType == ID($xor))
+			else if(cellType == TW($xor))
 				return factory.bitwise_xor(a, b);
-			else if(cellType == ID($xnor))
+			else if(cellType == TW($xnor))
 				return factory.bitwise_not(factory.bitwise_xor(a, b));
 			else
 				log_abort();
-		}else if(cellType.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt))){
+		}else if(cellType.in(TW($eq), TW($ne), TW($eqx), TW($nex), TW($le), TW($lt), TW($ge), TW($gt))){
 			bool is_signed = a_signed && b_signed;
 			int width = max(a_width, b_width);
 			Node a = factory.extend(inputs.at(TW::A), width, is_signed);
 			Node b = factory.extend(inputs.at(TW::B), width, is_signed);
-			if(cellType.in(ID($eq), ID($eqx)))
+			if(cellType.in(TW($eq), TW($eqx)))
 				return factory.extend(factory.equal(a, b), y_width, false);
-			else if(cellType.in(ID($ne), ID($nex)))
+			else if(cellType.in(TW($ne), TW($nex)))
 				return factory.extend(factory.not_equal(a, b), y_width, false);
-			else if(cellType == ID($lt))
+			else if(cellType == TW($lt))
 				return factory.extend(is_signed ? factory.signed_greater_than(b, a) : factory.unsigned_greater_than(b, a), y_width, false);
-			else if(cellType == ID($le))
+			else if(cellType == TW($le))
 				return factory.extend(is_signed ? factory.signed_greater_equal(b, a) : factory.unsigned_greater_equal(b, a), y_width, false);
-			else if(cellType == ID($gt))
+			else if(cellType == TW($gt))
 				return factory.extend(is_signed ? factory.signed_greater_than(a, b) : factory.unsigned_greater_than(a, b), y_width, false);
-			else if(cellType == ID($ge))
+			else if(cellType == TW($ge))
 				return factory.extend(is_signed ? factory.signed_greater_equal(a, b) : factory.unsigned_greater_equal(a, b), y_width, false);
 			else
 				log_abort();
-		}else if(cellType.in(ID($logic_or), ID($logic_and))){
+		}else if(cellType.in(TW($logic_or), TW($logic_and))){
 			Node a = factory.reduce_or(inputs.at(TW::A));
 			Node b = factory.reduce_or(inputs.at(TW::B));
-			Node y = cellType == ID($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b);
+			Node y = cellType == TW($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b);
 			return factory.extend(y, y_width, false);
-		}else if(cellType == ID($not)){
+		}else if(cellType == TW($not)){
 			Node a = factory.extend(inputs.at(TW::A), y_width, a_signed);
 			return factory.bitwise_not(a);
-		}else if(cellType == ID($pos)){
+		}else if(cellType == TW($pos)){
 			return factory.extend(inputs.at(TW::A), y_width, a_signed);
-		}else if(cellType == ID($neg)){
+		}else if(cellType == TW($neg)){
 			Node a = factory.extend(inputs.at(TW::A), y_width, a_signed);
 			return factory.unary_minus(a);
-		}else if(cellType == ID($logic_not)){
+		}else if(cellType == TW($logic_not)){
 			Node a = factory.reduce_or(inputs.at(TW::A));
 			Node y = factory.bitwise_not(a);
 			return factory.extend(y, y_width, false);
-		}else if(cellType.in(ID($reduce_or), ID($reduce_bool))){
+		}else if(cellType.in(TW($reduce_or), TW($reduce_bool))){
 			Node a = factory.reduce_or(inputs.at(TW::A));
 			return factory.extend(a, y_width, false);
-		}else if(cellType == ID($reduce_and)){
+		}else if(cellType == TW($reduce_and)){
 			Node a = factory.reduce_and(inputs.at(TW::A));
 			return factory.extend(a, y_width, false);
-		}else if(cellType.in(ID($reduce_xor), ID($reduce_xnor))){
+		}else if(cellType.in(TW($reduce_xor), TW($reduce_xnor))){
 			Node a = factory.reduce_xor(inputs.at(TW::A));
-			Node y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a) : a;
+			Node y = cellType == TW($reduce_xnor) ? factory.bitwise_not(a) : a;
 			return factory.extend(y, y_width, false);
-		}else if(cellType == ID($shl) || cellType == ID($sshl)){
+		}else if(cellType == TW($shl) || cellType == TW($sshl)){
 			Node a = factory.extend(inputs.at(TW::A), y_width, a_signed);
 			Node b = inputs.at(TW::B);
 			return logical_shift_left(a, b);
-		}else if(cellType == ID($shr) || cellType == ID($sshr)){
+		}else if(cellType == TW($shr) || cellType == TW($sshr)){
 			int width = max(a_width, y_width);
 			Node a = factory.extend(inputs.at(TW::A), width, a_signed);
 			Node b = inputs.at(TW::B);
-			Node y = a_signed && cellType == ID($sshr) ?
+			Node y = a_signed && cellType == TW($sshr) ?
 				arithmetic_shift_right(a, b) :
 				logical_shift_right(a, b);
 			return factory.extend(y, y_width, a_signed);
-		}else if(cellType == ID($shiftx) || cellType == ID($shift)){
+		}else if(cellType == TW($shiftx) || cellType == TW($shift)){
 			int width = max(a_width, y_width);
-			Node a = factory.extend(inputs.at(TW::A), width, cellType == ID($shift) && a_signed);
+			Node a = factory.extend(inputs.at(TW::A), width, cellType == TW($shift) && a_signed);
 			Node b = inputs.at(TW::B);
 			Node shr = logical_shift_right(a, b);
 			if(b_signed) {
@@ -343,35 +343,35 @@ public:
 			} else {
 				return factory.extend(shr, y_width, false);
 			}
-		}else if(cellType == ID($mux)){
+		}else if(cellType == TW($mux)){
 			return factory.mux(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::S));
-		}else if(cellType == ID($pmux)){
+		}else if(cellType == TW($pmux)){
 			return handle_pmux(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::S));
-		}else if(cellType == ID($concat)){
+		}else if(cellType == TW($concat)){
 			Node a = inputs.at(TW::A);
 			Node b = inputs.at(TW::B);
 			return factory.concat(a, b);
-		}else if(cellType == ID($slice)){
+		}else if(cellType == TW($slice)){
 			int offset = parameters.at(ID(OFFSET)).as_int();
 			Node a = inputs.at(TW::A);
 			return factory.slice(a, offset, y_width);
-		}else if(cellType.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+		}else if(cellType.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 			int width = max(a_width, b_width);
 			bool is_signed = a_signed && b_signed;
 			Node a = factory.extend(inputs.at(TW::A), width, is_signed);
 			Node b = factory.extend(inputs.at(TW::B), width, is_signed);
 			if(is_signed) {
-				if(cellType == ID($div)) {
+				if(cellType == TW($div)) {
 					// divide absolute values, then flip the sign if input signs differ
 					// but extend the width first, to handle the case (most negative value) / (-1)
 					Node abs_y = factory.unsigned_div(abs(a), abs(b));
 					Node out_sign = factory.not_equal(sign(a), sign(b));
 					return neg_if(factory.extend(abs_y, y_width, false), out_sign);
-				} else if(cellType == ID($mod)) {
+				} else if(cellType == TW($mod)) {
 					// similar to division but output sign == divisor sign
 					Node abs_y = factory.unsigned_mod(abs(a), abs(b));
 					return neg_if(factory.extend(abs_y, y_width, false), sign(a));
-				} else if(cellType == ID($divfloor)) {
+				} else if(cellType == TW($divfloor)) {
 					// if b is negative, flip both signs so that b is positive
 					Node b_sign = sign(b);
 					Node a1 = neg_if(a, b_sign);
@@ -385,7 +385,7 @@ public:
 					Node y1 = factory.unsigned_div(a2, b1);
 					Node y2 = factory.extend(y1, y_width, false);
 					return factory.mux(y2, factory.bitwise_not(y2), a1_sign);
-				} else if(cellType == ID($modfloor)) {
+				} else if(cellType == TW($modfloor)) {
 					// calculate |a| % |b| and then subtract from |b| if input signs differ and the remainder is non-zero
 					Node abs_b = abs(b);
 					Node abs_y = factory.unsigned_mod(abs(a), abs_b);
@@ -397,34 +397,34 @@ public:
 				} else
 					log_error("unhandled cell in CellSimplifier %s\n", cellType);
 			} else {
-				if(cellType.in(ID($mod), ID($modfloor)))
+				if(cellType.in(TW($mod), TW($modfloor)))
 					return factory.extend(factory.unsigned_mod(a, b), y_width, false);
 				else
 					return factory.extend(factory.unsigned_div(a, b), y_width, false);
 			}
-		} else if(cellType == ID($pow)) {
+		} else if(cellType == TW($pow)) {
 			return handle_pow(inputs.at(TW::A), inputs.at(TW::B), y_width, a_signed && b_signed);
-		} else if (cellType == ID($lut)) {
+		} else if (cellType == TW($lut)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			Const lut_table = parameters.at(ID(LUT));
 			lut_table.extu(1 << width);
 			return handle_bmux(factory.constant(lut_table), inputs.at(TW::A), 0, 1, width);
-		} else if (cellType == ID($bwmux)) {
+		} else if (cellType == TW($bwmux)) {
 			Node a = inputs.at(TW::A);
 			Node b = inputs.at(TW::B);
 			Node s = inputs.at(TW::S);
 			return factory.bitwise_or(
 				factory.bitwise_and(a, factory.bitwise_not(s)),
 				factory.bitwise_and(b, s));
-		} else if (cellType == ID($bweqx)) {
+		} else if (cellType == TW($bweqx)) {
 			Node a = inputs.at(TW::A);
 			Node b = inputs.at(TW::B);
 			return factory.bitwise_not(factory.bitwise_xor(a, b));
-		} else if(cellType == ID($bmux)) {
+		} else if(cellType == TW($bmux)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			int s_width = parameters.at(ID(S_WIDTH)).as_int();
 			return handle_bmux(inputs.at(TW::A), inputs.at(TW::S), 0, width, s_width);
-		} else if(cellType == ID($demux)) {
+		} else if(cellType == TW($demux)) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			int s_width = parameters.at(ID(S_WIDTH)).as_int();
 			int y_width = width << s_width;
@@ -433,31 +433,31 @@ public:
 			Node s = factory.extend(inputs.at(TW::S), b_width, false);
 			Node b = factory.mul(s, factory.constant(Const(width, b_width)));
 			return factory.logical_shift_left(a, b);
-		} else if(cellType == ID($fa)) {
+		} else if(cellType == TW($fa)) {
 			return handle_fa(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::C));
-		} else if(cellType == ID($lcu)) {
+		} else if(cellType == TW($lcu)) {
 			return handle_lcu(inputs.at(TW::P), inputs.at(TW::G), inputs.at(TW::CI));
-		} else if(cellType == ID($alu)) {
+		} else if(cellType == TW($alu)) {
 			return handle_alu(inputs.at(TW::A), inputs.at(TW::B), y_width, a_signed && b_signed, inputs.at(TW::CI), inputs.at(TW::BI));
-		} else if(cellType.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
+		} else if(cellType.in(TW($assert), TW($assume), TW($live), TW($fair), TW($cover))) {
 			Node a = factory.mux(factory.constant(Const(State::S1, 1)), inputs.at(TW::A), inputs.at(TW::EN));
 			auto &output = factory.add_output(cellName, cellType, Sort(1));
 			output.set_value(a);
 			return {};
-		} else if(cellType.in(ID($anyconst), ID($allconst), ID($anyseq), ID($allseq))) {
+		} else if(cellType.in(TW($anyconst), TW($allconst), TW($anyseq), TW($allseq))) {
 			int width = parameters.at(ID(WIDTH)).as_int();
 			auto &input = factory.add_input(cellName, cellType, Sort(width));
 			return factory.value(input);
-		} else if(cellType == ID($initstate)) {
-			if(factory.ir().has_state(ID($initstate), ID($state)))
-				return factory.value(factory.ir().state(ID($initstate)));
+		} else if(cellType == TW($initstate)) {
+			if(factory.ir().has_state(TW($initstate), TW($state)))
+				return factory.value(factory.ir().state(TW($initstate)));
 			else {
-				auto &state = factory.add_state(ID($initstate), ID($state), Sort(1));
+				auto &state = factory.add_state(TW($initstate), TW($state), Sort(1));
 				state.set_initial_value(RTLIL::Const(State::S1, 1));
 				state.set_next_value(factory.constant(RTLIL::Const(State::S0, 1)));
 				return factory.value(state);
 			}
-		} else if(cellType == ID($check)) {
+		} else if(cellType == TW($check)) {
 			log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName);
 		} else {
 			log_error("`%s' cells are not supported by the functional backend\n", cellType);
@@ -495,7 +495,7 @@ class FunctionalIRConstruction {
 			queue.emplace_back(cell);
 			std::optional<Node> rv;
 			for(auto const &[name, sigspec] : cell->connections())
-				if(driver_map.celltypes.cell_output(cell->type, name)) {
+				if(driver_map.celltypes.cell_output(cell->type.ref(), name)) {
 					auto node = factory.create_pending(sigspec.size());
 					factory.suggest_name(node, cell->name.str() + "$" + cell->module->design->twines.str(name));
 					cell_outputs.emplace({cell, name}, node);
@@ -515,17 +515,17 @@ public:
 	{
 		driver_map.add(module);
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($check)))
+			if (cell->type.in(TW($assert), TW($assume), TW($live), TW($fair), TW($cover), TW($check)))
 				queue.emplace_back(cell);
 		}
 		// we are relying here on unsorted pools iterating last-in-first-out
 		for (auto riter = module->ports.rbegin(); riter != module->ports.rend(); ++riter) {
 			auto *wire = module->wire(*riter);
 			if (wire && wire->port_input) {
-				factory.add_input(wire->name, ID($input), Sort(wire->width));
+				factory.add_input(wire->name, TW($input), Sort(wire->width));
 			}
 			if (wire && wire->port_output) {
-				auto &output = factory.add_output(wire->name, ID($output), Sort(wire->width));
+				auto &output = factory.add_output(wire->name, TW($output), Sort(wire->width));
 				output.set_value(enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))));
 			}
 		}
@@ -565,14 +565,14 @@ private:
 		// - Since wr port j can only have priority over wr port i if j > i, if we do writes in
 		//   ascending index order the result will obey the priorty relation.
 		vector<Node> read_results;
-		auto &state = factory.add_state(mem->cell->name, ID($state), Sort(ceil_log2(mem->size), mem->width));
+		auto &state = factory.add_state(mem->cell->name, TW($state), Sort(ceil_log2(mem->size), mem->width));
 		state.set_initial_value(MemContents(mem));
 		Node node = factory.value(state);
 		for (size_t i = 0; i < mem->wr_ports.size(); i++) {
 			const auto &wr = mem->wr_ports[i];
 			if (wr.clk_enable)
 				log_error("Write port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
-					"Call async2sync or clk2fflogic to avoid this error.\n", i, mem->module, mem->memid.unescape());
+					"Call async2sync or clk2fflogic to avoid this error.\n", i, mem->module, design->twines.unescaped_str(mem->memid));
 			Node en = enqueue(driver_map(DriveSpec(wr.en)));
 			Node addr = enqueue(driver_map(DriveSpec(wr.addr)));
 			Node new_data = enqueue(driver_map(DriveSpec(wr.data)));
@@ -582,12 +582,12 @@ private:
 		}
 		if (mem->rd_ports.empty())
 			log_error("Memory %s.%s has no read ports. This is not supported by the functional backend. "
-				"Call opt_clean to remove it.", mem->module, mem->memid.unescape());
+				"Call opt_clean to remove it.", mem->module, design->twines.unescaped_str(mem->memid));
 		for (size_t i = 0; i < mem->rd_ports.size(); i++) {
 			const auto &rd = mem->rd_ports[i];
 			if (rd.clk_enable)
 				log_error("Read port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
-					"Call memory_nordff to avoid this error.\n", i, mem->module, mem->memid.unescape());
+					"Call memory_nordff to avoid this error.\n", i, mem->module, design->twines.unescaped_str(mem->memid));
 			Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
 			read_results.push_back(factory.memory_read(node, addr));
 		}
@@ -609,8 +609,8 @@ private:
 			FfData ff(&ff_initvals, cell);
 			if (!ff.has_gclk)
 				log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
-					"Call async2sync or clk2fflogic to avoid this error.\n", cell->type.unescape(), cell);
-			auto &state = factory.add_state(ff.name, ID($state), Sort(ff.width));
+					"Call async2sync or clk2fflogic to avoid this error.\n", cell->type.unescaped(), cell);
+			auto &state = factory.add_state(ff.name, TW($state), Sort(ff.width));
 			Node q_value = factory.value(state);
 			factory.suggest_name(q_value, ff.name);
 			factory.update_pending(cell_outputs.at({cell, TW::Q}), q_value);
@@ -621,9 +621,9 @@ private:
 			TwineRef output_name; // for the single output case
 			int n_outputs = 0;
 			for(auto const &[name, sigspec] : cell->connections()) {
-				if(driver_map.celltypes.cell_input(cell->type, name) && sigspec.size() > 0)
+				if(driver_map.celltypes.cell_input(cell->type.ref(), name) && sigspec.size() > 0)
 					connections.insert({ name, enqueue(DriveChunkPort(cell, {name, sigspec})) });
-				if(driver_map.celltypes.cell_output(cell->type, name)) {
+				if(driver_map.celltypes.cell_output(cell->type.ref(), name)) {
 					output_name = name;
 					n_outputs++;
 				}
@@ -677,7 +677,7 @@ public:
 							factory.update_pending(pending, node);
 						} else {
 							DriveSpec driver = driver_map(DriveSpec(wire_chunk));
-							check_undriven(driver, wire_chunk.wire->name.unescape());
+							check_undriven(driver, design->twines.unescaped_str(wire_chunk.wire->name));
 							Node node = enqueue(driver);
 							factory.suggest_name(node, wire_chunk.wire->name);
 							factory.update_pending(pending, node);
@@ -690,7 +690,7 @@ public:
 				} else if (chunk.is_port()) {
 					DriveChunkPort port_chunk = chunk.port();
 					if (port_chunk.is_whole()) {
-						if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
+						if (driver_map.celltypes.cell_output(port_chunk.cell->type.ref(), port_chunk.port)) {
 							Node node = enqueue_cell(port_chunk.cell, port_chunk.port);
 							factory.update_pending(pending, node);
 						} else {
@@ -745,7 +745,7 @@ void IR::topological_sort() {
             log_warning("Combinational loop:\n");
             for (int *i = begin; i != end; ++i) {
 				Node node(_graph[*i]);
-                log("- %s = %s\n", node.name().unescape(), node.to_string());
+                log("- %s = %s\n", design->twines.unescaped_str(node.name()), node.to_string());
 			}
             log("\n");
             scc = true;
diff --git a/kernel/functional.h b/kernel/functional.h
index 3334f02c8..776b29205 100644
--- a/kernel/functional.h
+++ b/kernel/functional.h
@@ -1,645 +1,645 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
- *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
+// /*
+//  *  yosys -- Yosys Open SYnthesis Suite
+//  *
+//  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+//  *  Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC
+//  *
+//  *  Permission to use, copy, modify, and/or distribute this software for any
+//  *  purpose with or without fee is hereby granted, provided that the above
+//  *  copyright notice and this permission notice appear in all copies.
+//  *
+//  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+//  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+//  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+//  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+//  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+//  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+//  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+//  *
+//  */
 
-#ifndef FUNCTIONAL_H
-#define FUNCTIONAL_H
+// #ifndef FUNCTIONAL_H
+// #define FUNCTIONAL_H
 
-#include "kernel/yosys.h"
-#include "kernel/compute_graph.h"
-#include "kernel/drivertools.h"
-#include "kernel/mem.h"
-#include "kernel/utils.h"
+// #include "kernel/yosys.h"
+// #include "kernel/compute_graph.h"
+// #include "kernel/drivertools.h"
+// #include "kernel/mem.h"
+// #include "kernel/utils.h"
 
-USING_YOSYS_NAMESPACE
-YOSYS_NAMESPACE_BEGIN
+// USING_YOSYS_NAMESPACE
+// YOSYS_NAMESPACE_BEGIN
 
-namespace Functional {
-	// each function is documented with a short pseudocode declaration or definition
-	// standard C/Verilog operators are used to describe the result
-	// 
-	// the sorts used in this are:
-	// - bit[N]: a bitvector of N bits
-	//   bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend
-	//   but is meant to indicate how the value is interpreted
-	//   if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation
-	// - memory[N, M]: a memory with N address and M data bits
-	// - int: C++ int
-	// - Const[N]: yosys RTLIL::Const (with size() == N)
-	// - IdString: yosys IdString
-	// - any: used in documentation to indicate that the sort is unconstrained
-	//
-	// nodes in the functional backend are either of sort bit[N] or memory[N,M] (for some N, M: int)
-	// additionally, they can carry a constant of sort int, Const[N] or IdString
-	// each node has a 'sort' field that stores the sort of the node
-	// slice, zero_extend, sign_extend use the sort field to store out_width
-	enum class Fn {
-		// invalid() = known-invalid/shouldn't happen value
-		// TODO: maybe remove this and use e.g. std::optional instead?
-		invalid,
-		// buf(a: any): any = a
-		// no-op operation
-		// when constructing the compute graph we generate invalid buf() nodes as a placeholder
-		// and later insert the argument
-		buf,
-		// slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width]
-		// required: offset + out_width <= in_width
-		slice,
-		// zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended)
-		// required: out_width > in_width
-		zero_extend,
-		// sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended)
-		// required: out_width > in_width
-		sign_extend,
-		// concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax)
-		// concatenates two bitvectors, with a in the least significant position and b in the more significant position
-		concat,
-		// add(a: bit[N], b: bit[N]): bit[N] = a + b
-		add,
-		// sub(a: bit[N], b: bit[N]): bit[N] = a - b
-		sub,
-		// mul(a: bit[N], b: bit[N]): bit[N] = a * b
-		mul,
-		// unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b
-		unsigned_div,
-		// unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b
-		unsigned_mod,
-		// bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b
-		bitwise_and,
-		// bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b
-		bitwise_or,
-		// bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b
-		bitwise_xor,
-		// bitwise_not(a: bit[N]): bit[N] = ~a
-		bitwise_not,
-		// reduce_and(a: bit[N]): bit[1] = &a
-		reduce_and,
-		// reduce_or(a: bit[N]): bit[1] = |a
-		reduce_or,
-		// reduce_xor(a: bit[N]): bit[1] = ^a
-		reduce_xor,
-		// unary_minus(a: bit[N]): bit[N] = -a
-		unary_minus,
-		// equal(a: bit[N], b: bit[N]): bit[1] = (a == b)
-		equal,
-		// not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b)
-		not_equal,
-		// signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b)
-		signed_greater_than,
-		// signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b)
-		signed_greater_equal,
-		// unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b)
-		unsigned_greater_than,
-		// unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b)
-		unsigned_greater_equal,
-		// logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b
-		// required: M == clog2(N)
-		logical_shift_left,
-		// logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b
-		// required: M == clog2(N)
-		logical_shift_right,
-		// arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b
-		// required: M == clog2(N)
-		arithmetic_shift_right,
-		// mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a
-		mux,
-		// constant(a: Const[N]): bit[N] = a
-		constant,
-		// input(a: IdString): any
-		// returns the current value of the input with the specified name
-		input,
-		// state(a: IdString): any
-		// returns the current value of the state variable with the specified name
-		state,
-		// memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr]
-		memory_read,
-		// memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width]
-		// returns a copy of `memory` but with the value at `addr` changed to `data`
-		memory_write
-	};
-	// returns the name of a Fn value, as a string literal
-	const char *fn_to_string(Fn);
-	// Sort represents the sort or type of a node
-	// currently the only two sorts are signal/bit and memory
-	class Sort {
-		std::variant<int, std::pair<int, int>> _v;
-	public:
-		explicit Sort(int width) : _v(width) { }
-		Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { }
-		bool is_signal() const { return _v.index() == 0; }
-		bool is_memory() const { return _v.index() == 1; }
-		// returns the width of a bitvector sort, errors out for other sorts
-		int width() const { return std::get<0>(_v); }
-		// returns the address width of a bitvector sort, errors out for other sorts
-		int addr_width() const { return std::get<1>(_v).first; }
-		// returns the data width of a bitvector sort, errors out for other sorts
-		int data_width() const { return std::get<1>(_v).second; }
-		bool operator==(Sort const& other) const { return _v == other._v; }
-		[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(_v); return h; }
-	};
-	class IR;
-	class Factory;
-	class Node;
-	class IRInput {
-		friend class Factory;
-	public:
-		IdString name;
-		IdString kind;
-		Sort sort;
-	private:
-		IRInput(IR &, IdString name, IdString kind, Sort sort)
-		: name(name), kind(kind), sort(std::move(sort)) {}
-	};
-	class IROutput {
-		friend class Factory;
-		IR &_ir;
-	public:
-		IdString name;
-		IdString kind;
-		Sort sort;
-	private:
-		IROutput(IR &ir, IdString name, IdString kind, Sort sort)
-		: _ir(ir), name(name), kind(kind), sort(std::move(sort)) {}
-	public:
-		Node value() const;
-		bool has_value() const;
-		void set_value(Node value);
-	};
-	class IRState {
-		friend class Factory;
-		IR &_ir;
-	public:
-		IdString name;
-		IdString kind;
-		Sort sort;
-	private:
-		std::variant<RTLIL::Const, MemContents> _initial;
-		IRState(IR &ir, IdString name, IdString kind, Sort sort)
-		: _ir(ir), name(name), kind(kind), sort(std::move(sort)) {}
-	public:
-		Node next_value() const;
-		bool has_next_value() const;
-		RTLIL::Const const& initial_value_signal() const { return std::get<RTLIL::Const>(_initial); }
-		MemContents const& initial_value_memory() const { return std::get<MemContents>(_initial); }
-		void set_next_value(Node value);
-		void set_initial_value(RTLIL::Const value) { value.extu(sort.width()); _initial = std::move(value); }
-		void set_initial_value(MemContents value) { log_assert(Sort(value.addr_width(), value.data_width()) == sort); _initial = std::move(value); }
-	};
-	class IR {
-		friend class Factory;
-		friend class Node;
-		friend class IRInput;
-		friend class IROutput;
-		friend class IRState;
-		// one NodeData is stored per Node, containing the function and non-node arguments
-		// note that NodeData is deduplicated by ComputeGraph
-		class NodeData {
-			Fn _fn;
-			std::variant<
-				std::monostate,
-				RTLIL::Const,
-				std::pair<IdString, IdString>,
-				int
-			> _extra;
-		public:
-			NodeData() : _fn(Fn::invalid) {}
-			NodeData(Fn fn) : _fn(fn) {}
-			template<class T> NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward<T>(extra)) {}
-			Fn fn() const { return _fn; }
-			const RTLIL::Const &as_const() const { return std::get<RTLIL::Const>(_extra); }
-			std::pair<IdString, IdString> as_idstring_pair() const { return std::get<std::pair<IdString, IdString>>(_extra); }
-			int as_int() const { return std::get<int>(_extra); }
-			[[nodiscard]] Hasher hash_into(Hasher h) const {
-				h.eat((unsigned int) _fn);
-				h.eat(_extra);
-				return h;
-			}
-			bool operator==(NodeData const &other) const {
-				return _fn == other._fn && _extra == other._extra;
-			}
-		};
-		// Attr contains all the information about a note that should not be deduplicated
-		struct Attr {
-			Sort sort;
-		};
-		// our specialised version of ComputeGraph
-		// the sparse_attr IdString stores a naming suggestion, retrieved with name()
-		// the key is currently used to identify the nodes that represent output and next state values
-		// the bool is true for next state values
-		using Graph = ComputeGraph<NodeData, Attr, IdString, std::tuple<IdString, IdString, bool>>;
-		Graph _graph;
-		dict<std::pair<IdString, IdString>, IRInput> _inputs;
-		dict<std::pair<IdString, IdString>, IROutput> _outputs;
-		dict<std::pair<IdString, IdString>, IRState> _states;
-		IR::Graph::Ref mutate(Node n);
-	public:
-		static IR from_module(Module *module);
-		Factory factory();
-		int size() const { return _graph.size(); }
-		Node operator[](int i);
-		void topological_sort();
-		void forward_buf();
-		IRInput const& input(IdString name, IdString kind) const { return _inputs.at({name, kind}); }
-		IRInput const& input(IdString name) const { return input(name, ID($input)); }
-		IROutput const& output(IdString name, IdString kind) const { return _outputs.at({name, kind}); }
-		IROutput const& output(IdString name) const { return output(name, ID($output)); }
-		IRState const& state(IdString name, IdString kind) const { return _states.at({name, kind}); }
-		IRState const& state(IdString name) const { return state(name, ID($state)); }
-		bool has_input(IdString name, IdString kind) const { return _inputs.count({name, kind}); }
-		bool has_output(IdString name, IdString kind) const { return _outputs.count({name, kind}); }
-		bool has_state(IdString name, IdString kind) const { return _states.count({name, kind}); }
-		vector<IRInput const*> inputs(IdString kind) const;
-		vector<IRInput const*> inputs() const { return inputs(ID($input)); }
-		vector<IROutput const*> outputs(IdString kind) const;
-		vector<IROutput const*> outputs() const { return outputs(ID($output)); }
-		vector<IRState const*> states(IdString kind) const;
-		vector<IRState const*> states() const { return states(ID($state)); }
-		vector<IRInput const*> all_inputs() const;
-		vector<IROutput const*> all_outputs() const;
-		vector<IRState const*> all_states() const;
-		class iterator {
-			friend class IR;
-			IR *_ir;
-			int _index;
-			iterator(IR *ir, int index) : _ir(ir), _index(index) {}
-		public:
-			using iterator_category = std::input_iterator_tag;
-			using value_type = Node;
-			using pointer = arrow_proxy<Node>;
-			using reference = Node;
-			using difference_type = ptrdiff_t;
-			Node operator*();
-			iterator &operator++() { _index++; return *this; }
-			bool operator!=(iterator const &other) const { return _ir != other._ir || _index != other._index; }
-			bool operator==(iterator const &other) const { return !(*this != other); }
-			pointer operator->();
-		};
-		iterator begin() { return iterator(this, 0); }
-		iterator end() { return iterator(this, _graph.size()); }
-	};
-	// Node is an immutable reference to a FunctionalIR node
-	class Node {
-		friend class Factory;
-		friend class IR;
-		friend class IRInput;
-		friend class IROutput;
-		friend class IRState;
-		IR::Graph::ConstRef _ref;
-		explicit Node(IR::Graph::ConstRef ref) : _ref(ref) { }
-		explicit operator IR::Graph::ConstRef() { return _ref; }
-	public:
-		// the node's index. may change if nodes are added or removed
-		int id() const { return _ref.index(); }
-		// a name suggestion for the node, which need not be unique
-		IdString name() const {
-			if(_ref.has_sparse_attr())
-				return _ref.sparse_attr();
-			else
-				return std::string("\\n") + std::to_string(id());
-		}
-		Fn fn() const { return _ref.function().fn(); }
-		Sort sort() const { return _ref.attr().sort; }
-		// returns the width of a bitvector node, errors out for other nodes
-		int width() const { return sort().width(); }
-		size_t arg_count() const { return _ref.size(); }
-		Node arg(int n) const { return Node(_ref.arg(n)); }
-		// visit calls the appropriate visitor method depending on the type of the node
-		template<class Visitor> auto visit(Visitor v) const
-		{
-			// currently templated but could be switched to AbstractVisitor &
-			switch(_ref.function().fn()) {
-			case Fn::invalid: log_error("invalid node in visit"); break;
-			case Fn::buf: return v.buf(*this, arg(0)); break;
-			case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break;
-			case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break;
-			case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break;
-			case Fn::concat: return v.concat(*this, arg(0), arg(1)); break;
-			case Fn::add: return v.add(*this, arg(0), arg(1)); break;
-			case Fn::sub: return v.sub(*this, arg(0), arg(1)); break;
-			case Fn::mul: return v.mul(*this, arg(0), arg(1)); break;
-			case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break;
-			case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break;
-			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break;
-			case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break;
-			case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break;
-			case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break;
-			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break;
-			case Fn::equal: return v.equal(*this, arg(0), arg(1)); break;
-			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break;
-			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; 
-			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break;
-			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; 
-			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break;
-			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break;
-			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break;
-			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break;
-			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break;
-			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
-			case Fn::input: return v.input(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break;
-			case Fn::state: return v.state(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break;
-			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
-			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
-			}
-			log_abort();
-		}
-		std::string to_string();
-		std::string to_string(std::function<std::string(Node)>);
-	};
-	inline IR::Graph::Ref IR::mutate(Node n) { return _graph[n._ref.index()]; }
-	inline Node IR::operator[](int i) { return Node(_graph[i]); }
-	inline Node IROutput::value() const { return Node(_ir._graph({name, kind, false})); }
-	inline bool IROutput::has_value() const { return _ir._graph.has_key({name, kind, false}); }
-	inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, false}); }
-	inline Node IRState::next_value() const { return Node(_ir._graph({name, kind, true})); }
-	inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, kind, true}); }
-	inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, true}); }
-	inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); }
-	inline arrow_proxy<Node> IR::iterator::operator->() { return arrow_proxy<Node>(**this); }
-	// AbstractVisitor provides an abstract base class for visitors
-	template<class T> struct AbstractVisitor {
-		virtual T buf(Node self, Node n) = 0;
-		virtual T slice(Node self, Node a, int offset, int out_width) = 0;
-		virtual T zero_extend(Node self, Node a, int out_width) = 0;
-		virtual T sign_extend(Node self, Node a, int out_width) = 0;
-		virtual T concat(Node self, Node a, Node b) = 0;
-		virtual T add(Node self, Node a, Node b) = 0;
-		virtual T sub(Node self, Node a, Node b) = 0;
-		virtual T mul(Node self, Node a, Node b) = 0;
-		virtual T unsigned_div(Node self, Node a, Node b) = 0;
-		virtual T unsigned_mod(Node self, Node a, Node b) = 0;
-		virtual T bitwise_and(Node self, Node a, Node b) = 0;
-		virtual T bitwise_or(Node self, Node a, Node b) = 0;
-		virtual T bitwise_xor(Node self, Node a, Node b) = 0;
-		virtual T bitwise_not(Node self, Node a) = 0;
-		virtual T unary_minus(Node self, Node a) = 0;
-		virtual T reduce_and(Node self, Node a) = 0;
-		virtual T reduce_or(Node self, Node a) = 0;
-		virtual T reduce_xor(Node self, Node a) = 0;
-		virtual T equal(Node self, Node a, Node b) = 0;
-		virtual T not_equal(Node self, Node a, Node b) = 0;
-		virtual T signed_greater_than(Node self, Node a, Node b) = 0;
-		virtual T signed_greater_equal(Node self, Node a, Node b) = 0;
-		virtual T unsigned_greater_than(Node self, Node a, Node b) = 0;
-		virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0;
-		virtual T logical_shift_left(Node self, Node a, Node b) = 0;
-		virtual T logical_shift_right(Node self, Node a, Node b) = 0;
-		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
-		virtual T mux(Node self, Node a, Node b, Node s) = 0;
-		virtual T constant(Node self, RTLIL::Const const & value) = 0;
-		virtual T input(Node self, IdString name, IdString kind) = 0;
-		virtual T state(Node self, IdString name, IdString kind) = 0;
-		virtual T memory_read(Node self, Node mem, Node addr) = 0;
-		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
-	};
-	// DefaultVisitor provides defaults for all visitor methods which just calls default_handler
-	template<class T> struct DefaultVisitor : public AbstractVisitor<T> {
-		virtual T default_handler(Node self) = 0;
-		T buf(Node self, Node) override { return default_handler(self); }
-		T slice(Node self, Node, int, int) override { return default_handler(self); }
-		T zero_extend(Node self, Node, int) override { return default_handler(self); }
-		T sign_extend(Node self, Node, int) override { return default_handler(self); }
-		T concat(Node self, Node, Node) override { return default_handler(self); }
-		T add(Node self, Node, Node) override { return default_handler(self); }
-		T sub(Node self, Node, Node) override { return default_handler(self); }
-		T mul(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_div(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_mod(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_and(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_or(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_xor(Node self, Node, Node) override { return default_handler(self); }
-		T bitwise_not(Node self, Node) override { return default_handler(self); }
-		T unary_minus(Node self, Node) override { return default_handler(self); }
-		T reduce_and(Node self, Node) override { return default_handler(self); }
-		T reduce_or(Node self, Node) override { return default_handler(self); }
-		T reduce_xor(Node self, Node) override { return default_handler(self); }
-		T equal(Node self, Node, Node) override { return default_handler(self); }
-		T not_equal(Node self, Node, Node) override { return default_handler(self); }
-		T signed_greater_than(Node self, Node, Node) override { return default_handler(self); }
-		T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); }
-		T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); }
-		T logical_shift_left(Node self, Node, Node) override { return default_handler(self); }
-		T logical_shift_right(Node self, Node, Node) override { return default_handler(self); }
-		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
-		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
-		T constant(Node self, RTLIL::Const const &) override { return default_handler(self); }
-		T input(Node self, IdString, IdString) override { return default_handler(self); }
-		T state(Node self, IdString, IdString) override { return default_handler(self); }
-		T memory_read(Node self, Node, Node) override { return default_handler(self); }
-		T memory_write(Node self, Node, Node, Node) override { return default_handler(self); }
-	};
-	// a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes.
-	class Factory {
-		friend class IR;
-		IR &_ir;
-		explicit Factory(IR &ir) : _ir(ir) {}
-		Node add(IR::NodeData &&fn, Sort const &sort, std::initializer_list<Node> args) {
-			log_assert(!sort.is_signal() || sort.width() > 0);
-			log_assert(!sort.is_memory() || (sort.addr_width() > 0 && sort.data_width() > 0));
-			IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
-			for (auto arg : args)
-				ref.append_arg(IR::Graph::ConstRef(arg));
-			return Node(ref);
-		}
-		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
-		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); }
-		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
-	public:
-		IR &ir() { return _ir; }
-		Node slice(Node a, int offset, int out_width) {
-			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
-			if(offset == 0 && out_width == a.width())
-				return a;
-			return add(IR::NodeData(Fn::slice, offset), Sort(out_width), {a});
-		}
-		// extend will either extend or truncate the provided value to reach the desired width
-		Node extend(Node a, int out_width, bool is_signed) {
-			int in_width = a.sort().width();
-			log_assert(a.sort().is_signal());
-			if(in_width == out_width)
-				return a;
-			if(in_width > out_width)
-				return slice(a, 0, out_width);
-			if(is_signed)
-				return add(Fn::sign_extend, Sort(out_width), {a});
-			else
-				return add(Fn::zero_extend, Sort(out_width), {a});
-		}
-		Node concat(Node a, Node b) {
-			log_assert(a.sort().is_signal() && b.sort().is_signal());
-			return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b});
-		}
-		Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
-		Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
-		Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); }
-		Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); }
-		Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); }
-		Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
-		Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
-		Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
-		Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
-		Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
-		Node reduce_and(Node a) {
-			check_unary(a);
-			if(a.width() == 1)
-				return a;
-			return add(Fn::reduce_and, Sort(1), {a});
-		}
-		Node reduce_or(Node a) {
-			check_unary(a);
-			if(a.width() == 1)
-				return a;
-			return add(Fn::reduce_or, Sort(1), {a});
-		}
-		Node reduce_xor(Node a) { 
-			check_unary(a);
-			if(a.width() == 1)
-				return a;
-			return add(Fn::reduce_xor, Sort(1), {a});
-		}
-		Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
-		Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
-		Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
-		Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); }
-		Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); }
-		Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); }
-		Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); }
-		Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); }
-		Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); }
-		Node mux(Node a, Node b, Node s) {
-			log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1));
-			return add(Fn::mux, a.sort(), {a, b, s});
-		}
-		Node memory_read(Node mem, Node addr) {
-			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width());
-			return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr});
-		}
-		Node memory_write(Node mem, Node addr, Node data) {
-			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() &&
-				mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width());
-			return add(Fn::memory_write, mem.sort(), {mem, addr, data});
-		}
-		Node constant(RTLIL::Const value) {
-			int s = value.size();
-			return add(IR::NodeData(Fn::constant, std::move(value)), Sort(s), {});
-		}
-		Node create_pending(int width) {
-			return add(Fn::buf, Sort(width), {});
-		}
-		void update_pending(Node node, Node value) {
-			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
-			log_assert(node.sort() == value.sort());
-			_ir.mutate(node).append_arg(value._ref);
-		}
-		IRInput &add_input(IdString name, IdString kind, Sort sort) {
-			auto [it, inserted] = _ir._inputs.emplace({name, kind}, IRInput(_ir, name, kind, std::move(sort)));
-			if (!inserted) log_error("input `%s` was re-defined", name);
-			return it->second;
-		}
-		IROutput &add_output(IdString name, IdString kind, Sort sort) {
-			auto [it, inserted] = _ir._outputs.emplace({name, kind}, IROutput(_ir, name, kind, std::move(sort)));
-			if (!inserted) log_error("output `%s` was re-defined", name);
-			return it->second;
-		}
-		IRState &add_state(IdString name, IdString kind, Sort sort) {
-			auto [it, inserted] = _ir._states.emplace({name, kind}, IRState(_ir, name, kind, std::move(sort)));
-			if (!inserted) log_error("state `%s` was re-defined", name);
-			return it->second;
-		}
-		Node value(IRInput const& input) {
-			return add(IR::NodeData(Fn::input, std::pair(input.name, input.kind)), input.sort, {});
-		}
-		Node value(IRState const& state) {
-			return add(IR::NodeData(Fn::state, std::pair(state.name, state.kind)), state.sort, {});
-		}
-		void suggest_name(Node node, IdString name) {
-			_ir.mutate(node).sparse_attr() = name;
-		}
-	};
-	inline Factory IR::factory() { return Factory(*this); }
-	template<class Id> class Scope {
-	protected:
-		char substitution_character = '_';
-		virtual bool is_character_legal(char, int) = 0;
-	private:
-		pool<std::string> _used_names;
-		dict<Id, std::string> _by_id;
-	public:
-		void reserve(std::string name) {
-			_used_names.insert(std::move(name));
-		}
-		std::string unique_name(IdString suggestion) {
-			std::string str = suggestion.unescape();
-			for(size_t i = 0; i < str.size(); i++)
-				if(!is_character_legal(str[i], i))
-					str[i] = substitution_character;
-			if(_used_names.count(str) == 0) {
-				_used_names.insert(str);
-				return str;
-			}
-			for (int idx = 0 ; ; idx++){
-				std::string suffixed = str + "_" + std::to_string(idx);
-				if(_used_names.count(suffixed) == 0) {
-					_used_names.insert(suffixed);
-					return suffixed;
-				}
-			}
-		}
-		std::string operator()(Id id, IdString suggestion) {
-			auto it = _by_id.find(id);
-			if(it != _by_id.end())
-				return it->second;
-			std::string str = unique_name(suggestion);
-			_by_id.insert({id, str});
-			return str;
-		}
-	};
-	class Writer {
-		std::ostream *os;
-		void print_impl(const char *fmt, vector<std::function<void()>>& fns);
-	public:
-		Writer(std::ostream &os) : os(&os) {}
-		template<class T> Writer& operator <<(T&& arg) { *os << std::forward<T>(arg); return *this; }
-		template<typename... Args>
-		void print(const char *fmt, Args&&... args)
-		{
-			vector<std::function<void()>> fns { [&]() { *this << args; }... };
-			print_impl(fmt, fns);
-		}
-		template<typename Fn, typename... Args>
-		void print_with(Fn fn, const char *fmt, Args&&... args)
-		{
-			vector<std::function<void()>> fns { [&]() {
-				if constexpr (std::is_invocable_v<Fn, Args>)
-					*this << fn(args);
-				else
-					*this << args; }...
-			};
-			print_impl(fmt, fns);
-		}
-	};
+// namespace Functional {
+// 	// each function is documented with a short pseudocode declaration or definition
+// 	// standard C/Verilog operators are used to describe the result
+// 	// 
+// 	// the sorts used in this are:
+// 	// - bit[N]: a bitvector of N bits
+// 	//   bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend
+// 	//   but is meant to indicate how the value is interpreted
+// 	//   if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation
+// 	// - memory[N, M]: a memory with N address and M data bits
+// 	// - int: C++ int
+// 	// - Const[N]: yosys RTLIL::Const (with size() == N)
+// 	// - TwineRef: yosys TwineRef
+// 	// - any: used in documentation to indicate that the sort is unconstrained
+// 	//
+// 	// nodes in the functional backend are either of sort bit[N] or memory[N,M] (for some N, M: int)
+// 	// additionally, they can carry a constant of sort int, Const[N] or TwineRef
+// 	// each node has a 'sort' field that stores the sort of the node
+// 	// slice, zero_extend, sign_extend use the sort field to store out_width
+// 	enum class Fn {
+// 		// invalid() = known-invalid/shouldn't happen value
+// 		// TODO: maybe remove this and use e.g. std::optional instead?
+// 		invalid,
+// 		// buf(a: any): any = a
+// 		// no-op operation
+// 		// when constructing the compute graph we generate invalid buf() nodes as a placeholder
+// 		// and later insert the argument
+// 		buf,
+// 		// slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width]
+// 		// required: offset + out_width <= in_width
+// 		slice,
+// 		// zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended)
+// 		// required: out_width > in_width
+// 		zero_extend,
+// 		// sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended)
+// 		// required: out_width > in_width
+// 		sign_extend,
+// 		// concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax)
+// 		// concatenates two bitvectors, with a in the least significant position and b in the more significant position
+// 		concat,
+// 		// add(a: bit[N], b: bit[N]): bit[N] = a + b
+// 		add,
+// 		// sub(a: bit[N], b: bit[N]): bit[N] = a - b
+// 		sub,
+// 		// mul(a: bit[N], b: bit[N]): bit[N] = a * b
+// 		mul,
+// 		// unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b
+// 		unsigned_div,
+// 		// unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b
+// 		unsigned_mod,
+// 		// bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b
+// 		bitwise_and,
+// 		// bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b
+// 		bitwise_or,
+// 		// bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b
+// 		bitwise_xor,
+// 		// bitwise_not(a: bit[N]): bit[N] = ~a
+// 		bitwise_not,
+// 		// reduce_and(a: bit[N]): bit[1] = &a
+// 		reduce_and,
+// 		// reduce_or(a: bit[N]): bit[1] = |a
+// 		reduce_or,
+// 		// reduce_xor(a: bit[N]): bit[1] = ^a
+// 		reduce_xor,
+// 		// unary_minus(a: bit[N]): bit[N] = -a
+// 		unary_minus,
+// 		// equal(a: bit[N], b: bit[N]): bit[1] = (a == b)
+// 		equal,
+// 		// not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b)
+// 		not_equal,
+// 		// signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b)
+// 		signed_greater_than,
+// 		// signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b)
+// 		signed_greater_equal,
+// 		// unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b)
+// 		unsigned_greater_than,
+// 		// unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b)
+// 		unsigned_greater_equal,
+// 		// logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b
+// 		// required: M == clog2(N)
+// 		logical_shift_left,
+// 		// logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b
+// 		// required: M == clog2(N)
+// 		logical_shift_right,
+// 		// arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b
+// 		// required: M == clog2(N)
+// 		arithmetic_shift_right,
+// 		// mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a
+// 		mux,
+// 		// constant(a: Const[N]): bit[N] = a
+// 		constant,
+// 		// input(a: IdString): any
+// 		// returns the current value of the input with the specified name
+// 		input,
+// 		// state(a: IdString): any
+// 		// returns the current value of the state variable with the specified name
+// 		state,
+// 		// memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr]
+// 		memory_read,
+// 		// memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width]
+// 		// returns a copy of `memory` but with the value at `addr` changed to `data`
+// 		memory_write
+// 	};
+// 	// returns the name of a Fn value, as a string literal
+// 	const char *fn_to_string(Fn);
+// 	// Sort represents the sort or type of a node
+// 	// currently the only two sorts are signal/bit and memory
+// 	class Sort {
+// 		std::variant<int, std::pair<int, int>> _v;
+// 	public:
+// 		explicit Sort(int width) : _v(width) { }
+// 		Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { }
+// 		bool is_signal() const { return _v.index() == 0; }
+// 		bool is_memory() const { return _v.index() == 1; }
+// 		// returns the width of a bitvector sort, errors out for other sorts
+// 		int width() const { return std::get<0>(_v); }
+// 		// returns the address width of a bitvector sort, errors out for other sorts
+// 		int addr_width() const { return std::get<1>(_v).first; }
+// 		// returns the data width of a bitvector sort, errors out for other sorts
+// 		int data_width() const { return std::get<1>(_v).second; }
+// 		bool operator==(Sort const& other) const { return _v == other._v; }
+// 		[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(_v); return h; }
+// 	};
+// 	class IR;
+// 	class Factory;
+// 	class Node;
+// 	class IRInput {
+// 		friend class Factory;
+// 	public:
+// 		TwineRef name;
+// 		TwineRef kind;
+// 		Sort sort;
+// 	private:
+// 		IRInput(IR &, IdString name, IdString kind, Sort sort)
+// 		: name(name), kind(kind), sort(std::move(sort)) {}
+// 	};
+// 	class IROutput {
+// 		friend class Factory;
+// 		IR &_ir;
+// 	public:
+// 		TwineRef name;
+// 		TwineRef kind;
+// 		Sort sort;
+// 	private:
+// 		IROutput(IR &ir, TwineRef name, TwineRef kind, Sort sort)
+// 		: _ir(ir), name(name), kind(kind), sort(std::move(sort)) {}
+// 	public:
+// 		Node value() const;
+// 		bool has_value() const;
+// 		void set_value(Node value);
+// 	};
+// 	class IRState {
+// 		friend class Factory;
+// 		IR &_ir;
+// 	public:
+// 		TwineRef name;
+// 		TwineRef kind;
+// 		Sort sort;
+// 	private:
+// 		std::variant<RTLIL::Const, MemContents> _initial;
+// 		IRState(IR &ir, TwineRef name, TwineRef kind, Sort sort)
+// 		: _ir(ir), name(name), kind(kind), sort(std::move(sort)) {}
+// 	public:
+// 		Node next_value() const;
+// 		bool has_next_value() const;
+// 		RTLIL::Const const& initial_value_signal() const { return std::get<RTLIL::Const>(_initial); }
+// 		MemContents const& initial_value_memory() const { return std::get<MemContents>(_initial); }
+// 		void set_next_value(Node value);
+// 		void set_initial_value(RTLIL::Const value) { value.extu(sort.width()); _initial = std::move(value); }
+// 		void set_initial_value(MemContents value) { log_assert(Sort(value.addr_width(), value.data_width()) == sort); _initial = std::move(value); }
+// 	};
+// 	class IR {
+// 		friend class Factory;
+// 		friend class Node;
+// 		friend class IRInput;
+// 		friend class IROutput;
+// 		friend class IRState;
+// 		// one NodeData is stored per Node, containing the function and non-node arguments
+// 		// note that NodeData is deduplicated by ComputeGraph
+// 		class NodeData {
+// 			Fn _fn;
+// 			std::variant<
+// 				std::monostate,
+// 				RTLIL::Const,
+// 				std::pair<TwineRef, TwineRef>,
+// 				int
+// 			> _extra;
+// 		public:
+// 			NodeData() : _fn(Fn::invalid) {}
+// 			NodeData(Fn fn) : _fn(fn) {}
+// 			template<class T> NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward<T>(extra)) {}
+// 			Fn fn() const { return _fn; }
+// 			const RTLIL::Const &as_const() const { return std::get<RTLIL::Const>(_extra); }
+// 			std::pair<TwineRef, TwineRef> as_idstring_pair() const { return std::get<std::pair<TwineRef, TwineRef>>(_extra); }
+// 			int as_int() const { return std::get<int>(_extra); }
+// 			[[nodiscard]] Hasher hash_into(Hasher h) const {
+// 				h.eat((unsigned int) _fn);
+// 				h.eat(_extra);
+// 				return h;
+// 			}
+// 			bool operator==(NodeData const &other) const {
+// 				return _fn == other._fn && _extra == other._extra;
+// 			}
+// 		};
+// 		// Attr contains all the information about a note that should not be deduplicated
+// 		struct Attr {
+// 			Sort sort;
+// 		};
+// 		// our specialised version of ComputeGraph
+// 		// the sparse_attr TwineRef stores a naming suggestion, retrieved with name()
+// 		// the key is currently used to identify the nodes that represent output and next state values
+// 		// the bool is true for next state values
+// 		using Graph = ComputeGraph<NodeData, Attr, TwineRef, std::tuple<TwineRef, TwineRef, bool>>;
+// 		Graph _graph;
+// 		dict<std::pair<TwineRef, TwineRef>, IRInput> _inputs;
+// 		dict<std::pair<TwineRef, TwineRef>, IROutput> _outputs;
+// 		dict<std::pair<TwineRef, TwineRef>, IRState> _states;
+// 		IR::Graph::Ref mutate(Node n);
+// 	public:
+// 		static IR from_module(Module *module);
+// 		Factory factory();
+// 		int size() const { return _graph.size(); }
+// 		Node operator[](int i);
+// 		void topological_sort();
+// 		void forward_buf();
+// 		IRInput const& input(TwineRef name, TwineRef kind) const { return _inputs.at({name, kind}); }
+// 		IRInput const& input(TwineRef name) const { return input(name, TW($input)); }
+// 		IROutput const& output(TwineRef name, TwineRef kind) const { return _outputs.at({name, kind}); }
+// 		IROutput const& output(TwineRef name) const { return output(name, TW($output)); }
+// 		IRState const& state(TwineRef name, TwineRef kind) const { return _states.at({name, kind}); }
+// 		IRState const& state(TwineRef name) const { return state(name, TW($state)); }
+// 		bool has_input(TwineRef name, TwineRef kind) const { return _inputs.count({name, kind}); }
+// 		bool has_output(TwineRef name, TwineRef kind) const { return _outputs.count({name, kind}); }
+// 		bool has_state(TwineRef name, TwineRef kind) const { return _states.count({name, kind}); }
+// 		vector<IRInput const*> inputs(TwineRef kind) const;
+// 		vector<IRInput const*> inputs() const { return inputs(TW($input)); }
+// 		vector<IROutput const*> outputs(TwineRef kind) const;
+// 		vector<IROutput const*> outputs() const { return outputs(TW($output)); }
+// 		vector<IRState const*> states(TwineRef kind) const;
+// 		vector<IRState const*> states() const { return states(TW($state)); }
+// 		vector<IRInput const*> all_inputs() const;
+// 		vector<IROutput const*> all_outputs() const;
+// 		vector<IRState const*> all_states() const;
+// 		class iterator {
+// 			friend class IR;
+// 			IR *_ir;
+// 			int _index;
+// 			iterator(IR *ir, int index) : _ir(ir), _index(index) {}
+// 		public:
+// 			using iterator_category = std::input_iterator_tag;
+// 			using value_type = Node;
+// 			using pointer = arrow_proxy<Node>;
+// 			using reference = Node;
+// 			using difference_type = ptrdiff_t;
+// 			Node operator*();
+// 			iterator &operator++() { _index++; return *this; }
+// 			bool operator!=(iterator const &other) const { return _ir != other._ir || _index != other._index; }
+// 			bool operator==(iterator const &other) const { return !(*this != other); }
+// 			pointer operator->();
+// 		};
+// 		iterator begin() { return iterator(this, 0); }
+// 		iterator end() { return iterator(this, _graph.size()); }
+// 	};
+// 	// Node is an immutable reference to a FunctionalIR node
+// 	class Node {
+// 		friend class Factory;
+// 		friend class IR;
+// 		friend class IRInput;
+// 		friend class IROutput;
+// 		friend class IRState;
+// 		IR::Graph::ConstRef _ref;
+// 		explicit Node(IR::Graph::ConstRef ref) : _ref(ref) { }
+// 		explicit operator IR::Graph::ConstRef() { return _ref; }
+// 	public:
+// 		// the node's index. may change if nodes are added or removed
+// 		int id() const { return _ref.index(); }
+// 		// a name suggestion for the node, which need not be unique
+// 		TwineRef name() const {
+// 			if(_ref.has_sparse_attr())
+// 				return _ref.sparse_attr();
+// 			else
+// 				return std::string("\\n") + std::to_string(id());
+// 		}
+// 		Fn fn() const { return _ref.function().fn(); }
+// 		Sort sort() const { return _ref.attr().sort; }
+// 		// returns the width of a bitvector node, errors out for other nodes
+// 		int width() const { return sort().width(); }
+// 		size_t arg_count() const { return _ref.size(); }
+// 		Node arg(int n) const { return Node(_ref.arg(n)); }
+// 		// visit calls the appropriate visitor method depending on the type of the node
+// 		template<class Visitor> auto visit(Visitor v) const
+// 		{
+// 			// currently templated but could be switched to AbstractVisitor &
+// 			switch(_ref.function().fn()) {
+// 			case Fn::invalid: log_error("invalid node in visit"); break;
+// 			case Fn::buf: return v.buf(*this, arg(0)); break;
+// 			case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break;
+// 			case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break;
+// 			case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break;
+// 			case Fn::concat: return v.concat(*this, arg(0), arg(1)); break;
+// 			case Fn::add: return v.add(*this, arg(0), arg(1)); break;
+// 			case Fn::sub: return v.sub(*this, arg(0), arg(1)); break;
+// 			case Fn::mul: return v.mul(*this, arg(0), arg(1)); break;
+// 			case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break;
+// 			case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break;
+// 			case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break;
+// 			case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break;
+// 			case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break;
+// 			case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break;
+// 			case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break;
+// 			case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break;
+// 			case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break;
+// 			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break;
+// 			case Fn::equal: return v.equal(*this, arg(0), arg(1)); break;
+// 			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break;
+// 			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; 
+// 			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break;
+// 			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; 
+// 			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break;
+// 			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break;
+// 			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break;
+// 			case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break;
+// 			case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break;
+// 			case Fn::constant: return v.constant(*this, _ref.function().as_const()); break;
+// 			case Fn::input: return v.input(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break;
+// 			case Fn::state: return v.state(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break;
+// 			case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break;
+// 			case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break;
+// 			}
+// 			log_abort();
+// 		}
+// 		std::string to_string();
+// 		std::string to_string(std::function<std::string(Node)>);
+// 	};
+// 	inline IR::Graph::Ref IR::mutate(Node n) { return _graph[n._ref.index()]; }
+// 	inline Node IR::operator[](int i) { return Node(_graph[i]); }
+// 	inline Node IROutput::value() const { return Node(_ir._graph({name, kind, false})); }
+// 	inline bool IROutput::has_value() const { return _ir._graph.has_key({name, kind, false}); }
+// 	inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, false}); }
+// 	inline Node IRState::next_value() const { return Node(_ir._graph({name, kind, true})); }
+// 	inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, kind, true}); }
+// 	inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, true}); }
+// 	inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); }
+// 	inline arrow_proxy<Node> IR::iterator::operator->() { return arrow_proxy<Node>(**this); }
+// 	// AbstractVisitor provides an abstract base class for visitors
+// 	template<class T> struct AbstractVisitor {
+// 		virtual T buf(Node self, Node n) = 0;
+// 		virtual T slice(Node self, Node a, int offset, int out_width) = 0;
+// 		virtual T zero_extend(Node self, Node a, int out_width) = 0;
+// 		virtual T sign_extend(Node self, Node a, int out_width) = 0;
+// 		virtual T concat(Node self, Node a, Node b) = 0;
+// 		virtual T add(Node self, Node a, Node b) = 0;
+// 		virtual T sub(Node self, Node a, Node b) = 0;
+// 		virtual T mul(Node self, Node a, Node b) = 0;
+// 		virtual T unsigned_div(Node self, Node a, Node b) = 0;
+// 		virtual T unsigned_mod(Node self, Node a, Node b) = 0;
+// 		virtual T bitwise_and(Node self, Node a, Node b) = 0;
+// 		virtual T bitwise_or(Node self, Node a, Node b) = 0;
+// 		virtual T bitwise_xor(Node self, Node a, Node b) = 0;
+// 		virtual T bitwise_not(Node self, Node a) = 0;
+// 		virtual T unary_minus(Node self, Node a) = 0;
+// 		virtual T reduce_and(Node self, Node a) = 0;
+// 		virtual T reduce_or(Node self, Node a) = 0;
+// 		virtual T reduce_xor(Node self, Node a) = 0;
+// 		virtual T equal(Node self, Node a, Node b) = 0;
+// 		virtual T not_equal(Node self, Node a, Node b) = 0;
+// 		virtual T signed_greater_than(Node self, Node a, Node b) = 0;
+// 		virtual T signed_greater_equal(Node self, Node a, Node b) = 0;
+// 		virtual T unsigned_greater_than(Node self, Node a, Node b) = 0;
+// 		virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0;
+// 		virtual T logical_shift_left(Node self, Node a, Node b) = 0;
+// 		virtual T logical_shift_right(Node self, Node a, Node b) = 0;
+// 		virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0;
+// 		virtual T mux(Node self, Node a, Node b, Node s) = 0;
+// 		virtual T constant(Node self, RTLIL::Const const & value) = 0;
+// 		virtual T input(Node self, TwineRef name, TwineRef kind) = 0;
+// 		virtual T state(Node self, TwineRef name, TwineRef kind) = 0;
+// 		virtual T memory_read(Node self, Node mem, Node addr) = 0;
+// 		virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0;
+// 	};
+// 	// DefaultVisitor provides defaults for all visitor methods which just calls default_handler
+// 	template<class T> struct DefaultVisitor : public AbstractVisitor<T> {
+// 		virtual T default_handler(Node self) = 0;
+// 		T buf(Node self, Node) override { return default_handler(self); }
+// 		T slice(Node self, Node, int, int) override { return default_handler(self); }
+// 		T zero_extend(Node self, Node, int) override { return default_handler(self); }
+// 		T sign_extend(Node self, Node, int) override { return default_handler(self); }
+// 		T concat(Node self, Node, Node) override { return default_handler(self); }
+// 		T add(Node self, Node, Node) override { return default_handler(self); }
+// 		T sub(Node self, Node, Node) override { return default_handler(self); }
+// 		T mul(Node self, Node, Node) override { return default_handler(self); }
+// 		T unsigned_div(Node self, Node, Node) override { return default_handler(self); }
+// 		T unsigned_mod(Node self, Node, Node) override { return default_handler(self); }
+// 		T bitwise_and(Node self, Node, Node) override { return default_handler(self); }
+// 		T bitwise_or(Node self, Node, Node) override { return default_handler(self); }
+// 		T bitwise_xor(Node self, Node, Node) override { return default_handler(self); }
+// 		T bitwise_not(Node self, Node) override { return default_handler(self); }
+// 		T unary_minus(Node self, Node) override { return default_handler(self); }
+// 		T reduce_and(Node self, Node) override { return default_handler(self); }
+// 		T reduce_or(Node self, Node) override { return default_handler(self); }
+// 		T reduce_xor(Node self, Node) override { return default_handler(self); }
+// 		T equal(Node self, Node, Node) override { return default_handler(self); }
+// 		T not_equal(Node self, Node, Node) override { return default_handler(self); }
+// 		T signed_greater_than(Node self, Node, Node) override { return default_handler(self); }
+// 		T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); }
+// 		T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); }
+// 		T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); }
+// 		T logical_shift_left(Node self, Node, Node) override { return default_handler(self); }
+// 		T logical_shift_right(Node self, Node, Node) override { return default_handler(self); }
+// 		T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); }
+// 		T mux(Node self, Node, Node, Node) override { return default_handler(self); }
+// 		T constant(Node self, RTLIL::Const const &) override { return default_handler(self); }
+// 		T input(Node self, TwineRef, TwineRef) override { return default_handler(self); }
+// 		T state(Node self, TwineRef, TwineRef) override { return default_handler(self); }
+// 		T memory_read(Node self, Node, Node) override { return default_handler(self); }
+// 		T memory_write(Node self, Node, Node, Node) override { return default_handler(self); }
+// 	};
+// 	// a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes.
+// 	class Factory {
+// 		friend class IR;
+// 		IR &_ir;
+// 		explicit Factory(IR &ir) : _ir(ir) {}
+// 		Node add(IR::NodeData &&fn, Sort const &sort, std::initializer_list<Node> args) {
+// 			log_assert(!sort.is_signal() || sort.width() > 0);
+// 			log_assert(!sort.is_memory() || (sort.addr_width() > 0 && sort.data_width() > 0));
+// 			IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)});
+// 			for (auto arg : args)
+// 				ref.append_arg(IR::Graph::ConstRef(arg));
+// 			return Node(ref);
+// 		}
+// 		void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); }
+// 		void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); }
+// 		void check_unary(Node const &a) { log_assert(a.sort().is_signal()); }
+// 	public:
+// 		IR &ir() { return _ir; }
+// 		Node slice(Node a, int offset, int out_width) {
+// 			log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width());
+// 			if(offset == 0 && out_width == a.width())
+// 				return a;
+// 			return add(IR::NodeData(Fn::slice, offset), Sort(out_width), {a});
+// 		}
+// 		// extend will either extend or truncate the provided value to reach the desired width
+// 		Node extend(Node a, int out_width, bool is_signed) {
+// 			int in_width = a.sort().width();
+// 			log_assert(a.sort().is_signal());
+// 			if(in_width == out_width)
+// 				return a;
+// 			if(in_width > out_width)
+// 				return slice(a, 0, out_width);
+// 			if(is_signed)
+// 				return add(Fn::sign_extend, Sort(out_width), {a});
+// 			else
+// 				return add(Fn::zero_extend, Sort(out_width), {a});
+// 		}
+// 		Node concat(Node a, Node b) {
+// 			log_assert(a.sort().is_signal() && b.sort().is_signal());
+// 			return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b});
+// 		}
+// 		Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); }
+// 		Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); }
+// 		Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); }
+// 		Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); }
+// 		Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); }
+// 		Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); }
+// 		Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); }
+// 		Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); }
+// 		Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); }
+// 		Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); }
+// 		Node reduce_and(Node a) {
+// 			check_unary(a);
+// 			if(a.width() == 1)
+// 				return a;
+// 			return add(Fn::reduce_and, Sort(1), {a});
+// 		}
+// 		Node reduce_or(Node a) {
+// 			check_unary(a);
+// 			if(a.width() == 1)
+// 				return a;
+// 			return add(Fn::reduce_or, Sort(1), {a});
+// 		}
+// 		Node reduce_xor(Node a) { 
+// 			check_unary(a);
+// 			if(a.width() == 1)
+// 				return a;
+// 			return add(Fn::reduce_xor, Sort(1), {a});
+// 		}
+// 		Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); }
+// 		Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); }
+// 		Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); }
+// 		Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); }
+// 		Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); }
+// 		Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); }
+// 		Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); }
+// 		Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); }
+// 		Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); }
+// 		Node mux(Node a, Node b, Node s) {
+// 			log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1));
+// 			return add(Fn::mux, a.sort(), {a, b, s});
+// 		}
+// 		Node memory_read(Node mem, Node addr) {
+// 			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width());
+// 			return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr});
+// 		}
+// 		Node memory_write(Node mem, Node addr, Node data) {
+// 			log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() &&
+// 				mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width());
+// 			return add(Fn::memory_write, mem.sort(), {mem, addr, data});
+// 		}
+// 		Node constant(RTLIL::Const value) {
+// 			int s = value.size();
+// 			return add(IR::NodeData(Fn::constant, std::move(value)), Sort(s), {});
+// 		}
+// 		Node create_pending(int width) {
+// 			return add(Fn::buf, Sort(width), {});
+// 		}
+// 		void update_pending(Node node, Node value) {
+// 			log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0);
+// 			log_assert(node.sort() == value.sort());
+// 			_ir.mutate(node).append_arg(value._ref);
+// 		}
+// 		IRInput &add_input(TwineRef name, TwineRef kind, Sort sort) {
+// 			auto [it, inserted] = _ir._inputs.emplace({name, kind}, IRInput(_ir, name, kind, std::move(sort)));
+// 			if (!inserted) log_error("input `%s` was re-defined", name);
+// 			return it->second;
+// 		}
+// 		IROutput &add_output(TwineRef name, TwineRef kind, Sort sort) {
+// 			auto [it, inserted] = _ir._outputs.emplace({name, kind}, IROutput(_ir, name, kind, std::move(sort)));
+// 			if (!inserted) log_error("output `%s` was re-defined", name);
+// 			return it->second;
+// 		}
+// 		IRState &add_state(TwineRef name, TwineRef kind, Sort sort) {
+// 			auto [it, inserted] = _ir._states.emplace({name, kind}, IRState(_ir, name, kind, std::move(sort)));
+// 			if (!inserted) log_error("state `%s` was re-defined", name);
+// 			return it->second;
+// 		}
+// 		Node value(IRInput const& input) {
+// 			return add(IR::NodeData(Fn::input, std::pair(input.name, input.kind)), input.sort, {});
+// 		}
+// 		Node value(IRState const& state) {
+// 			return add(IR::NodeData(Fn::state, std::pair(state.name, state.kind)), state.sort, {});
+// 		}
+// 		void suggest_name(Node node, TwineRef name) {
+// 			_ir.mutate(node).sparse_attr() = name;
+// 		}
+// 	};
+// 	inline Factory IR::factory() { return Factory(*this); }
+// 	template<class Id> class Scope {
+// 	protected:
+// 		char substitution_character = '_';
+// 		virtual bool is_character_legal(char, int) = 0;
+// 	private:
+// 		pool<std::string> _used_names;
+// 		dict<Id, std::string> _by_id;
+// 	public:
+// 		void reserve(std::string name) {
+// 			_used_names.insert(std::move(name));
+// 		}
+// 		std::string unique_name(TwineRef suggestion) {
+// 			std::string str = design->twines.unescaped_str(suggestion);
+// 			for(size_t i = 0; i < str.size(); i++)
+// 				if(!is_character_legal(str[i], i))
+// 					str[i] = substitution_character;
+// 			if(_used_names.count(str) == 0) {
+// 				_used_names.insert(str);
+// 				return str;
+// 			}
+// 			for (int idx = 0 ; ; idx++){
+// 				std::string suffixed = str + "_" + std::to_string(idx);
+// 				if(_used_names.count(suffixed) == 0) {
+// 					_used_names.insert(suffixed);
+// 					return suffixed;
+// 				}
+// 			}
+// 		}
+// 		std::string operator()(Id id, TwineRef suggestion) {
+// 			auto it = _by_id.find(id);
+// 			if(it != _by_id.end())
+// 				return it->second;
+// 			std::string str = unique_name(suggestion);
+// 			_by_id.insert({id, str});
+// 			return str;
+// 		}
+// 	};
+// 	class Writer {
+// 		std::ostream *os;
+// 		void print_impl(const char *fmt, vector<std::function<void()>>& fns);
+// 	public:
+// 		Writer(std::ostream &os) : os(&os) {}
+// 		template<class T> Writer& operator <<(T&& arg) { *os << std::forward<T>(arg); return *this; }
+// 		template<typename... Args>
+// 		void print(const char *fmt, Args&&... args)
+// 		{
+// 			vector<std::function<void()>> fns { [&]() { *this << args; }... };
+// 			print_impl(fmt, fns);
+// 		}
+// 		template<typename Fn, typename... Args>
+// 		void print_with(Fn fn, const char *fmt, Args&&... args)
+// 		{
+// 			vector<std::function<void()>> fns { [&]() {
+// 				if constexpr (std::is_invocable_v<Fn, Args>)
+// 					*this << fn(args);
+// 				else
+// 					*this << args; }...
+// 			};
+// 			print_impl(fmt, fns);
+// 		}
+// 	};
 
-}
+// }
 
-YOSYS_NAMESPACE_END
+// YOSYS_NAMESPACE_END
 
-#endif
+// #endif
diff --git a/kernel/macc.h b/kernel/macc.h
index 5bbe042b1..e5f139836 100644
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -138,11 +138,11 @@ struct Macc
 
 	void from_cell(RTLIL::Cell *cell)
 	{
-		if (cell->type == ID($macc)) {
+		if (cell->type == TW($macc)) {
 			from_cell_v1(cell);
 			return;
 		}
-		log_assert(cell->type == ID($macc_v2));
+		log_assert(cell->type == TW($macc_v2));
 
 		RTLIL::SigSpec port_a = cell->getPort(TW::A);
 		RTLIL::SigSpec port_b = cell->getPort(TW::B);
diff --git a/kernel/mem.cc b/kernel/mem.cc
index d2b0fdbc7..77086a3ca 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -123,7 +123,7 @@ void Mem::emit() {
 		if (!cell) {
 			if (memid.empty())
 				memid = NEW_ID;
-			cell = module->addCell(Twine{memid.str()}, ID($mem_v2));
+			cell = module->addCell(Twine{memid.str()}, TW::$mem_v2);
 		}
 		cell->type_impl = TW::$mem_v2;
 		cell->attributes = attributes;
@@ -300,7 +300,7 @@ void Mem::emit() {
 		mem->attributes = attributes;
 		for (auto &port : rd_ports) {
 			if (!port.cell)
-				port.cell = module->addCell(NEW_TWINE, ID($memrd_v2));
+				port.cell = module->addCell(NEW_TWINE, TW::$memrd_v2);
 			port.cell->type_impl = TW::$memrd_v2;
 			port.cell->attributes = port.attributes;
 			port.cell->parameters[ID::MEMID] = memid.str();
@@ -325,7 +325,7 @@ void Mem::emit() {
 		int idx = 0;
 		for (auto &port : wr_ports) {
 			if (!port.cell)
-				port.cell = module->addCell(NEW_TWINE, ID($memwr_v2));
+				port.cell = module->addCell(NEW_TWINE, TW::$memwr_v2);
 			port.cell->type_impl = TW::$memwr_v2;
 			port.cell->attributes = port.attributes;
 			if (port.cell->parameters.count(ID::PRIORITY))
@@ -346,7 +346,7 @@ void Mem::emit() {
 		for (auto &init : inits) {
 			bool v2 = !init.en.is_fully_ones();
 			if (!init.cell)
-				init.cell = module->addCell(NEW_TWINE, v2 ? ID($meminit_v2) : ID($meminit));
+				init.cell = module->addCell(NEW_TWINE, v2 ? TW::$meminit_v2 : TW::$meminit);
 			else {
 				if (!v2)
 					init.cell->unsetPort(TW::EN);
@@ -548,11 +548,11 @@ namespace {
 		dict<IdString, pool<Cell *>> inits;
 		MemIndex (Module *module) {
 			for (auto cell: module->cells()) {
-				if (cell->type.in(ID($memwr), ID($memwr_v2)))
+				if (cell->type.in(TW($memwr), TW($memwr_v2)))
 					wr_ports[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
-				else if (cell->type.in(ID($memrd), ID($memrd_v2)))
+				else if (cell->type.in(TW($memrd), TW($memrd_v2)))
 					rd_ports[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
-				else if (cell->type.in(ID($meminit), ID($meminit_v2)))
+				else if (cell->type.in(TW($meminit), TW($meminit_v2)))
 					inits[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
 			}
 		}
@@ -568,7 +568,7 @@ namespace {
 		if (index.rd_ports.count(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) {
 			for (auto cell : index.rd_ports.at(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) {
 				MemRd mrd;
-				bool is_compat = cell->type == ID($memrd);
+				bool is_compat = cell->type == TW($memrd);
 				mrd.cell = cell;
 				mrd.attributes = cell->attributes;
 				mrd.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
@@ -612,7 +612,7 @@ namespace {
 			std::vector<std::pair<int, MemWr>> ports;
 			for (auto cell : index.wr_ports.at(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) {
 				MemWr mwr;
-				bool is_compat = cell->type == ID($memwr);
+				bool is_compat = cell->type == TW($memwr);
 				mwr.cell = cell;
 				mwr.attributes = cell->attributes;
 				mwr.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
@@ -631,7 +631,7 @@ namespace {
 			}
 			for (int i = 0; i < GetSize(res.wr_ports); i++) {
 				auto &port = res.wr_ports[i];
-				bool is_compat = port.cell->type == ID($memwr);
+				bool is_compat = port.cell->type == TW($memwr);
 				if (is_compat) {
 					port.priority_mask.resize(GetSize(res.wr_ports));
 					for (int j = 0; j < i; j++) {
@@ -667,7 +667,7 @@ namespace {
 					log_error("Non-constant data %s in memory initialization %s.\n", log_signal(data), cell);
 				init.addr = addr.as_const();
 				init.data = data.as_const();
-				if (cell->type == ID($meminit_v2)) {
+				if (cell->type == TW($meminit_v2)) {
 					auto en = cell->getPort(TW::EN);
 					if (!en.is_fully_const())
 						log_error("Non-constant enable %s in memory initialization %s.\n", log_signal(en), cell);
@@ -683,7 +683,7 @@ namespace {
 		}
 		for (int i = 0; i < GetSize(res.rd_ports); i++) {
 			auto &port = res.rd_ports[i];
-			bool is_compat = port.cell->type == ID($memrd);
+			bool is_compat = port.cell->type == TW($memrd);
 			if (is_compat) {
 				port.transparency_mask.resize(GetSize(res.wr_ports));
 				port.collision_x_mask.resize(GetSize(res.wr_ports));
@@ -720,7 +720,7 @@ namespace {
 			cell->parameters.at(ID::OFFSET).as_int(),
 			cell->parameters.at(ID::SIZE).as_int()
 		);
-		bool is_compat = cell->type == ID($mem);
+		bool is_compat = cell->type == TW($mem);
 		int abits = cell->parameters.at(ID::ABITS).as_int();
 		res.packed = true;
 		res.cell = cell;
@@ -860,7 +860,7 @@ std::vector<Mem> Mem::get_all_memories(Module *module) {
 		res.push_back(mem_from_memory(module, it.second, index));
 	}
 	for (auto cell: module->cells()) {
-		if (cell->type.in(ID($mem), ID($mem_v2)))
+		if (cell->type.in(TW($mem), TW($mem_v2)))
 			res.push_back(mem_from_cell(cell));
 	}
 	return res;
@@ -874,7 +874,7 @@ std::vector<Mem> Mem::get_selected_memories(Module *module) {
 			res.push_back(mem_from_memory(module, it.second, index));
 	}
 	for (auto cell: module->selected_cells()) {
-		if (cell->type.in(ID($mem), ID($mem_v2)))
+		if (cell->type.in(TW($mem), TW($mem_v2)))
 			res.push_back(mem_from_cell(cell));
 	}
 	return res;
diff --git a/kernel/modtools.h b/kernel/modtools.h
index c6cee0cf8..4d47b57c2 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -321,7 +321,7 @@ struct ModIndex : public RTLIL::Monitor
 				log("  PRIMARY OUTPUT\n");
 			for (auto &port : it.second.ports)
 				log("  PORT: %s.%s[%d] (%s)\n", port.cell,
-						module->design->twines.str(port.port), port.offset, port.cell->type.unescape());
+						module->design->twines.str(port.port), port.offset, port.cell->module->design->twines.unescaped_str(port.cell->type_impl));
 		}
 	}
 };
@@ -402,11 +402,11 @@ struct ModWalker
 
 	void add_cell(RTLIL::Cell *cell)
 	{
-		if (ct.cell_known(cell->type)) {
+		if (ct.cell_known(cell->type.ref())) {
 			for (auto &conn : cell->connections())
 				add_cell_port(cell, conn.first, sigmap(conn.second),
-						ct.cell_output(cell->type, conn.first),
-						ct.cell_input(cell->type, conn.first));
+						ct.cell_output(cell->type.ref(), conn.first),
+						ct.cell_input(cell->type.ref(), conn.first));
 		} else {
 			for (auto &conn : cell->connections())
 				add_cell_port(cell, conn.first, sigmap(conn.second), true, true);
@@ -436,7 +436,7 @@ struct ModWalker
 		for (auto &it : module->wires_)
 			add_wire(it.second);
 		for (auto &it : module->cells_)
-			if (filter_ct == NULL || filter_ct->cell_known(it.second->type))
+			if (filter_ct == NULL || filter_ct->cell_known(it.second->type.ref()))
 				add_cell(it.second);
 	}
 
diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h
index 8b892262a..be528d32c 100644
--- a/kernel/newcelltypes.h
+++ b/kernel/newcelltypes.h
@@ -555,13 +555,8 @@ struct NewCellType {
 };
 
 struct NewCellTypes {
-	struct IdStringHash {
-		std::size_t operator()(const IdString id) const {
-			return static_cast<size_t>(id.hash_top().yield());
-		}
-	};
 	StaticCellTypes::Categories::Category static_cell_types = StaticCellTypes::categories.empty;
-	std::unordered_map<TwineRef, NewCellType, IdStringHash> custom_cell_types {};
+	dict<TwineRef, NewCellType> custom_cell_types {};
 
 	NewCellTypes() {
 		static_cell_types = StaticCellTypes::categories.empty;
diff --git a/kernel/pmux.h b/kernel/pmux.h
index 6903028ce..cc7e3fa8c 100644
--- a/kernel/pmux.h
+++ b/kernel/pmux.h
@@ -12,7 +12,7 @@ struct PmuxBPortIterator {
     int port_idx;
     int port_count;
     PmuxBPortIterator(Cell* mux) : cell(mux) {
-        log_assert(mux->type == ID($mux) || mux->type == ID($pmux));
+        log_assert(mux->type == TW($mux) || mux->type == TW($pmux));
         port_idx = 0;
         b = mux->getPort(TW::B).to_sigbit_vector();
         
diff --git a/kernel/qcsat.cc b/kernel/qcsat.cc
index c9d00efa1..c90070436 100644
--- a/kernel/qcsat.cc
+++ b/kernel/qcsat.cc
@@ -77,25 +77,25 @@ void QuickConeSat::prepare()
 
 int QuickConeSat::cell_complexity(RTLIL::Cell *cell)
 {
-	if (cell->type.in(ID($concat), ID($slice), ID($pos), ID($buf), ID($_BUF_)))
+	if (cell->type.in(TW($concat), TW($slice), TW($pos), TW($buf), TW($_BUF_)))
 		return 0;
-	if (cell->type.in(ID($not), ID($and), ID($or), ID($xor), ID($xnor),
-			ID($reduce_and), ID($reduce_or), ID($reduce_xor),
-			ID($reduce_xnor), ID($reduce_bool),
-			ID($logic_not), ID($logic_and), ID($logic_or),
-			ID($eq), ID($ne), ID($eqx), ID($nex), ID($fa),
-			ID($mux), ID($pmux), ID($bmux), ID($demux), ID($lut), ID($sop),
-			ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
-			ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
-			ID($_MUX_), ID($_NMUX_), ID($_MUX4_), ID($_MUX8_), ID($_MUX16_),
-			ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
+	if (cell->type.in(TW($not), TW($and), TW($or), TW($xor), TW($xnor),
+			TW($reduce_and), TW($reduce_or), TW($reduce_xor),
+			TW($reduce_xnor), TW($reduce_bool),
+			TW($logic_not), TW($logic_and), TW($logic_or),
+			TW($eq), TW($ne), TW($eqx), TW($nex), TW($fa),
+			TW($mux), TW($pmux), TW($bmux), TW($demux), TW($lut), TW($sop),
+			TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_),
+			TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_),
+			TW($_MUX_), TW($_NMUX_), TW($_MUX4_), TW($_MUX8_), TW($_MUX16_),
+			TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)))
 		return 1;
-	if (cell->type.in(ID($neg), ID($add), ID($sub), ID($alu), ID($lcu),
-			ID($lt), ID($le), ID($gt), ID($ge)))
+	if (cell->type.in(TW($neg), TW($add), TW($sub), TW($alu), TW($lcu),
+			TW($lt), TW($le), TW($gt), TW($ge)))
 		return 2;
-	if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
+	if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
 		return 3;
-	if (cell->type.in(ID($mul), ID($macc), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
+	if (cell->type.in(TW($mul), TW($macc), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow)))
 		return 4;
 	// Unknown cell.
 	return 5;
diff --git a/kernel/register.cc b/kernel/register.cc
index f3d32db12..14d6bace0 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -983,7 +983,7 @@ struct HelpPass : public Pass {
 		for (auto it : StaticCellTypes::builder.cells) {
 			if (!StaticCellTypes::categories.is_known(it.type))
 				continue;
-			auto name = it.type.str();
+			auto name = TW::str(it.type);
 			if (cell_help_messages.contains(name)) {
 				auto cell_help = cell_help_messages.get(name);
 				groups[cell_help.group].emplace_back(name);
@@ -1021,10 +1021,10 @@ struct HelpPass : public Pass {
 			json.name("code"); json.value(ch.code);
 			vector<string> inputs, outputs;
 			for (auto &input : ct.inputs)
-				inputs.push_back(RTLIL::IdString((RTLIL::StaticId)input).str());
+				inputs.push_back(TW::str(input));
 			json.name("inputs"); json.value(inputs);
 			for (auto &output : ct.outputs)
-				outputs.push_back(RTLIL::IdString((RTLIL::StaticId)output).str());
+				outputs.push_back(TW::str(output));
 			json.name("outputs"); json.value(outputs);
 			vector<string> properties;
 			// CellType properties
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 59bf58cd0..135ba7265 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1948,18 +1948,18 @@ bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
 	return false;
 }
 
-RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
+TwineRef RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
 {
 	if (mayfail)
-		return IdString();
+		return Twine::Null;
 	log_error("Module `%s' is used with parameters but is not parametric!\n", design->twines.str(meta_->name).c_str());
 }
 
 
-RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
+TwineRef RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<TwineRef, RTLIL::Module*> &, const dict<TwineRef, TwineRef> &, bool mayfail)
 {
 	if (mayfail)
-		return IdString();
+		return Twine::Null;
 	log_error("Module `%s' is used with parameters but is not parametric!\n", design->twines.str(meta_->name).c_str());
 }
 
@@ -3574,6 +3574,11 @@ TwineRef RTLIL::Module::uniquify(TwineRef name)
 	return uniquify(name, index);
 }
 
+TwineRef RTLIL::Module::uniquify(Twine&& name)
+{
+	return uniquify(design->twines.add(Twine{std::move(name)}));
+}
+
 TwineRef RTLIL::Module::uniquify(TwineRef name, int &index)
 {
 	if (index == 0) {
@@ -3590,6 +3595,11 @@ TwineRef RTLIL::Module::uniquify(TwineRef name, int &index)
 	}
 }
 
+TwineRef RTLIL::Module::uniquify(Twine&& name, int &index)
+{
+	return uniquify(design->twines.add(Twine{std::move(name)}), index);
+}
+
 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 {
 	if (a->port_id && !b->port_id)
@@ -4524,10 +4534,14 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 		return cell;
 	}
 
+	static TwinePool& _cell_adder_twines(RTLIL::Module* m) { return m->design->twines; }
+	static TwinePool& _cell_adder_twines(RTLIL::Patch* p) { return p->mod->design->twines; }
+
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSrGate(Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::S, sig_set);
 		cell->setPort(TW::R, sig_clr);
 		cell->setPort(TW::Q, sig_q);
@@ -4546,7 +4560,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::D, sig_d);
 		cell->setPort(TW::Q, sig_q);
@@ -4556,7 +4571,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::E, sig_en);
 		cell->setPort(TW::D, sig_d);
@@ -4568,7 +4584,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsrGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::S, sig_set);
 		cell->setPort(TW::R, sig_clr);
@@ -4581,7 +4598,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsreGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::S, sig_set);
 		cell->setPort(TW::R, sig_clr);
@@ -4595,7 +4613,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool arst_value, bool clk_polarity, bool arst_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::R, sig_arst);
 		cell->setPort(TW::D, sig_d);
@@ -4607,7 +4626,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::R, sig_arst);
 		cell->setPort(TW::E, sig_en);
@@ -4620,7 +4640,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_ALDFF_%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_ALDFF_%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::L, sig_aload);
 		cell->setPort(TW::D, sig_d);
@@ -4633,7 +4654,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_ALDFFE_%c%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_ALDFFE_%c%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::L, sig_aload);
 		cell->setPort(TW::E, sig_en);
@@ -4647,7 +4669,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool srst_value, bool clk_polarity, bool srst_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::R, sig_srst);
 		cell->setPort(TW::D, sig_d);
@@ -4659,7 +4682,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffeGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::R, sig_srst);
 		cell->setPort(TW::E, sig_en);
@@ -4672,7 +4696,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffceGate(Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::C, sig_clk);
 		cell->setPort(TW::R, sig_srst);
 		cell->setPort(TW::E, sig_en);
@@ -4684,7 +4709,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::E, sig_en);
 		cell->setPort(TW::D, sig_d);
 		cell->setPort(TW::Q, sig_q);
@@ -4695,7 +4721,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdlatchGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool arst_value, bool en_polarity, bool arst_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::E, sig_en);
 		cell->setPort(TW::R, sig_arst);
 		cell->setPort(TW::D, sig_d);
@@ -4707,7 +4734,8 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
 	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchsrGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, TwineRef src)
 	{
-		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), Twine{stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')});
+		TwineRef _t = _cell_adder_twines(static_cast<Derived*>(this)).add(Twine{stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')});
+		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _t);
 		cell->setPort(TW::E, sig_en);
 		cell->setPort(TW::S, sig_set);
 		cell->setPort(TW::R, sig_clr);
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f2abf2495..318086b10 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -743,7 +743,7 @@ constexpr int lookup_well_known_id(std::string_view name)
 	return -1;
 }
 
-// Create a statically allocated IdString object, using for example ID::A or ID($add).
+// Create a statically allocated IdString object, using for example ID::A or TW($add).
 //
 // Recipe for Converting old code that is using conversion of strings like ID::A and
 // "$add" for creating IdStrings: Run below SED command on the .cc file and then use for
@@ -3026,7 +3026,7 @@ public:
 	Module();
 	virtual ~Module();
 	virtual TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);
-	virtual TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
+	virtual TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<TwineRef, RTLIL::Module*> &interfaces, const dict<TwineRef, TwineRef> &modports, bool mayfail = false);
 	virtual size_t count_id(TwineRef id);
 	virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
 	virtual bool reprocess_if_necessary(RTLIL::Design *design);
@@ -3158,7 +3158,9 @@ public:
 	void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
 
 	TwineRef uniquify(TwineRef name);
+	TwineRef uniquify(Twine&& name);
 	TwineRef uniquify(TwineRef name, int &index);
+	TwineRef uniquify(Twine&& name, int &index);
 
 	// Primary overloads: name already interned in design->twines.
 	RTLIL::Wire *addWire(TwineRef name, int width = 1);
@@ -3171,6 +3173,7 @@ public:
 	RTLIL::Cell *addCell(TwineRef name, TwineRef type);
 	RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other);
 	// Convenience.
+	RTLIL::Cell *addCell(Twine name, Twine type);
 	RTLIL::Cell *addCell(Twine &&name, TwineRef type);
 	RTLIL::Cell *addCell(TwineRef name, Twine &&type);
 	RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index c7c6f05c5..901e7848e 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -81,7 +81,7 @@ struct RTLIL::SigNormIndex
 		dict<Wire *, Cell *> input_port_cells;
 
 		for (auto cell : module->cells()) {
-			if (cell->type != ID($input_port))
+			if (cell->type != TW($input_port))
 				continue;
 
 			auto const &sig_y = cell->getPort(TW::Y);
@@ -98,7 +98,7 @@ struct RTLIL::SigNormIndex
 		for (auto portname : module->ports) {
 			Wire *wire = module->wire(portname);
 			if (wire->port_input && !wire->port_output && !input_port_cells.count(wire)) {
-				Cell *cell = module->addCell(NEW_TWINE, ID($input_port));
+				Cell *cell = module->addCell(NEW_TWINE, TW::$input_port);
 				cell->setParam(ID::WIDTH, GetSize(wire));
 				cell->setPort(TW::Y, wire);
 				input_port_cells.emplace(wire, cell);
@@ -195,7 +195,7 @@ struct RTLIL::SigNormIndex
 		}
 
 		if (!connect_lhs.empty()) {
-			Cell *cell = module->addCell(NEW_TWINE, ID($connect));
+			Cell *cell = module->addCell(NEW_TWINE, TW::$connect);
 			xlog("add connect (1) %s\n", cell->name);
 			cell->setParam(ID::WIDTH, GetSize(connect_lhs));
 			cell->setPort(TW::A, std::move(connect_lhs));
@@ -355,7 +355,7 @@ void RTLIL::Design::sigNormalize(bool enable)
 			// TODO inefficient?
 			std::vector<Cell*> cells_snapshot = module->cells();
 			for (auto cell : cells_snapshot) {
-				if (cell->type == ID($input_port))
+				if (cell->type == TW($input_port))
 					module->remove(cell);
 			}
 		}
@@ -560,12 +560,12 @@ void RTLIL::Module::bufNormalize()
 		// Ensure that every enqueued input port is represented by a cell
 		for (auto wire : buf_norm_wire_queue) {
 			if (wire->port_input && !wire->port_output) {
-				if (wire->driverCell_ != nullptr && wire->driverCell_->type != ID($input_port)) {
+				if (wire->driverCell_ != nullptr && wire->driverCell_->type != TW($input_port)) {
 					wire->driverCell_ = nullptr;
 					wire->driverPort_ = Twine::Null;
 				}
 				if (wire->driverCell_ == nullptr) {
-					Cell *input_port_cell = addCell(NEW_TWINE, ID($input_port));
+					Cell *input_port_cell = addCell(NEW_TWINE, TW::$input_port);
 					input_port_cell->setParam(ID::WIDTH, GetSize(wire));
 					input_port_cell->setPort(TW::Y, wire); // this hits the fast path that doesn't mutate the queues
 				}
@@ -621,7 +621,7 @@ void RTLIL::Module::bufNormalize()
 				if (chunk.is_wire())
 					wire_queue_entries(chunk.wire);
 
-			if (cell->type == ID($buf) && cell->attributes.empty() && !cell->name.isPublic()) {
+			if (cell->type == TW($buf) && cell->attributes.empty() && !cell->name.isPublic()) {
 				// For a plain `$buf` cell, we enqueue all wires on its input
 				// side, bypass it using module level connections (skipping 'z
 				// bits) and then remove the cell. Eventually the module level
@@ -662,7 +662,7 @@ void RTLIL::Module::bufNormalize()
 				log_assert(GetSize(buf_norm_wire_queue) <= 1);
 				buf_norm_wire_queue.clear();
 				return;
-			} else if (cell->type == ID($input_port)) {
+			} else if (cell->type == TW($input_port)) {
 				log_assert(port == TW::Y);
 				if (sig.is_wire()) {
 					Wire *w = sig.as_wire();
@@ -744,7 +744,7 @@ void RTLIL::Module::bufNormalize()
 					break;
 				while (!found->second.empty()) {
 					Cell *connect_cell = *found->second.begin();
-					log_assert(connect_cell->type == ID($connect));
+					log_assert(connect_cell->type == TW($connect));
 					SigSpec const &sig_a = connect_cell->getPort(TW::A);
 					SigSpec const &sig_b = connect_cell->getPort(TW::B);
 					xlog("found $connect cell %s: %s <-> %s\n", connect_cell, log_signal(sig_a), log_signal(sig_b));
@@ -769,7 +769,7 @@ void RTLIL::Module::bufNormalize()
 		// As a first step for re-normalization we add all require intermediate
 		// wires for cell output and inout ports.
 		for (auto &[cell, port] : pending_ports) {
-			log_assert(cell->type != ID($input_port));
+			log_assert(cell->type != TW($input_port));
 			log_assert(!cell->type.empty());
 			log_assert(!pending_deleted_cells.count(cell));
 			SigSpec const &sig = cell->getPort(port);
@@ -848,7 +848,7 @@ void RTLIL::Module::bufNormalize()
 			auto const &[cell, port] = cellport;
 			for (int i = 0; i != GetSize(wire); ++i) {
 				SigBit driver = sigmap(SigBit(wire, i));
-				if (cell->type == ID($tribuf) || cell->port_dir(port) == RTLIL::PD_INOUT) {
+				if (cell->type == TW($tribuf) || cell->port_dir(port) == RTLIL::PD_INOUT) {
 					// We add inout drivers to `driven` in a separate loop below
 					weakly_driven.insert(driver);
 				} else {
@@ -947,7 +947,7 @@ void RTLIL::Module::bufNormalize()
 			if (sig_a.empty())
 				return;
 			xlog("connect %s <-> %s\n", log_signal(sig_a), log_signal(sig_b));
-			Cell *connect_cell = addCell(NEW_TWINE, ID($connect));
+			Cell *connect_cell = addCell(NEW_TWINE, TW::$connect);
 			connect_cell->setParam(ID::WIDTH, GetSize(sig_a));
 			connect_cell->setPort(TW::A, sig_a);
 			connect_cell->setPort(TW::B, sig_b);
@@ -1066,7 +1066,7 @@ void RTLIL::Cell::unsetPort(TwineRef portname)
 				}
 			}
 
-			if (type == ID($connect)) {
+			if (type == TW($connect)) {
 				for (auto &[port, sig] : connections_) {
 					for (auto &chunk : sig.chunks()) {
 						if (!chunk.wire)
@@ -1097,7 +1097,7 @@ void RTLIL::Cell::unsetPort(TwineRef portname)
 
 static bool ignored_cell(const RTLIL::IdString& type)
 {
-	return type == ID($specify2) || type == ID($specify3) || type == ID($specrule);
+	return type == TW($specify2) || type == TW($specify3) || type == TW($specrule);
 }
 
 void RTLIL::Cell::signorm_index_remove(TwineRef portname, const SigSpec &old_signal, bool is_input)
@@ -1167,7 +1167,7 @@ bool RTLIL::Cell::bufnorm_handle_setPort(TwineRef portname, SigSpec &signal, dic
 	if ((dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) && signal.is_wire()) {
 		Wire *w = signal.as_wire();
 		if (w->driverCell_ == nullptr &&
-				(w->port_input && !w->port_output) == (type == ID($input_port))) {
+				(w->port_input && !w->port_output) == (type == TW($input_port))) {
 			w->driverCell_ = this;
 			w->driverPort_ = portname;
 			conn_it->second = std::move(signal);
@@ -1184,7 +1184,7 @@ bool RTLIL::Cell::bufnorm_handle_setPort(TwineRef portname, SigSpec &signal, dic
 				module->buf_norm_wire_queue.insert(chunk.wire);
 	}
 
-	if (type == ID($connect)) {
+	if (type == TW($connect)) {
 		for (auto &[port, sig] : connections_) {
 			for (auto &chunk : sig.chunks()) {
 				if (!chunk.wire) continue;
@@ -1229,7 +1229,7 @@ void RTLIL::Cell::initIndex()
 			if ((dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) && signal.is_wire()) {
 				Wire *w = signal.as_wire();
 				if (w->driverCell_ == nullptr &&
-						(w->port_input && !w->port_output) == (type == ID($input_port))) {
+						(w->port_input && !w->port_output) == (type == TW($input_port))) {
 					w->driverCell_ = this;
 					w->driverPort_ = portname;
 					continue;
diff --git a/kernel/satgen.cc b/kernel/satgen.cc
index fedcc26f8..af250f630 100644
--- a/kernel/satgen.cc
+++ b/kernel/satgen.cc
@@ -26,9 +26,9 @@ USING_YOSYS_NAMESPACE
 bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 {
 	bool arith_undef_handled = false;
-	bool is_arith_compare = cell->type.in(ID($lt), ID($le), ID($ge), ID($gt));
+	bool is_arith_compare = cell->type.in(TW($lt), TW($le), TW($ge), TW($gt));
 
-	if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)) || is_arith_compare))
+	if (model_undef && (cell->type.in(TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor)) || is_arith_compare))
 	{
 		std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
@@ -42,7 +42,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
 		int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
 
-		if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+		if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 			std::vector<int> b = importSigSpec(cell->getPort(TW::B), timestep);
 			undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
 		}
@@ -59,8 +59,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		arith_undef_handled = true;
 	}
 
-	if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
-			ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub)))
+	if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_),
+			TW($and), TW($or), TW($xor), TW($xnor), TW($add), TW($sub)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -69,25 +69,25 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
-		if (cell->type.in(ID($and), ID($_AND_)))
+		if (cell->type.in(TW($and), TW($_AND_)))
 			ez->assume(ez->vec_eq(ez->vec_and(a, b), yy));
-		if (cell->type == ID($_NAND_))
+		if (cell->type == TW($_NAND_))
 			ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy));
-		if (cell->type.in(ID($or), ID($_OR_)))
+		if (cell->type.in(TW($or), TW($_OR_)))
 			ez->assume(ez->vec_eq(ez->vec_or(a, b), yy));
-		if (cell->type == ID($_NOR_))
+		if (cell->type == TW($_NOR_))
 			ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy));
-		if (cell->type.in(ID($xor), ID($_XOR_)))
+		if (cell->type.in(TW($xor), TW($_XOR_)))
 			ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy));
-		if (cell->type.in(ID($xnor), ID($_XNOR_)))
+		if (cell->type.in(TW($xnor), TW($_XNOR_)))
 			ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy));
-		if (cell->type == ID($_ANDNOT_))
+		if (cell->type == TW($_ANDNOT_))
 			ez->assume(ez->vec_eq(ez->vec_and(a, ez->vec_not(b)), yy));
-		if (cell->type == ID($_ORNOT_))
+		if (cell->type == TW($_ORNOT_))
 			ez->assume(ez->vec_eq(ez->vec_or(a, ez->vec_not(b)), yy));
-		if (cell->type == ID($add))
+		if (cell->type == TW($add))
 			ez->assume(ez->vec_eq(ez->vec_add(a, b), yy));
-		if (cell->type == ID($sub))
+		if (cell->type == TW($sub))
 			ez->assume(ez->vec_eq(ez->vec_sub(a, b), yy));
 
 		if (model_undef && !arith_undef_handled)
@@ -97,30 +97,30 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
 			extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
 
-			if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) {
+			if (cell->type.in(TW($and), TW($_AND_), TW($_NAND_))) {
 				std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a));
 				std::vector<int> b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b));
 				std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0)));
 				ez->assume(ez->vec_eq(yX, undef_y));
 			}
-			else if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_))) {
+			else if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_))) {
 				std::vector<int> a1 = ez->vec_and(a, ez->vec_not(undef_a));
 				std::vector<int> b1 = ez->vec_and(b, ez->vec_not(undef_b));
 				std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a1, b1)));
 				ez->assume(ez->vec_eq(yX, undef_y));
 			}
-			else if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
+			else if (cell->type.in(TW($xor), TW($xnor), TW($_XOR_), TW($_XNOR_))) {
 				std::vector<int> yX = ez->vec_or(undef_a, undef_b);
 				ez->assume(ez->vec_eq(yX, undef_y));
 			}
-			else if (cell->type == ID($_ANDNOT_)) {
+			else if (cell->type == TW($_ANDNOT_)) {
 				std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a));
 				std::vector<int> b1 = ez->vec_and(b, ez->vec_not(undef_b));
 				std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b1)));
 				ez->assume(ez->vec_eq(yX, undef_y));
 			}
 
-			else if (cell->type == ID($_ORNOT_)) {
+			else if (cell->type == TW($_ORNOT_)) {
 				std::vector<int> a1 = ez->vec_and(a, ez->vec_not(undef_a));
 				std::vector<int> b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b));
 				std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a1, b0)));
@@ -139,10 +139,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
+	if (cell->type.in(TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)))
 	{
-		bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_));
-		bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_));
+		bool aoi_mode = cell->type.in(TW($_AOI3_), TW($_AOI4_));
+		bool three_mode = cell->type.in(TW($_AOI3_), TW($_OAI3_));
 
 		int a = importDefSigSpec(cell->getPort(TW::A), timestep).at(0);
 		int b = importDefSigSpec(cell->getPort(TW::B), timestep).at(0);
@@ -151,7 +151,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0);
 		int yy = model_undef ? ez->literal() : y;
 
-		if (cell->type.in(ID($_AOI3_), ID($_AOI4_)))
+		if (cell->type.in(TW($_AOI3_), TW($_AOI4_)))
 			ez->assume(ez->IFF(ez->NOT(ez->OR(ez->AND(a, b), ez->AND(c, d))), yy));
 		else
 			ez->assume(ez->IFF(ez->NOT(ez->AND(ez->OR(a, b), ez->OR(c, d))), yy));
@@ -205,7 +205,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($_NOT_), ID($not)))
+	if (cell->type.in(TW($_NOT_), TW($not)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
@@ -224,7 +224,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($bweqx))
+	if (cell->type == TW($bweqx))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -250,7 +250,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_), ID($bwmux)))
+	if (cell->type.in(TW($_MUX_), TW($mux), TW($_NMUX_), TW($bwmux)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -258,9 +258,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
 
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
-		if (cell->type == ID($_NMUX_))
+		if (cell->type == TW($_NMUX_))
 			ez->assume(ez->vec_eq(ez->vec_not(ez->vec_ite(s.at(0), b, a)), yy));
-		else if (cell->type == ID($bwmux))
+		else if (cell->type == TW($bwmux))
 			ez->assume(ez->vec_eq(ez->vec_ite(s, b, a), yy));
 		else
 			ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
@@ -275,7 +275,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
 			std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
 			std::vector<int> yX;
-			if (cell->type == ID($bwmux))
+			if (cell->type == TW($bwmux))
 				yX = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));
 			else
 				yX = ez->vec_ite(undef_s.at(0), undef_ab, ez->vec_ite(s.at(0), undef_b, undef_a));
@@ -285,7 +285,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($bmux))
+	if (cell->type == TW($bmux))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
@@ -333,7 +333,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($demux))
+	if (cell->type == TW($demux))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
@@ -385,7 +385,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($pmux))
+	if (cell->type == TW($pmux))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -431,7 +431,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($pos), ID($buf), ID($neg)))
+	if (cell->type.in(TW($pos), TW($buf), TW($neg)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
@@ -439,7 +439,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
-		if (cell->type.in(ID($pos), ID($buf))) {
+		if (cell->type.in(TW($pos), TW($buf))) {
 			ez->assume(ez->vec_eq(a, yy));
 		} else {
 			std::vector<int> zero(a.size(), ez->CONST_FALSE);
@@ -452,7 +452,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
 			extendSignalWidthUnary(undef_a, undef_y, cell);
 
-			if (cell->type.in(ID($pos), ID($buf))) {
+			if (cell->type.in(TW($pos), TW($buf))) {
 				ez->assume(ez->vec_eq(undef_a, undef_y));
 			} else {
 				int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@@ -465,7 +465,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($connect)))
+	if (cell->type.in(TW($connect)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -485,22 +485,22 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not)))
+	if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($logic_not)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
 
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
-		if (cell->type == ID($reduce_and))
+		if (cell->type == TW($reduce_and))
 			ez->SET(ez->expression(ez->OpAnd, a), yy.at(0));
-		if (cell->type.in(ID($reduce_or), ID($reduce_bool)))
+		if (cell->type.in(TW($reduce_or), TW($reduce_bool)))
 			ez->SET(ez->expression(ez->OpOr, a), yy.at(0));
-		if (cell->type == ID($reduce_xor))
+		if (cell->type == TW($reduce_xor))
 			ez->SET(ez->expression(ez->OpXor, a), yy.at(0));
-		if (cell->type == ID($reduce_xnor))
+		if (cell->type == TW($reduce_xnor))
 			ez->SET(ez->NOT(ez->expression(ez->OpXor, a)), yy.at(0));
-		if (cell->type == ID($logic_not))
+		if (cell->type == TW($logic_not))
 			ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), yy.at(0));
 		for (size_t i = 1; i < y.size(); i++)
 			ez->SET(ez->CONST_FALSE, yy.at(i));
@@ -511,15 +511,15 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
 			int aX = ez->expression(ezSAT::OpOr, undef_a);
 
-			if (cell->type == ID($reduce_and)) {
+			if (cell->type == TW($reduce_and)) {
 				int a0 = ez->expression(ezSAT::OpOr, ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)));
 				ez->assume(ez->IFF(ez->AND(ez->NOT(a0), aX), undef_y.at(0)));
 			}
-			else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+			else if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
 				int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(a, ez->vec_not(undef_a)));
 				ez->assume(ez->IFF(ez->AND(ez->NOT(a1), aX), undef_y.at(0)));
 			}
-			else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+			else if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) {
 				ez->assume(ez->IFF(aX, undef_y.at(0)));
 			} else
 				log_abort();
@@ -532,7 +532,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($logic_and), ID($logic_or)))
+	if (cell->type.in(TW($logic_and), TW($logic_or)))
 	{
 		std::vector<int> vec_a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> vec_b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -543,7 +543,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
-		if (cell->type == ID($logic_and))
+		if (cell->type == TW($logic_and))
 			ez->SET(ez->expression(ez->OpAnd, a, b), yy.at(0));
 		else
 			ez->SET(ez->expression(ez->OpOr, a, b), yy.at(0));
@@ -563,9 +563,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			int aX = ez->expression(ezSAT::OpOr, undef_a);
 			int bX = ez->expression(ezSAT::OpOr, undef_b);
 
-			if (cell->type == ID($logic_and))
+			if (cell->type == TW($logic_and))
 				ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a1, b1)), ez->NOT(a0), ez->NOT(b0)), undef_y.at(0));
-			else if (cell->type == ID($logic_or))
+			else if (cell->type == TW($logic_or))
 				ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a0, b0)), ez->NOT(a1), ez->NOT(b1)), undef_y.at(0));
 			else
 				log_abort();
@@ -578,7 +578,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
+	if (cell->type.in(TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt)))
 	{
 		bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
@@ -588,7 +588,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
-		if (model_undef && cell->type.in(ID($eqx), ID($nex))) {
+		if (model_undef && cell->type.in(TW($eqx), TW($nex))) {
 			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
 			std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
 			extendSignalWidth(undef_a, undef_b, cell, true);
@@ -596,29 +596,29 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			b = ez->vec_or(b, undef_b);
 		}
 
-		if (cell->type == ID($lt))
+		if (cell->type == TW($lt))
 			ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), yy.at(0));
-		if (cell->type == ID($le))
+		if (cell->type == TW($le))
 			ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), yy.at(0));
-		if (cell->type.in(ID($eq), ID($eqx)))
+		if (cell->type.in(TW($eq), TW($eqx)))
 			ez->SET(ez->vec_eq(a, b), yy.at(0));
-		if (cell->type.in(ID($ne), ID($nex)))
+		if (cell->type.in(TW($ne), TW($nex)))
 			ez->SET(ez->vec_ne(a, b), yy.at(0));
-		if (cell->type == ID($ge))
+		if (cell->type == TW($ge))
 			ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), yy.at(0));
-		if (cell->type == ID($gt))
+		if (cell->type == TW($gt))
 			ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), yy.at(0));
 		for (size_t i = 1; i < y.size(); i++)
 			ez->SET(ez->CONST_FALSE, yy.at(i));
 
-		if (model_undef && cell->type.in(ID($eqx), ID($nex)))
+		if (model_undef && cell->type.in(TW($eqx), TW($nex)))
 		{
 			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
 			std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
 			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
 			extendSignalWidth(undef_a, undef_b, cell, true);
 
-			if (cell->type == ID($eqx))
+			if (cell->type == TW($eqx))
 				yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b));
 			else
 				yy.at(0) = ez->OR(yy.at(0), ez->vec_ne(undef_a, undef_b));
@@ -628,7 +628,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 
 			ez->assume(ez->vec_eq(y, yy));
 		}
-		else if (model_undef && cell->type.in(ID($eq), ID($ne)))
+		else if (model_undef && cell->type.in(TW($eq), TW($ne)))
 		{
 			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
 			std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
@@ -662,7 +662,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
+	if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -681,16 +681,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 		std::vector<int> shifted_a;
 
-		if (cell->type.in( ID($shl), ID($sshl)))
+		if (cell->type.in( TW($shl), TW($sshl)))
 			shifted_a = ez->vec_shift_left(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
 
-		if (cell->type == ID($shr))
+		if (cell->type == TW($shr))
 			shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
 
-		if (cell->type == ID($sshr))
+		if (cell->type == TW($sshr))
 			shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
 
-		if (cell->type.in(ID($shift), ID($shiftx)))
+		if (cell->type.in(TW($shift), TW($shiftx)))
 			shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
 
 		ez->assume(ez->vec_eq(shifted_a, yy));
@@ -702,7 +702,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
 			std::vector<int> undef_a_shifted;
 
-			extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
+			extend_bit = cell->type == TW($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
 			if (cell->parameters[ID::A_SIGNED].as_bool())
 				extend_bit = undef_a.back();
 
@@ -711,19 +711,19 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			while (undef_y.size() > undef_a.size())
 				undef_a.push_back(extend_bit);
 
-			if (cell->type.in(ID($shl), ID($sshl)))
+			if (cell->type.in(TW($shl), TW($sshl)))
 				undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
 
-			if (cell->type == ID($shr))
+			if (cell->type == TW($shr))
 				undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
 
-			if (cell->type == ID($sshr))
+			if (cell->type == TW($sshr))
 				undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
 
-			if (cell->type == ID($shift))
+			if (cell->type == TW($shift))
 				undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
 
-			if (cell->type == ID($shiftx))
+			if (cell->type == TW($shiftx))
 				undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
 
 			int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
@@ -734,7 +734,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($mul))
+	if (cell->type == TW($mul))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -761,7 +761,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($macc), ID($macc_v2)))
+	if (cell->type.in(TW($macc), TW($macc_v2)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
@@ -811,7 +811,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
 			std::vector<int> undef_c;
 
-			if (cell->type == ID($macc_v2))
+			if (cell->type == TW($macc_v2))
 				undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep);
 
 			int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@@ -830,7 +830,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))
+	if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -878,14 +878,14 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			floored_eq_trunc = ez->CONST_TRUE;
 		}
 
-		if (cell->type == ID($div)) {
+		if (cell->type == TW($div)) {
 			if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
 				ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
 			else
 				ez->assume(ez->vec_eq(y_tmp, y_u));
-		} else if (cell->type == ID($mod)) {
+		} else if (cell->type == TW($mod)) {
 			ez->assume(ez->vec_eq(y_tmp, modulo_trunc));
-		} else if (cell->type == ID($divfloor)) {
+		} else if (cell->type == TW($divfloor)) {
 			if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
 				ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(
 					ez->XOR(a.back(), b.back()),
@@ -898,7 +898,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 				)));
 			else
 				ez->assume(ez->vec_eq(y_tmp, y_u));
-		} else if (cell->type == ID($modfloor)) {
+		} else if (cell->type == TW($modfloor)) {
 			ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(floored_eq_trunc, modulo_trunc, ez->vec_add(modulo_trunc, b))));
 		}
 
@@ -906,7 +906,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 			ez->assume(ez->expression(ezSAT::OpOr, b));
 		} else {
 			std::vector<int> div_zero_result;
-			if (cell->type.in(ID($div), ID($divfloor))) {
+			if (cell->type.in(TW($div), TW($divfloor))) {
 				if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
 					std::vector<int> all_ones(y.size(), ez->CONST_TRUE);
 					std::vector<int> only_first_one(y.size(), ez->CONST_FALSE);
@@ -916,7 +916,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 					div_zero_result.insert(div_zero_result.end(), cell->getPort(TW::A).size(), ez->CONST_TRUE);
 					div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
 				}
-			} else if (cell->type.in(ID($mod), ID($modfloor))) {
+			} else if (cell->type.in(TW($mod), TW($modfloor))) {
 				// a mod 0 = a
 				int copy_a_bits = min(cell->getPort(TW::A).size(), cell->getPort(TW::B).size());
 				div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
@@ -936,7 +936,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($lut))
+	if (cell->type == TW($lut))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
@@ -986,7 +986,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($sop))
+	if (cell->type == TW($sop))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0);
@@ -1068,7 +1068,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($fa))
+	if (cell->type == TW($fa))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -1104,7 +1104,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($lcu))
+	if (cell->type == TW($lcu))
 	{
 		std::vector<int> p = importDefSigSpec(cell->getPort(TW::P), timestep);
 		std::vector<int> g = importDefSigSpec(cell->getPort(TW::G), timestep);
@@ -1136,7 +1136,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($alu))
+	if (cell->type == TW($alu))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
@@ -1202,7 +1202,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($slice))
+	if (cell->type == TW($slice))
 	{
 		RTLIL::SigSpec a = cell->getPort(TW::A);
 		RTLIL::SigSpec y = cell->getPort(TW::Y);
@@ -1210,7 +1210,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($concat))
+	if (cell->type == TW($concat))
 	{
 		RTLIL::SigSpec a = cell->getPort(TW::A);
 		RTLIL::SigSpec b = cell->getPort(TW::B);
@@ -1223,7 +1223,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (timestep > 0 && (cell->is_builtin_ff() || cell->type == ID($anyinit)))
+	if (timestep > 0 && (cell->is_builtin_ff() || cell->type == TW($anyinit)))
 	{
 		FfData ff(nullptr, cell);
 
@@ -1303,7 +1303,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($anyconst))
+	if (cell->type == TW($anyconst))
 	{
 		if (timestep < 2) {
 			if (model_undef && def_formal) {
@@ -1335,7 +1335,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($anyseq))
+	if (cell->type == TW($anyseq))
 	{
 		if (model_undef && def_formal) {
 			std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Y), timestep);
@@ -1345,7 +1345,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($_BUF_), ID($equiv)))
+	if (cell->type.in(TW($_BUF_), TW($equiv)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
@@ -1364,7 +1364,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($initstate))
+	if (cell->type == TW($initstate))
 	{
 		auto key = make_pair(prefix, timestep);
 		if (initstates.count(key) == 0)
@@ -1383,7 +1383,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($assert))
+	if (cell->type == TW($assert))
 	{
 		std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
 		asserts_a[pf].append((*sigmap)(cell->getPort(TW::A)));
@@ -1391,7 +1391,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($assume))
+	if (cell->type == TW($assume))
 	{
 		std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
 		assumes_a[pf].append((*sigmap)(cell->getPort(TW::A)));
@@ -1399,7 +1399,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
+	if (cell->type.in(TW($scopeinfo), TW($input_port), TW($output_port), TW($public)))
 	{
 		return true;
 	}
@@ -1415,9 +1415,9 @@ void report_missing_model(bool warn_only, RTLIL::Cell* cell)
 {
 	std::string s;
 	if (cell->is_builtin_ff())
-		s = stringf("No SAT model available for async FF cell %s (%s).  Consider running `async2sync` or `clk2fflogic` first.\n", cell, cell->type.unescape());
+		s = stringf("No SAT model available for async FF cell %s (%s).  Consider running `async2sync` or `clk2fflogic` first.\n", cell, cell->type.unescaped());
 	else
-		s = stringf("No SAT model available for cell %s (%s).\n", cell, cell->type.unescape());
+		s = stringf("No SAT model available for cell %s (%s).\n", cell, cell->type.unescaped());
 
 	if (warn_only) {
 		log_formatted_warning_noprefix(s);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 722433d62..e9a979f8f 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -102,7 +102,7 @@ struct SatGen
 				else
 					vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
 			} else {
-				std::string wire_name = bit.wire->name.unescape();
+				std::string wire_name = bit.wire->module->design->twines.unescaped_str(bit.wire->meta_->name);
 				std::string name = pf +
 					(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name, bit.offset));
 				vec.push_back(ez->frozen_literal(name));
diff --git a/kernel/scopeinfo.cc b/kernel/scopeinfo.cc
index aac83d564..4557c8441 100644
--- a/kernel/scopeinfo.cc
+++ b/kernel/scopeinfo.cc
@@ -55,7 +55,7 @@ void ModuleHdlnameIndex::index_cells()
 void ModuleHdlnameIndex::index_scopeinfo_cells()
 {
 	auto cells = module->cells();
-	index_items(cells.begin(), cells.end(), [](Cell *cell) { return cell->type == ID($scopeinfo); });
+	index_items(cells.begin(), cells.end(), [](Cell *cell) { return cell->type == TW($scopeinfo); });
 }
 
 std::vector<std::string> ModuleHdlnameIndex::scope_sources(Cursor cursor)
@@ -69,7 +69,7 @@ std::vector<std::string> ModuleHdlnameIndex::scope_sources(Cursor cursor)
 			continue;
 		}
 		Cell *cell = cursor.entry().cell();
-		if (cell == nullptr || cell->type != ID($scopeinfo)) {
+		if (cell == nullptr || cell->type != TW($scopeinfo)) {
 			result.push_back("");
 			result.push_back("");
 			continue;
@@ -99,14 +99,14 @@ static const char *attr_prefix(ScopeinfoAttrs attrs)
 
 bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id)
 {
-	log_assert(scopeinfo->type == ID($scopeinfo));
-	return scopeinfo->has_attribute(attr_prefix(attrs) + id.unescape());
+	log_assert(scopeinfo->type == TW($scopeinfo));
+	return scopeinfo->has_attribute(attr_prefix(attrs) + design->twines.unescaped_str(id));
 }
 
 RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id)
 {
-	log_assert(scopeinfo->type == ID($scopeinfo));
-	auto found = scopeinfo->attributes.find(attr_prefix(attrs) + id.unescape());
+	log_assert(scopeinfo->type == TW($scopeinfo));
+	auto found = scopeinfo->attributes.find(attr_prefix(attrs) + design->twines.unescaped_str(id));
 	if (found == scopeinfo->attributes.end())
 		return RTLIL::Const();
 	return found->second;
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 845e9a1f2..ed9f8c732 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -29,15 +29,15 @@ struct TimingInfo
 {
 	struct NameBit
 	{
-		RTLIL::IdString name;
+		TwineRef name;
 		int offset;
 		NameBit() : offset(0) {}
-		NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
-		explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
+		NameBit(TwineRef name, int offset) : name(name), offset(offset) {}
+		explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->meta_->name), offset(b.offset) {}
 		bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
 		bool operator!=(const NameBit& nb) const { return !operator==(nb); }
 		std::optional<SigBit> get_connection(RTLIL::Cell *cell) {
-			TwineRef port_name = cell->module->design->twines.lookup(name.str());
+			TwineRef port_name = name;
 			if (!cell->hasPort(port_name))
 				return {};
 			auto &port = cell->getPort(port_name);
@@ -71,7 +71,7 @@ struct TimingInfo
 		bool has_inputs;
 	};
 
-	dict<RTLIL::IdString, ModuleTiming> data;
+	dict<TwineRef, ModuleTiming> data;
 
 	TimingInfo()
 	{
@@ -93,12 +93,12 @@ struct TimingInfo
 
 	const ModuleTiming& setup_module(RTLIL::Module *module)
 	{
-		auto r = data.insert(RTLIL::IdString(module->design->twines.str(module->meta_->name)));
+		auto r = data.insert(module->meta_->name);
 		log_assert(r.second);
 		auto &t = r.first->second;
 
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($specify2)) {
+			if (cell->type == TW($specify2)) {
 				auto en = cell->getPort(TW::EN);
 				if (en.is_fully_const() && !en.as_bool())
 					continue;
@@ -136,7 +136,7 @@ struct TimingInfo
 					}
 				}
 			}
-			else if (cell->type == ID($specify3)) {
+			else if (cell->type == TW($specify3)) {
 				auto src = cell->getPort(TW::SRC).as_bit();
 				auto dst = cell->getPort(TW::DST);
 				if (!src.wire || !src.wire->port_input)
@@ -160,9 +160,9 @@ struct TimingInfo
 					}
 				}
 			}
-			else if (cell->type == ID($specrule)) {
+			else if (cell->type == TW($specrule)) {
 				IdString type = cell->getParam(ID::TYPE).decode_string();
-				if (type != ID($setup) && type != ID($setuphold))
+				if (type != TW($setup) && type != TW($setuphold))
 					continue;
 				auto src = cell->getPort(TW::SRC);
 				auto dst = cell->getPort(TW::DST).as_bit();
@@ -198,10 +198,10 @@ struct TimingInfo
 		return t;
 	}
 
-	decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
+	decltype(data)::const_iterator find(TwineRef module_name) const { return data.find(module_name); }
 	decltype(data)::const_iterator end() const { return data.end(); }
-	int count(RTLIL::IdString module_name) const { return data.count(module_name); }
-	const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
+	int count(TwineRef module_name) const { return data.count(module_name); }
+	const ModuleTiming& at(TwineRef module_name) const { return data.at(module_name); }
 };
 
 YOSYS_NAMESPACE_END
diff --git a/kernel/twine.h b/kernel/twine.h
index 98dda3439..48f2b17ff 100644
--- a/kernel/twine.h
+++ b/kernel/twine.h
@@ -91,6 +91,20 @@ struct TW {
 
 		throw "unknown twine id";
 	}
+
+	static constexpr const char* static_names[] = {
+#define X(N) #N,
+#include "kernel/constids.inc"
+#undef X
+	};
+
+	static std::string str(TwineRef ref) {
+		TwineRef idx = ref.untag();
+		if (idx.value >= STATIC_TWINE_END) return {};
+		std::string result = ref.is_public() ? "\\" : "";
+		result += static_names[idx.value];
+		return result;
+	}
 };
 
 #define TW(id) (size_t)lookup_well_known_id(#id)
@@ -102,7 +116,6 @@ struct Twine {
 	struct Suffix {
 		TwineRef prefix;
 		std::string tail;
-		// TODO check
 		auto operator<=>(const Suffix&) const = default;
 	};
 
diff --git a/kernel/unstable/patch.h b/kernel/unstable/patch.h
index f22a8d9cc..beebffb23 100644
--- a/kernel/unstable/patch.h
+++ b/kernel/unstable/patch.h
@@ -76,9 +76,9 @@ public:
 
 	RTLIL::Cell *addCell(TwineRef name, TwineRef type);
 	RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other);
+	RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
 	RTLIL::Cell *addCell(Twine &&name, TwineRef type);
 	RTLIL::Cell *addCell(TwineRef name, Twine &&type);
-	RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
 
 	// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
 	// Returned refs are twine_staging-local and die at the next commit.
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 4b9dce1e9..68471ef7f 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -964,7 +964,7 @@ static char *readline_obj_generator(const char *text, int state)
 			RTLIL::Module *module = design->module(design->selected_active_module);
 
 			for (auto w : module->wires())
-				if (w->name.unescape().compare(0, len, text) == 0)
+				if (design->twines.unescaped_str(w->meta_->name).compare(0, len, text) == 0)
 					obj_names.push_back(strdup(w->name.unescape().c_str()));
 
 			for (auto &it : module->memories) {
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 587963095..3a89fc0cd 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -50,7 +50,7 @@ OBJS += passes/cmds/xprop.o
 OBJS += passes/cmds/dft_tag.o
 OBJS += passes/cmds/future.o
 OBJS += passes/cmds/box_derive.o
-OBJS += passes/cmds/example_dt.o
+#OBJS += passes/cmds/example_dt.o
 OBJS += passes/cmds/portarcs.o
 OBJS += passes/cmds/wrapcell.o
 OBJS += passes/cmds/setenv.o
diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc
index e344385e1..f0d73681f 100644
--- a/passes/cmds/abstract.cc
+++ b/passes/cmds/abstract.cc
@@ -174,7 +174,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
 	std::vector<FfData> ffs;
 	// Abstract flop inputs if they're driving a selected output rep
 	for (auto cell : mod->cells()) {
-		if (!ct.cell_types.count(cell->type))
+		if (!ct.cell_types.count(cell->type_impl))
 			continue;
 		FfData ff(nullptr, cell);
 		if (ff.has_sr)
@@ -265,7 +265,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
 	unsigned int changed = 0;
 	std::vector<Cell*> cells_snapshot = mod->cells();
 	for (auto cell : cells_snapshot) {
-		if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+		if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 			continue;
 		for (auto conn : cell->connections())
 			if (cell->output(conn.first)) {
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 864156b1c..6b44ea161 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -42,7 +42,8 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
 		log_error("Could not find wire with name \"%s\".\n", name);
 	}
 	else {
-		RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype);
+		TwineRef _type = module->design->twines.add(Twine{"$" + celltype});
+		RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, _type);
 		formal_cell->setPort(TW::A, wire);
 		if(enable_name == "") {
 			formal_cell->setPort(TW::EN, State::S1);
diff --git a/passes/cmds/box_derive.cc b/passes/cmds/box_derive.cc
index 87509bb5a..62aedcf28 100644
--- a/passes/cmds/box_derive.cc
+++ b/passes/cmds/box_derive.cc
@@ -100,7 +100,7 @@ struct BoxDerivePass : Pass {
 					continue;
 
 				if (!done.count(index)) {
-					IdString derived_type = base->derive(d, cell->parameters);
+					TwineRef derived_type = base->derive(d, cell->parameters);
 					Module *derived = d->module(derived_type);
 					log_assert(derived && "Failed to derive module\n");
 					log("derived %s\n", derived_type);
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index 759b83d5a..ea6772e07 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -87,7 +87,7 @@ int check_bufnorm_wire(RTLIL::Module *module, RTLIL::Wire *wire)
 			if (!dsig.is_wire() || dsig.as_wire() != wire)
 				log_warning("bufNorm: wire %s.%s driverCell_ %s port %s does not connect back to this wire\n",
 					log_id(module), log_id(wire), log_id(driver), module->design->twines.str(dport).c_str()), counter++;
-			if (wire->port_input && !wire->port_output && driver->type != ID($input_port))
+			if (wire->port_input && !wire->port_output && driver->type != TW($input_port))
 				log_warning("bufNorm: module input wire %s.%s is driven by non-$input_port cell %s of type %s\n",
 					log_id(module), log_id(wire), log_id(driver), log_id(driver->type)), counter++;
 		}
@@ -295,14 +295,14 @@ struct CheckPass : public Pass {
 					// Only those cell types for which the edge data can expode quadratically
 					// in port widths are those for us to check.
 					if (!cell->type.in(
-							ID($add), ID($sub),
-							ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
-							ID($pmux), ID($bmux)))
+							TW($add), TW($sub),
+							TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx),
+							TW($pmux), TW($bmux)))
 						return false;
 
 					int in_widths = 0, out_widths = 0;
 
-					if (cell->type.in(ID($pmux), ID($bmux))) {
+					if (cell->type.in(TW($pmux), TW($bmux))) {
 						// We're skipping inputs A and B, since each of their bits contributes only one edge
 						in_widths = GetSize(cell->getPort(TW::S));
 						out_widths = GetSize(cell->getPort(TW::Y));
@@ -358,17 +358,17 @@ struct CheckPass : public Pass {
 			pool<Cell *> coarsened_cells;
 			for (auto cell : module->cells())
 			{
-				if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+				if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 					continue;
 
 				if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
-					if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
-					log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescape());
+					if (allow_tbuf && cell->type == TW($_TBUF_)) goto cell_allowed;
+					log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescaped());
 					counter++;
 				cell_allowed:;
 				}
 
-				if (cell->type == ID($connect)) {
+				if (cell->type == TW($connect)) {
 					// Inefficient, but rare case in sane design
 					auto sig_a = cell->getPort(TW::A);
 					auto sig_b = cell->getPort(TW::B);
@@ -406,13 +406,13 @@ struct CheckPass : public Pass {
 						wire_drivers_count[bit]++;
 						if (output && (bit.wire || !input))
 							wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", cell->module->design->twines.str(conn.first).c_str(), i,
-																cell, cell->type.unescape()));
+																cell, cell->type.unescaped()));
 						if (output)
 							driver_cells[bit] = cell;
 					}
 				}
 
-				if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
+				if (yosys_celltypes.cell_evaluable(cell->type.ref()) || cell->type.in(TW($mem_v2), TW($memrd), TW($memrd_v2)) \
 						|| cell->is_builtin_ff()) {
 					if (!edges_db.add_edges_from_cell(cell))
 						coarsened_cells.insert(cell);
@@ -529,7 +529,7 @@ struct CheckPass : public Pass {
 						driver_src = stringf(" source: %s", src_attr);
 					}
 
-					message += stringf("    cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src);
+					message += stringf("    cell %s (%s)%s\n", driver, design->twines.unescaped_str(driver->type), driver_src);
 
 					if (!coarsened_cells.count(driver)) {						
 						MatchingEdgePrinter printer(message, sigmap, prev, bit);
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc
index faff0ec7b..c7b41da85 100644
--- a/passes/cmds/chformal.cc
+++ b/passes/cmds/chformal.cc
@@ -24,42 +24,42 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static RTLIL::IdString formal_flavor(RTLIL::Cell *cell)
+static TwineRef formal_flavor(RTLIL::Cell *cell)
 {
-	if (cell->type != ID($check))
-		return cell->type;
+	if (cell->type != TW($check))
+		return cell->type_impl;
 
 	std::string flavor_param = cell->getParam(ID(FLAVOR)).decode_string();
 	if (flavor_param == "assert")
-		return ID($assert);
+		return TW($assert);
 	else if (flavor_param == "assume")
-		return ID($assume);
+		return TW($assume);
 	else if (flavor_param == "cover")
-		return ID($cover);
+		return TW($cover);
 	else if (flavor_param == "live")
-		return ID($live);
+		return TW($live);
 	else if (flavor_param == "fair")
-		return ID($fair);
+		return TW($fair);
 	else
 		log_abort();
 }
 
-static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor)
+static void set_formal_flavor(RTLIL::Cell *cell, TwineRef flavor)
 {
-	if (cell->type != ID($check)) {
-		cell->type_impl = cell->module->design->twines.add(Twine{flavor.str()});
+	if (cell->type != TW($check)) {
+		cell->type_impl = flavor;
 		return;
 	}
 
-	if (flavor == ID($assert))
+	if (flavor == TW($assert))
 		cell->setParam(ID(FLAVOR), std::string("assert"));
-	else if (flavor == ID($assume))
+	else if (flavor == TW($assume))
 		cell->setParam(ID(FLAVOR), std::string("assume"));
-	else if (flavor == ID($cover))
+	else if (flavor == TW($cover))
 		cell->setParam(ID(FLAVOR), std::string("cover"));
-	else if (flavor == ID($live))
+	else if (flavor == TW($live))
 		cell->setParam(ID(FLAVOR), std::string("live"));
-	else if (flavor == ID($fair))
+	else if (flavor == TW($fair))
 		cell->setParam(ID(FLAVOR), std::string("fair"));
 	else
 		log_abort();
@@ -67,7 +67,7 @@ static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor)
 
 static bool is_triggered_check_cell(RTLIL::Cell * cell)
 {
-	return cell->type == ID($check) && cell->getParam(ID(TRG_ENABLE)).as_bool();
+	return cell->type == TW($check) && cell->getParam(ID(TRG_ENABLE)).as_bool();
 }
 
 struct ChformalPass : public Pass {
@@ -136,7 +136,7 @@ struct ChformalPass : public Pass {
 		bool live2fair = false;
 		bool fair2live = false;
 
-		pool<IdString> constr_types;
+		pool<TwineRef> constr_types;
 		char mode = 0;
 		int mode_arg = 0;
 
@@ -144,23 +144,23 @@ struct ChformalPass : public Pass {
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
 			if (args[argidx] == "-assert") {
-				constr_types.insert(ID($assert));
+				constr_types.insert(TW($assert));
 				continue;
 			}
 			if (args[argidx] == "-assume") {
-				constr_types.insert(ID($assume));
+				constr_types.insert(TW($assume));
 				continue;
 			}
 			if (args[argidx] == "-live") {
-				constr_types.insert(ID($live));
+				constr_types.insert(TW($live));
 				continue;
 			}
 			if (args[argidx] == "-fair") {
-				constr_types.insert(ID($fair));
+				constr_types.insert(TW($fair));
 				continue;
 			}
 			if (args[argidx] == "-cover") {
-				constr_types.insert(ID($cover));
+				constr_types.insert(TW($cover));
 				continue;
 			}
 			if (mode == 0 && args[argidx] == "-remove") {
@@ -222,11 +222,11 @@ struct ChformalPass : public Pass {
 		design->sigNormalize(false);
 
 		if (constr_types.empty()) {
-			constr_types.insert(ID($assert));
-			constr_types.insert(ID($assume));
-			constr_types.insert(ID($live));
-			constr_types.insert(ID($fair));
-			constr_types.insert(ID($cover));
+			constr_types.insert(TW($assert));
+			constr_types.insert(TW($assume));
+			constr_types.insert(TW($live));
+			constr_types.insert(TW($fair));
+			constr_types.insert(TW($cover));
 		}
 
 		if (assert2assume && assert2cover) {
@@ -274,13 +274,13 @@ struct ChformalPass : public Pass {
 
 				for (auto cell : module->selected_cells())
 				{
-					if (cell->type == ID($ff)) {
+					if (cell->type == TW($ff)) {
 						SigSpec D = sigmap(cell->getPort(TW::D));
 						SigSpec Q = sigmap(cell->getPort(TW::Q));
 						for (int i = 0; i < GetSize(D); i++)
 							ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
 					}
-					if (cell->type == ID($dff)) {
+					if (cell->type == TW($dff)) {
 						SigSpec D = sigmap(cell->getPort(TW::D));
 						SigSpec Q = sigmap(cell->getPort(TW::Q));
 						SigSpec C = sigmap(cell->getPort(TW::CLK));
@@ -301,7 +301,7 @@ struct ChformalPass : public Pass {
 						cell->setParam(ID::TRG_POLARITY, false);
 					}
 
-					IdString flavor = formal_flavor(cell);
+					TwineRef flavor = formal_flavor(cell);
 
 					while (true)
 					{
@@ -312,8 +312,8 @@ struct ChformalPass : public Pass {
 							break;
 
 						if (!init_zero.count(EN)) {
-							if (flavor == ID($cover)) break;
-							if (flavor.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
+							if (flavor == TW($cover)) break;
+							if (flavor.in(TW($assert), TW($assume)) && !init_one.count(A)) break;
 						}
 
 						const auto &A_map = ffmap.at(A);
@@ -372,8 +372,8 @@ struct ChformalPass : public Pass {
 			{
 				for (auto cell : constr_cells)
 				{
-					if (cell->type == ID($check)) {
-						Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), ID($check));
+					if (cell->type == TW($check)) {
+						Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), TW::$check);
 						cover->attributes = cell->attributes;
 						if (cell->src_id() != Twine::Null && module->design)
 							cover->set_src_id(cell->src_id());
@@ -395,24 +395,24 @@ struct ChformalPass : public Pass {
 			if (mode == 'c')
 			{
 				for (auto cell : constr_cells) {
-					IdString flavor = formal_flavor(cell);
-					if (assert2assume && flavor == ID($assert))
-						set_formal_flavor(cell, ID($assume));
-					if (assert2cover && flavor == ID($assert))
-						set_formal_flavor(cell, ID($cover));
-					else if (assume2assert && flavor == ID($assume))
-						set_formal_flavor(cell, ID($assert));
-					else if (live2fair && flavor == ID($live))
-						set_formal_flavor(cell, ID($fair));
-					else if (fair2live && flavor == ID($fair))
-						set_formal_flavor(cell, ID($live));
+					TwineRef flavor = formal_flavor(cell);
+					if (assert2assume && flavor == TW($assert))
+						set_formal_flavor(cell, TW($assume));
+					if (assert2cover && flavor == TW($assert))
+						set_formal_flavor(cell, TW($cover));
+					else if (assume2assert && flavor == TW($assume))
+						set_formal_flavor(cell, TW($assert));
+					else if (live2fair && flavor == TW($live))
+						set_formal_flavor(cell, TW($fair));
+					else if (fair2live && flavor == TW($fair))
+						set_formal_flavor(cell, TW($live));
 				}
 			}
 			else
 			if (mode == 'l')
 			{
 				for (auto cell : constr_cells) {
-					if (cell->type != ID($check))
+					if (cell->type != TW($check))
 						continue;
 
 					if (is_triggered_check_cell(cell))
@@ -431,7 +431,7 @@ struct ChformalPass : public Pass {
 					plain_cell->setPort(TW::A, sig_a);
 					plain_cell->setPort(TW::EN, sig_en);
 
-					if (plain_cell->type.in(ID($assert), ID($assume)))
+					if (plain_cell->type.in(TW($assert), TW($assume)))
 						sig_a = module->Not(NEW_TWINE, sig_a);
 
 					SigBit combined_en = module->And(NEW_TWINE, sig_a, sig_en);
diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc
index 615daf437..24b27cf39 100644
--- a/passes/cmds/clean_zerowidth.cc
+++ b/passes/cmds/clean_zerowidth.cc
@@ -66,7 +66,7 @@ struct CleanZeroWidthPass : public Pass {
 		{
 			for (auto cell : module->selected_cells())
 			{
-				if (!ct.cell_known(cell->type)) {
+				if (!ct.cell_known(cell->type_impl)) {
 					// User-defined cell: just prune zero-width connections.
 					for (auto it: cell->connections()) {
 						if (GetSize(it.second) == 0) {
@@ -80,7 +80,7 @@ struct CleanZeroWidthPass : public Pass {
 					if (GetSize(cell->getPort(TW::Q)) == 0) {
 						module->remove(cell);
 					}
-				} else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) {
+				} else if (cell->type.in(TW($pmux), TW($bmux), TW($demux))) {
 					// Remove altogether if WIDTH is 0, replace with
 					// a connection if S_WIDTH is 0.
 					if (cell->getParam(ID::WIDTH).as_int() == 0) {
@@ -90,7 +90,7 @@ struct CleanZeroWidthPass : public Pass {
 						module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
 						module->remove(cell);
 					}
-				} else if (cell->type == ID($concat)) {
+				} else if (cell->type == TW($concat)) {
 					// If a concat has a zero-width input: replace with direct
 					// connection to the other input.
 					if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
@@ -100,17 +100,17 @@ struct CleanZeroWidthPass : public Pass {
 						module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
 						module->remove(cell);
 					}
-				} else if (cell->type == ID($fsm)) {
+				} else if (cell->type == TW($fsm)) {
 					// TODO: not supported
 				} else if (cell->is_mem_cell()) {
 					// Skip — will be handled below.
-				} else if (cell->type == ID($lut)) {
+				} else if (cell->type == TW($lut)) {
 					// Zero-width LUT is just a const driver.
 					if (cell->getParam(ID::WIDTH).as_int() == 0) {
 						module->connect(cell->getPort(TW::Y), cell->getParam(ID::LUT)[0]);
 						module->remove(cell);
 					}
-				} else if (cell->type == ID($sop)) {
+				} else if (cell->type == TW($sop)) {
 					// Zero-width SOP is just a const driver.
 					if (cell->getParam(ID::WIDTH).as_int() == 0) {
 						// The value is 1 iff DEPTH is non-0.
@@ -128,7 +128,7 @@ struct CleanZeroWidthPass : public Pass {
 					// A and B to 1-bit if their width is 0.
 					if (cell->getParam(ID::Y_WIDTH).as_int() == 0) {
 						module->remove(cell);
-					} else if (cell->type.in(ID($macc), ID($macc_v2))) {
+					} else if (cell->type.in(TW($macc), TW($macc_v2))) {
 						// TODO: fixing zero-width A and B not supported.
 					} else {
 						if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index 2c77ac5ac..44f1d5c5c 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -36,7 +36,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 
 	for (auto cell : module->cells())
 	for (auto &port : cell->connections_)
-		if (ct.cell_output(cell->type, port.first))
+		if (ct.cell_output(cell->type.ref(), port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 
 	bool need_fixup = false;
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 805b6425e..c30b77c63 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -268,7 +268,7 @@ struct DesignPass : public Pass {
 			{
 				log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
 
-				RTLIL::Module *t = mod->clone(copy_to_design, RTLIL::IdString(prefix));
+				RTLIL::Module *t = mod->clone(copy_to_design, copy_to_design->twines.add(Twine{prefix}));
 				t->attributes.erase(ID::top);
 
 				queue.insert(t);
@@ -297,7 +297,7 @@ struct DesignPass : public Pass {
 						if (copy_to_design->module(trg_name) != nullptr)
 							copy_to_design->remove(copy_to_design->module(trg_name));
 
-						RTLIL::Module *t = fmod->clone(copy_to_design, RTLIL::IdString(trg_name));
+						RTLIL::Module *t = fmod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
 						t->attributes.erase(ID::top);
 
 						queue.insert(t);
@@ -321,7 +321,7 @@ struct DesignPass : public Pass {
 				if (copy_to_design->module(trg_name) != nullptr)
 					copy_to_design->remove(copy_to_design->module(trg_name));
 
-				mod->clone(copy_to_design, RTLIL::IdString(trg_name));
+				mod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
 			}
 		}
 
diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc
index 8e4fdb67a..f07558ea0 100644
--- a/passes/cmds/dft_tag.cc
+++ b/passes/cmds/dft_tag.cc
@@ -90,10 +90,10 @@ struct DftTagWorker {
 		bool design_changed = false;
 
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($overwrite_tag))
+			if (cell->type == TW($overwrite_tag))
 				overwrite_cells.push_back(cell);
 
-			if (cell->type == ID($original_tag))
+			if (cell->type == TW($original_tag))
 				original_cells.push_back(cell);
 		}
 
@@ -137,7 +137,7 @@ struct DftTagWorker {
 		if (found == modwalker.signal_consumers.end())
 			return;
 		for (auto &consumer : found->second) {
-			if (consumer.cell->type.in(ID($original_tag)))
+			if (consumer.cell->type.in(TW($original_tag)))
 				continue;
 			if (sigmap(consumer.cell->getPort(consumer.port)[consumer.offset]) != driver_bit)
 				continue;
@@ -249,7 +249,7 @@ struct DftTagWorker {
 	void propagate_tags()
 	{
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($set_tag)) {
+			if (cell->type == TW($set_tag)) {
 				pending_cells.insert(cell);
 				pending_cell_queue.push_back(cell);
 			}
@@ -371,7 +371,7 @@ struct DftTagWorker {
 
 	void propagate_tags(Cell *cell)
 	{
-		if (cell->type == ID($set_tag)) {
+		if (cell->type == TW($set_tag)) {
 			IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
 			if (all_tags.insert(tag).second) {
 				auto group_sep = tag.str().find(':');
@@ -388,25 +388,25 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type == ID($get_tag)) {
+		if (cell->type == TW($get_tag)) {
 			return;
 		}
 
-		if (cell->type.in(ID($not), ID($pos))) {
+		if (cell->type.in(TW($not), TW($pos))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
-			if (cell->type.in(ID($not), ID($or))) {
+			if (cell->type.in(TW($not), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			}
 			forward_tags(sig_y, sig_a);
 			return;
 		}
 
-		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
+		if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($bweqx))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
+			if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -415,13 +415,13 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($mux), ID($bwmux))) {
+		if (cell->type.in(TW($mux), TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
 			auto sig_s = cell->getPort(TW::S);
 
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
 
 			forward_tags(sig_y, sig_a);
@@ -430,7 +430,7 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 
 			if (ff.has_clk || ff.has_gclk)
@@ -440,10 +440,10 @@ struct DftTagWorker {
 
 		// Single output but, sensitive to all inputs
 		if (cell->type.in(
-			ID($le), ID($lt), ID($ge), ID($gt),
-			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
-			ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
-			ID($eq), ID($ne)
+			TW($le), TW($lt), TW($ge), TW($gt),
+			TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor),
+			TW($reduce_bool), TW($logic_not), TW($logic_or), TW($logic_and),
+			TW($eq), TW($ne)
 		)) {
 			auto &sig_y = cell->getPort(TW::Y);
 
@@ -456,10 +456,10 @@ struct DftTagWorker {
 		add_tags(cell, tags(cell));
 
 		if (cell->type.in(
-			ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_),
-			ID($_XOR_), ID($_XNOR_), ID($_NOT_), ID($_BUF_), ID($_MUX_),
+			TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_),
+			TW($_XOR_), TW($_XNOR_), TW($_NOT_), TW($_BUF_), TW($_MUX_),
 
-			ID($assert), ID($assume)
+			TW($assert), TW($assume)
 		)) {
 			return;
 		}
@@ -477,7 +477,7 @@ struct DftTagWorker {
 
 	void process_cell(IdString tag, Cell *cell)
 	{
-		if (cell->type == ID($set_tag)) {
+		if (cell->type == TW($set_tag)) {
 			IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
 
 			auto tag_sig_a = tag_signal(tag, cell->getPort(TW::A));
@@ -494,14 +494,14 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type == ID($get_tag)) {
+		if (cell->type == TW($get_tag)) {
 			log_assert(false);
 		}
 
-		if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
+		if (cell->type.in(TW($not), TW($pos), TW($_NOT_), TW($_BUF_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
-			if (cell->type.in(ID($not), ID($or))) {
+			if (cell->type.in(TW($not), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			}
 			emit_tag_signal(tag, sig_y, tag_signal(tag, sig_a));
@@ -509,13 +509,13 @@ struct DftTagWorker {
 		}
 
 		if (cell->type.in(
-			ID($and), ID($or),
-			ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
+			TW($and), TW($or),
+			TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_)
 		)) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($and), ID($or))) {
+			if (cell->type.in(TW($and), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -523,9 +523,9 @@ struct DftTagWorker {
 			bool inv_a = false;
 			bool inv_b = false;
 
-			if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
+			if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
 				inv_a ^= true, inv_b ^= true;
-			if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+			if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 				inv_b ^= true;
 
 			if (inv_a)
@@ -554,11 +554,11 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
+		if (cell->type.in(TW($xor), TW($xnor), TW($bweqx), TW($_XOR_), TW($_XNOR_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($xor), ID($xnor))) {
+			if (cell->type.in(TW($xor), TW($xnor))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -572,13 +572,13 @@ struct DftTagWorker {
 		}
 
 
-		if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
+		if (cell->type.in(TW($_MUX_), TW($mux), TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
 			auto sig_s = cell->getPort(TW::S);
 
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
 
 			auto group_sig_a = tag_group_signal(tag, sig_a);
@@ -606,7 +606,7 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
+		if (cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -635,7 +635,7 @@ struct DftTagWorker {
 		}
 
 
-		if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
+		if (cell->type.in(TW($lt), TW($gt), TW($le), TW($ge))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -643,7 +643,7 @@ struct DftTagWorker {
 			sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
 			sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
 
-			if (cell->type.in(ID($gt), ID($le)))
+			if (cell->type.in(TW($gt), TW($le)))
 				std::swap(sig_a, sig_b);
 
 			auto group_sig_a = tag_group_signal(tag, sig_a);
@@ -666,14 +666,14 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+		if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 
 			auto group_sig_a = tag_group_signal(tag, sig_a);
 			auto tag_sig_a = tag_signal(tag, sig_a);
 
-			if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
+			if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($logic_not)))
 				sig_a = autoNot(NEW_TWINE, sig_a);
 
 			auto filled = autoOr(NEW_TWINE, sig_a, group_sig_a);
@@ -686,12 +686,12 @@ struct DftTagWorker {
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 			// TODO handle some more variants
 			if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
 				if (ff.has_clk && !tags(ff.sig_clk).empty())
-					log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type.unescape());
+					log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type);
 
 				int width = ff.width;
 
@@ -709,7 +709,7 @@ struct DftTagWorker {
 				emit_tag_signal(tag, sig_q, ff.sig_q);
 				return;
 			} else {
-				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
+				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type);
 
 				// For unhandled FFs, the default propagation would cause combinational loops
 				emit_tag_signal(tag, ff.sig_q, Const(0, ff.width));
@@ -739,7 +739,7 @@ struct DftTagWorker {
 		// which is an over-approximation (unless the cell is a module that
 		// generates tags itself in which case it could be arbitrary).
 		if (warned_cells.insert(cell).second)
-			log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type.unescape());
+			log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type);
 	}
 
 	void emit_tags()
@@ -747,7 +747,7 @@ struct DftTagWorker {
 		warned_cells.clear();
 		std::vector<Cell *> get_tag_cells;
 		for (auto cell : module->selected_cells())
-			if (cell->type == ID($get_tag))
+			if (cell->type == TW($get_tag))
 				get_tag_cells.push_back(cell);
 
 		for (auto cell : get_tag_cells) {
@@ -798,13 +798,13 @@ struct DftTagWorker {
 		std::vector<Cell *> get_tag_cells;
 		std::vector<Cell *> set_tag_cells;
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($get_tag))
+			if (cell->type == TW($get_tag))
 				get_tag_cells.push_back(cell);
 
-			if (cell->type == ID($set_tag))
+			if (cell->type == TW($set_tag))
 				set_tag_cells.push_back(cell);
 
-			log_assert(!cell->type.in(ID($overwrite_tag), ID($original_tag)));
+			log_assert(!cell->type.in(TW($overwrite_tag), TW($original_tag)));
 		}
 
 		for (auto cell : set_tag_cells) {
diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc
index c3f63b42a..1fbd07b45 100644
--- a/passes/cmds/edgetypes.cc
+++ b/passes/cmds/edgetypes.cc
@@ -92,12 +92,12 @@ struct EdgetypePass : public Pass {
 				auto sink_bit_index = std::get<2>(sink);
 
 				string source_str = multibit_ports.count(std::pair<IdString, TwineRef>(source_cell_type, source_port_name)) ?
-						stringf("%s.%s[%d]", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str(), source_bit_index) :
-						stringf("%s.%s", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str());
+						stringf("%s.%s[%d]", design->twines.unescaped_str(source_cell_type), module->design->twines.str(source_port_name).c_str(), source_bit_index) :
+						stringf("%s.%s", design->twines.unescaped_str(source_cell_type), module->design->twines.str(source_port_name).c_str());
 
 				string sink_str = multibit_ports.count(std::pair<IdString, TwineRef>(sink_cell_type, sink_port_name)) ?
-						stringf("%s.%s[%d]", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str(), sink_bit_index) :
-						stringf("%s.%s", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str());
+						stringf("%s.%s[%d]", design->twines.unescaped_str(sink_cell_type), module->design->twines.str(sink_port_name).c_str(), sink_bit_index) :
+						stringf("%s.%s", design->twines.unescaped_str(sink_cell_type), module->design->twines.str(sink_port_name).c_str());
 
 				edge_cache.insert(source_str + " " + sink_str);
 			}
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
index 17e09ca59..ffb5bee22 100644
--- a/passes/cmds/example_dt.cc
+++ b/passes/cmds/example_dt.cc
@@ -77,13 +77,13 @@ struct ExampleDtPass : public Pass
 			auto enqueue = [&](DriveSpec const &spec) {
 				int index = queue(spec);
 				if (index == GetSize(graph_nodes))
-					graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index());
+					graph_nodes.emplace_back(compute_graph.add(TW($pending), index).index());
 				//if (index >= GetSize(graph_nodes))
 				return compute_graph[graph_nodes[index]];
 			};
 
 			for (auto cell : module->cells()) {
-				if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
+				if (cell->type.in(TW($assert), TW($assume), TW($cover), TW($check)))
 					enqueue(DriveBitMarker(cells(cell), 0));
 			}
 
@@ -99,7 +99,7 @@ struct ExampleDtPass : public Pass
 				ExampleGraph::Ref node = compute_graph[i];
 
 				if (spec.chunks().size() > 1) {
-					node.set_function(ID($$concat));
+					node.set_function(TW($$concat));
 
 					for (auto const &chunk : spec.chunks()) {
 						node.append_arg(enqueue(chunk));
@@ -111,39 +111,39 @@ struct ExampleDtPass : public Pass
 						if (wire_chunk.is_whole()) {
 							node.sparse_attr() = wire_chunk.wire->name;
 							if (wire_chunk.wire->port_input) {
-								node.set_function(ExampleFn(ID($$input), {{wire_chunk.wire->name, {}}}));
+								node.set_function(ExampleFn(TW($$input), {{wire_chunk.wire->name, {}}}));
 							} else {
 								DriveSpec driver = dm(DriveSpec(wire_chunk));
-								node.set_function(ID($$buf));
+								node.set_function(TW($$buf));
 
 								node.append_arg(enqueue(driver));
 							}
 						} else {
 							DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
-							node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
+							node.set_function(ExampleFn(TW($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}}));
 							node.append_arg(enqueue(whole_wire));
 						}
 					} else if (chunk.is_port()) {
 						DriveChunkPort port_chunk = chunk.port();
 						if (port_chunk.is_whole()) {
-							if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
-								if (port_chunk.cell->type.in(ID($dff), ID($ff)))
+							if (dm.celltypes.cell_output(port_chunk.cell->type_impl, port_chunk.port)) {
+								if (port_chunk.cell->type.in(TW($dff), TW($ff)))
 								{
 									Cell *cell = port_chunk.cell;
-									node.set_function(ExampleFn(ID($$state), {{cell->name, {}}}));
+									node.set_function(ExampleFn(TW($$state), {{cell->name, {}}}));
 									for (auto const &conn : cell->connections()) {
-										if (!dm.celltypes.cell_input(cell->type, conn.first))
+										if (!dm.celltypes.cell_input(cell->type_impl, conn.first))
 											continue;
 										enqueue(DriveChunkPort(cell, conn)).assign_key(cell->name);
 									}
 								}
 								else
 								{
-									node.set_function(ExampleFn(ID($$cell_output), {{RTLIL::escape_id(module->design->twines.str(port_chunk.port)), {}}}));
+									node.set_function(ExampleFn(TW($$cell_output), {{RTLIL::escape_id(module->design->twines.str(port_chunk.port)), {}}}));
 									node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0)));
 								}
 							} else {
-								node.set_function(ID($$buf));
+								node.set_function(TW($$buf));
 
 								DriveSpec driver = dm(DriveSpec(port_chunk));
 								node.append_arg(enqueue(driver));
@@ -151,14 +151,14 @@ struct ExampleDtPass : public Pass
 
 						} else {
 							DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
-							node.set_function(ExampleFn(ID($$slice), {{ID(offset), port_chunk.offset}}));
+							node.set_function(ExampleFn(TW($$slice), {{ID(offset), port_chunk.offset}}));
 							node.append_arg(enqueue(whole_port));
 						}
 					} else if (chunk.is_constant()) {
-						node.set_function(ExampleFn(ID($$const), {{ID(value), chunk.constant()}}));
+						node.set_function(ExampleFn(TW($$const), {{ID(value), chunk.constant()}}));
 
 					} else if (chunk.is_multiple()) {
-						node.set_function(ID($$multi));
+						node.set_function(TW($$multi));
 						for (auto const &driver : chunk.multiple().multiple())
 							node.append_arg(enqueue(driver));
 					} else if (chunk.is_marker()) {
@@ -166,13 +166,13 @@ struct ExampleDtPass : public Pass
 
 						node.set_function(ExampleFn(cell->type, cell->parameters));
 						for (auto const &conn : cell->connections()) {
-							if (!dm.celltypes.cell_input(cell->type, conn.first))
+							if (!dm.celltypes.cell_input(cell->type_impl, conn.first))
 								continue;
 
 							node.append_arg(enqueue(DriveChunkPort(cell, conn)));
 						}
 					} else if (chunk.is_none()) {
-						node.set_function(ID($$undriven));
+						node.set_function(TW($$undriven));
 
 					} else {
 						log_error("unhandled drivespec: %s\n", log_signal(chunk));
@@ -208,7 +208,7 @@ struct ExampleDtPass : public Pass
 
 			for (int i = 0; i < compute_graph.size(); ++i)
 			{
-				if (compute_graph[i].function().name == ID($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
+				if (compute_graph[i].function().name == TW($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i)
 				{
 
 					alias.push_back(alias[compute_graph[i].arg(0).index()]);
diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc
index cecc6d2e3..3d99eb3b6 100644
--- a/passes/cmds/future.cc
+++ b/passes/cmds/future.cc
@@ -50,7 +50,7 @@ struct FutureWorker {
 
 		std::vector<Cell *> replaced_cells;
 		for (auto cell : module->selected_cells()) {
-			if (cell->type != ID($future_ff))
+			if (cell->type != TW($future_ff))
 				continue;
 
 			module->connect(cell->getPort(TW::Y), future_ff(cell->getPort(TW::A)));
@@ -92,7 +92,7 @@ struct FutureWorker {
 
 		if (!ff.has_clk && !ff.has_gclk)
 			log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
-				  driver.cell->type.unescape());
+				  driver.cell->type);
 
 		ff.unmap_ce_srst();
 
diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc
index 229d72bbd..9dea8cc9c 100644
--- a/passes/cmds/glift.cc
+++ b/passes/cmds/glift.cc
@@ -70,7 +70,7 @@ private:
 
 	void add_precise_GLIFT_logic(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
 		//AKA AN2_SH2 or OR2_SH2
-		bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
+		bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
 		RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_1_1"}, port_a, false, cell->src_ref());
 		RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_1_2"}, port_b, false, cell->src_ref());
 		auto subexpr1 = module->And(Twine{cell->name.str() + "_t_1_3"}, is_and? port_a : n_port_a, port_b_taint, false, cell->src_ref());
@@ -82,7 +82,7 @@ private:
 
 	void add_imprecise_GLIFT_logic_1(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
 		//AKA AN2_SH3 or OR2_SH3
-		bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
+		bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
 		RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_2_1"}, port_a, false, cell->src_ref());
 		auto subexpr1 = module->And(Twine{cell->name.str() + "_t_2_2"}, is_and? port_b : n_port_a, is_and? port_a_taint : port_b_taint, false, cell->src_ref());
 		module->addOr(Twine{cell->name.str() + "_t_2_3"}, is_and? port_b_taint : port_a_taint, subexpr1, port_y_taint, false, cell->src_ref());
@@ -90,7 +90,7 @@ private:
 
 	void add_imprecise_GLIFT_logic_2(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
 		//AKA AN2_SH4 or OR2_SH4
-		bool is_and = cell->type.in(ID($_AND_), ID($_NAND_));
+		bool is_and = cell->type.in(TW($_AND_), TW($_NAND_));
 		RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_3_1"}, port_b, false, cell->src_ref());
 		auto subexpr1 = module->And(Twine{cell->name.str() + "_t_3_2"}, is_and? port_a : n_port_b, is_and? port_b_taint : port_a_taint, false, cell->src_ref());
 		module->addOr(Twine{cell->name.str() + "_t_3_3"}, is_and? port_a_taint : port_b_taint, subexpr1, port_y_taint, false, cell->src_ref());
@@ -150,13 +150,13 @@ private:
 			auto select_width = metamux_select.as_wire()->width;
 
 			std::vector<RTLIL::Const> costs;
-			if (celltype == ID($_AND_) || celltype == ID($_OR_)) {
+			if (celltype == TW($_AND_) || celltype == TW($_OR_)) {
 				costs = {5, 2, 2, 1, 0, 0, 0, 0};
 				log_assert(select_width == 2 || select_width == 3);
 				log_assert(opt_instrumentmore || select_width == 2);
 				log_assert(!opt_instrumentmore || select_width == 3);
 			}
-			else if (celltype == ID($_XOR_) || celltype == ID($_XNOR_)) {
+			else if (celltype == TW($_XOR_) || celltype == TW($_XNOR_)) {
 				costs = {1, 0, 0, 0};
 				log_assert(select_width == 2);
 			}
@@ -184,10 +184,10 @@ private:
 		std::vector<RTLIL::SigSig> connections(module->connections());
 
 		for(auto &cell : module->cells().to_vector()) {
-			if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) {
+			if (!cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_MUX_), TW($_NMUX_), TW($_NOT_), TW($anyconst), TW($allconst), TW($assume), TW($assert)) && module->design->module(cell->type) == nullptr) {
 				log_cmd_error("Unsupported cell type \"%s\" found.  Run `techmap` first.\n", cell->type);
 			}
-			if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
+			if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_))) {
 				const unsigned int A = 0, B = 1, Y = 2;
 				const unsigned int NUM_PORTS = 3;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
@@ -234,7 +234,7 @@ private:
 					auto select_width = log2(num_versions);
 					log_assert(exp2(select_width) == num_versions);
 					RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
-					meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
+					meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
 					module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
 
 					std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
@@ -252,7 +252,7 @@ private:
 				}
 				else log_cmd_error("This is a bug (1).\n");
 			}
-			else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) {
+			else if (cell->type.in(TW($_XOR_), TW($_XNOR_))) {
 				const unsigned int A = 0, B = 1, Y = 2;
 				const unsigned int NUM_PORTS = 3;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
@@ -289,7 +289,7 @@ private:
 					}
 
 					RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width));
-					meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type));
+					meta_mux_selects.push_back(make_pair(meta_mux_select, RTLIL::IdString(cell->type)));
 					module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref()));
 
 					std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
@@ -308,7 +308,7 @@ private:
 				else log_cmd_error("This is a bug (2).\n");
 
 			}
-			else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) {
+			else if (cell->type.in(TW($_MUX_), TW($_NMUX_))) {
 				const unsigned int A = 0, B = 1, S = 2, Y = 3;
 				const unsigned int NUM_PORTS = 4;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)};
@@ -321,7 +321,7 @@ private:
 
 				add_precise_GLIFT_mux(cell, ports[A], port_taints[A], ports[B], port_taints[B], ports[S], port_taints[S], port_taints[Y]);
 			}
-			else if (cell->type.in(ID($_NOT_))) {
+			else if (cell->type.in(TW($_NOT_))) {
 				const unsigned int A = 0, Y = 1;
 				const unsigned int NUM_PORTS = 2;
 				RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)};
@@ -332,7 +332,7 @@ private:
 				for (unsigned int i = 0; i < NUM_PORTS; ++i)
 					port_taints[i] = get_corresponding_taint_signal(ports[i]);
 
-				if (cell->type == ID($_NOT_)) {
+				if (cell->type == TW($_NOT_)) {
 					module->connect(port_taints[Y], port_taints[A]);
 				}
 				else log_cmd_error("This is a bug (3).\n");
diff --git a/passes/cmds/icell_liberty.cc b/passes/cmds/icell_liberty.cc
index b652dc641..86c9030b4 100644
--- a/passes/cmds/icell_liberty.cc
+++ b/passes/cmds/icell_liberty.cc
@@ -63,7 +63,7 @@ struct LibertyStubber {
 		}
 
 		f << "\tcell (\"" << derived_name << "\") {\n";
-		auto& base_type = ct.cell_types[base_name];
+		auto& base_type = ct.cell_types[base->name];
 		i.indent = 3;
 		auto sorted_ports = derived->ports;
 		// Hack for CLK and C coming before Q does
@@ -117,17 +117,17 @@ struct LibertyStubber {
 	}
 	void liberty_cell(Module* base, Module* derived, std::ostream& f)
 	{
-		auto base_name = base->design->twines.str(base->meta_->name).substr(1);
+		auto base_name = base->name.substr(1);
 		auto derived_name = derived->design->twines.str(derived->meta_->name).substr(1);
-		if (!ct.cell_types.count(base_name)) {
+		if (!ct.cell_types.count(base->name)) {
 			log_debug("skip skeleton for %s\n", base_name.c_str());
 			return;
 		}
 
-		if (StaticCellTypes::categories.is_ff(base_name))
+		if (StaticCellTypes::categories.is_ff(base->name))
 			return liberty_flop(base, derived, f);
 
-		auto& base_type = ct.cell_types[base_name];
+		auto& base_type = ct.cell_types[base->name];
 		f << "\tcell (\"" << derived_name << "\") {\n";
 		for (auto x : derived->ports) {
 			std::string port_name = derived->design->twines.str(x);
diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc
index 558c59419..6ff51b67e 100644
--- a/passes/cmds/linecoverage.cc
+++ b/passes/cmds/linecoverage.cc
@@ -95,7 +95,7 @@ struct CoveragePass : public Pass {
 		{
 			log_debug("Module %s:\n", module);
 			for (auto wire: module->wires()) {
-				log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), wire->name.unescape());
+				log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), design->twines.unescaped_str(wire->name));
 				for (auto src: design->src_leaves(wire)) {
 					auto filename = extract_src_filename(src);
 					if (filename.empty()) continue;
diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc
index 303abea6c..a005545bd 100644
--- a/passes/cmds/ltp.cc
+++ b/passes/cmds/ltp.cc
@@ -64,7 +64,7 @@ struct LtpWorker
 						dst_bits.insert(bit);
 				}
 
-			if (noff && ff_celltypes.cell_known(cell->type)) {
+			if (noff && ff_celltypes.cell_known(cell->type_impl)) {
 				for (auto s : src_bits)
 					for (auto d : dst_bits) {
 						bit2ff[s] = tuple<SigBit, Cell*>(d, cell);
diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc
index ebb3055b2..cc56cf7d9 100644
--- a/passes/cmds/portarcs.cc
+++ b/passes/cmds/portarcs.cc
@@ -31,7 +31,7 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit)
 {
 	RTLIL::Wire *w;
 	while ((w = bit.wire) != NULL && !w->port_input &&
-			w->driverCell()->type.in(ID($buf), ID($_BUF_))) {
+			w->driverCell()->type.in(TW($buf), TW($_BUF_))) {
 		bit = w->driverCell()->getPort(TW::A)[bit.offset];
 	}
 	return bit;
@@ -125,10 +125,10 @@ struct PortarcsPass : Pass {
 
 				for (auto cell : m->cells())
 				// Ignore all bufnorm helper cells
-				if (!cell->type.in(ID($buf), ID($input_port), ID($output_port), ID($public), ID($connect), ID($tribuf))) {
+				if (!cell->type.in(TW($buf), TW($input_port), TW($output_port), TW($public), TW($connect), TW($tribuf))) {
 					auto tdata = tinfo.find(cell->type);
 					if (tdata == tinfo.end())
-						log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape());
+						log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescaped());
 					for (auto [edge, delay] : tdata->second.comb) {
 						auto from = edge.first.get_connection(cell);
 						auto to = edge.second.get_connection(cell);
@@ -292,7 +292,7 @@ struct PortarcsPass : Pass {
 					int *p = annotations.at(canonical_bit(bit));
 					for (auto i = 0; i < inputs.size(); i++) {
 						if (p[i] >= 0) {
-							Cell *spec = m->addCell(NEW_TWINE, ID($specify2));
+							Cell *spec = m->addCell(NEW_TWINE, TW($specify2));
 							spec->setParam(ID::SRC_WIDTH, 1);
 							spec->setParam(ID::DST_WIDTH, 1);
 							spec->setParam(ID::T_FALL_MAX, p[i]);
diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc
index 25528431e..b0f3c4841 100644
--- a/passes/cmds/printattrs.cc
+++ b/passes/cmds/printattrs.cc
@@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
 
 	static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
 		if (x.flags & RTLIL::CONST_FLAG_STRING)
-			log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), s.unescape(), x.decode_string());
+			log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), design->twines.unescaped_str(s), x.decode_string());
 		else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
-			log("%s(* %s=%s *)\n", get_indent_str(indent), s.unescape(), x.as_string());
+			log("%s(* %s=%s *)\n", get_indent_str(indent), design->twines.unescaped_str(s), x.as_string());
 		else
 			log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
 	}
@@ -88,7 +88,7 @@ struct PrintAttrsPass : public Pass {
 			}
 
 			for (auto wire : mod->selected_wires()) {
-				log("%s%s\n", get_indent_str(indent), wire->name.unescape());
+				log("%s%s\n", get_indent_str(indent), design->twines.unescaped_str(wire->name));
 				indent += 2;
 				log_src(design, wire, indent);
 				for (auto &it : wire->attributes)
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index bb36ac137..0f1345b6b 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -21,6 +21,7 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 #include "backends/verilog/verilog_backend.h"
+#include "kernel/twine.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -149,11 +150,11 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 			}
 		}
 
-		if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) {
+		if (cell->type.in(TW($anyconst), TW($anyseq), TW($anyinit), TW($allconst), TW($allseq))) {
 			has_witness_signals = true;
 			IdString QY;
 			bool clk2fflogic = false;
-			if (cell->type == ID($anyinit))
+			if (cell->type == TW($anyinit))
 				QY = (clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic))) ? ID::D : ID::Q;
 			else
 				QY = ID::Y;
@@ -179,7 +180,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 		}
 
 
-		if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($live), ID($fair), ID($check))) {
+		if (cell->type.in(TW($assert), TW($assume), TW($cover), TW($live), TW($fair), TW($check))) {
 			has_witness_signals = true;
 			if (cell->name.isPublic())
 				continue;
@@ -386,6 +387,7 @@ struct RenamePass : public Pass {
 		// TODO disable signorm due to rename I think?
 		design->sigNormalize(false);
 
+		TwineSearch search(&design->twines);
 		if (flag_src)
 		{
 			extra_args(args, argidx, design);
@@ -527,14 +529,14 @@ struct RenamePass : public Pass {
 			if (argidx+1 != args.size())
 				log_cmd_error("Invalid number of arguments!\n");
 
-			IdString new_name = RTLIL::escape_id(args[argidx]);
+			TwineRef new_name = design->twines.add(Twine{RTLIL::escape_id(args[argidx])});
 			RTLIL::Module *module = design->top_module();
 
 			if (module == nullptr)
 				log_cmd_error("No top module found!\n");
 
-			log("Renaming module %s to %s.\n", log_id(module), new_name.unescape());
-			design->rename(module, design->twines.add(Twine{new_name.str()}));
+			log("Renaming module %s to %s.\n", log_id(module), design->twines.unescaped_str(new_name));
+			design->rename(module, new_name);
 		}
 		else
 		if (flag_scramble_name)
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index c2f99d792..876a284cd 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -53,7 +53,7 @@ struct ScatterPass : public Pass {
 				for (auto conn : cell->connections())
 					new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second))));
 				for (auto &it : new_connections) {
-					if (ct.cell_output(cell->type, it.first))
+					if (ct.cell_output(cell->type.ref(), it.first))
 						module->connect(RTLIL::SigSig(it.second.first, it.second.second));
 					else
 						module->connect(RTLIL::SigSig(it.second.second, it.second.first));
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 90a2706ea..da2acf4dd 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -117,7 +117,7 @@ struct SccWorker
 			for (auto mod : design->modules())
 				if (mod->get_blackbox_attribute(false))
 					for (auto cell : mod->cells())
-						if (cell->type == ID($specify2))
+						if (cell->type == TW($specify2))
 						{
 							specifyCells.setup_module(mod);
 							break;
@@ -138,18 +138,18 @@ struct SccWorker
 			if (!design->selected(module, cell))
 				continue;
 
-			if (!allCellTypes && !ct.cell_known(cell->type) && !specifyCells.cell_known(cell->type))
+			if (!allCellTypes && !ct.cell_known(cell->type.ref()) && !specifyCells.cell_known(cell->type.ref()))
 				continue;
 
 			workQueue.insert(cell);
 
 			RTLIL::SigSpec inputSignals, outputSignals;
 
-			if (specifyCells.cell_known(cell->type)) {
+			if (specifyCells.cell_known(cell->type.ref())) {
 				// Use specify rules of the type `(X => Y) = NN` to look for asynchronous paths in boxes.
 				for (auto subcell : design->module(cell->type)->cells())
 				{
-					if (subcell->type != ID($specify2))
+					if (subcell->type != TW($specify2))
 						continue;
 
 					for (auto bit : subcell->getPort(TW::SRC))
@@ -171,9 +171,9 @@ struct SccWorker
 				{
 					bool isInput = true, isOutput = true;
 
-					if (ct.cell_known(cell->type)) {
-						isInput = ct.cell_input(cell->type, conn.first);
-						isOutput = ct.cell_output(cell->type, conn.first);
+					if (ct.cell_known(cell->type.ref())) {
+						isInput = ct.cell_input(cell->type.ref(), conn.first);
+						isOutput = ct.cell_output(cell->type.ref(), conn.first);
 					}
 
 					RTLIL::SigSpec sig = selectedSignals.extract(sigmap(conn.second));
diff --git a/passes/cmds/sdc/sdc.cc b/passes/cmds/sdc/sdc.cc
index cb0b074d5..56301108f 100644
--- a/passes/cmds/sdc/sdc.cc
+++ b/passes/cmds/sdc/sdc.cc
@@ -1,3 +1,4 @@
+#include "kernel/twine.h"
 #ifdef YOSYS_ENABLE_TCL
 
 #include "kernel/register.h"
@@ -97,7 +98,7 @@ struct SdcObjects {
 		// constraint-side tracking
 		FullConstraint,
 	} collect_mode;
-	using CellPin = std::pair<Cell*, IdString>;
+	using CellPin = std::pair<Cell*, TwineRef>;
 	Design* design;
 	std::vector<std::pair<std::string, Wire*>> design_ports;
 	std::vector<std::pair<std::string, Cell*>> design_cells;
@@ -149,8 +150,8 @@ struct SdcObjects {
 			path += name;
 			design_cells.push_back(std::make_pair(path, cell));
 			for (auto pin : cell->connections()) {
-				IdString pin_name = pin.first;
-				std::string pin_name_sdc = path + "/" + pin.first.str().substr(1);
+				TwineRef pin_name = pin.first;
+				std::string pin_name_sdc = path + "/" + design->twines.unescaped_str(pin.first);
 				design_pins.push_back(std::make_pair(pin_name_sdc, std::make_pair(cell, pin_name)));
 			}
 			if (auto sub_mod = mod->design->module(cell->type)) {
@@ -168,9 +169,9 @@ struct SdcObjects {
 			RTLIL::Wire *wire = top->wire(port);
 			if (!wire) {
 				// This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573
-				log_error("Port %s doesn't exist", port.unescape());
+				log_error("Port %s doesn't exist", design->twines.unescaped_str(port));
 			}
-			design_ports.push_back(std::make_pair(port.str().substr(1), wire));
+			design_ports.push_back(std::make_pair(design->twines.unescaped_str(port), wire));
 		}
 		std::list<std::string> hierarchy{};
 		sniff_module(hierarchy, top);
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 69966ecb1..424999423 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -17,6 +17,8 @@
  *
  */
 
+#include "kernel/rtlil.h"
+#include "kernel/twine.h"
 #include "kernel/yosys.h"
 #include "kernel/newcelltypes.h"
 #include "kernel/sigtools.h"
@@ -450,7 +452,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 
 	select_all(design, lhs);
 
-	std::vector<RTLIL::IdString> del_list;
+	std::vector<TwineRef> del_list;
 
 	for (auto mod_name : lhs.selected_modules) {
 		if (rhs.selected_whole_module(mod_name))
@@ -471,7 +473,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 			del_list.push_back(it.first);
 			continue;
 		}
-		std::vector<RTLIL::IdString> del_list2;
+		std::vector<TwineRef> del_list2;
 		for (auto &it2 : it.second)
 			if (!rhs.selected_member(it.first, it2))
 				del_list2.push_back(it2);
@@ -487,11 +489,11 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 namespace {
 	struct expand_rule_t {
 		char mode;
-		std::set<RTLIL::IdString> cell_types, port_names;
+		std::set<std::string> cell_types, port_names;
 	};
 }
 
-static int parse_comma_list(std::set<RTLIL::IdString> &tokens, const std::string &str, size_t pos, std::string stopchar)
+static int parse_comma_list(std::set<std::string> &tokens, const std::string &str, size_t pos, std::string stopchar)
 {
 	stopchar += ',';
 	while (1) {
@@ -520,7 +522,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 		auto selected_members = lhs.selected_members[mod->meta_->name];
 
 		for (auto wire : mod->wires())
-			if (lhs.selected_member(mod->meta_->name, wire->meta_->name) && limits.count(wire->meta_->name) == 0)
+			if (lhs.selected_member(mod->meta_->name, wire->meta_->name) && limits.count(RTLIL::IdString(design->twines.str(wire->meta_->name))) == 0)
 				selected_wires.insert(wire);
 
 		for (auto &conn : mod->connections())
@@ -538,17 +540,18 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			}
 		}
 
+		auto twines = design->twines;
 		for (auto cell : mod->cells())
 		for (auto &conn : cell->connections())
 		{
 			char last_mode = '-';
-			if (eval_only && !yosys_celltypes.cell_evaluable(cell->type))
+			if (eval_only && !yosys_celltypes.cell_evaluable(cell->type.ref()))
 				goto exclude_match;
 			for (auto &rule : rules) {
 				last_mode = rule.mode;
-				if (rule.cell_types.size() > 0 && rule.cell_types.count(cell->type) == 0)
+				if (rule.cell_types.size() > 0 && rule.cell_types.count(twines.unescaped_str(cell->type_impl)) == 0)
 					continue;
-				if (rule.port_names.size() > 0 && rule.port_names.count(conn.first) == 0)
+				if (rule.port_names.size() > 0 && rule.port_names.count(twines.unescaped_str(conn.first)) == 0)
 					continue;
 				if (rule.mode == '+')
 					goto include_match;
@@ -558,16 +561,16 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			if (last_mode == '+')
 				goto exclude_match;
 		include_match:
-			is_input = mode == 'x' || ct.cell_input(cell->type, conn.first);
-			is_output = mode == 'x' || ct.cell_output(cell->type, conn.first);
+			is_input = mode == 'x' || ct.cell_input(cell->type.ref(), conn.first);
+			is_output = mode == 'x' || ct.cell_output(cell->type.ref(), conn.first);
 			for (auto &chunk : conn.second.chunks())
 				if (chunk.wire != nullptr) {
-					if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell->name) == 0)
+					if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell->name.ref()) == 0)
 						if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
-							lhs.selected_members[mod->name].insert(cell->name), sel_objects++, max_objects--;
-					if (max_objects != 0 && selected_members.count(cell->name) > 0 && limits.count(cell->name) == 0 && selected_members.count(chunk.wire->name) == 0)
+							lhs.selected_members[mod->meta_->name].insert(cell->name.ref()), sel_objects++, max_objects--;
+					if (max_objects != 0 && selected_members.count(cell->name.ref()) > 0 && limits.count(cell->name) == 0 && selected_members.count(chunk.wire->name.ref()) == 0)
 						if (mode == 'x' || (mode == 'i' && is_input) || (mode == 'o' && is_output))
-							lhs.selected_members[mod->name].insert(chunk.wire->name), sel_objects++, max_objects--;
+							lhs.selected_members[mod->meta_->name].insert(chunk.wire->name.ref()), sel_objects++, max_objects--;
 				}
 		exclude_match:;
 		}
@@ -634,7 +637,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
 					if (design->selection_vars.count(str) > 0) {
 						for (auto i1 : design->selection_vars.at(str).selected_members)
 						for (auto i2 : i1.second)
-							limits.insert(i2);
+							limits.insert(RTLIL::IdString(design->twines.str(i2)));
 					} else
 						log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str));
 				} else
@@ -682,7 +685,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
 
 static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
 {
-	if (design->selected_active_module.empty())
+	if (!design->selected_active_module)
 		return;
 
 	if (sel.full_selection) {
@@ -691,7 +694,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
 		return;
 	}
 
-	std::vector<RTLIL::IdString> del_list;
+	std::vector<TwineRef> del_list;
 	for (auto mod_name : sel.selected_modules)
 		if (mod_name != design->selected_active_module)
 			del_list.push_back(mod_name);
@@ -845,8 +848,8 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 		select_blackboxes = true;
 	}
 
-	if (!design->selected_active_module.empty()) {
-		arg_mod = design->selected_active_module;
+	if (design->selected_active_module) {
+		arg_mod = design->twines.str(design->selected_active_module);
 		arg_memb = arg;
 		if (!isprefixed(arg_memb))
 			arg_memb_found[arg_memb] = false;
@@ -898,29 +901,29 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 			arg_mod_found[arg_mod] = true;
 
 		if (arg_memb == "") {
-			sel.selected_modules.insert(mod->name);
+			sel.selected_modules.insert(mod->meta_->name);
 			continue;
 		}
 
 		if (arg_memb.compare(0, 2, "w:") == 0) {
 			for (auto wire : mod->wires())
 				if (match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "i:") == 0) {
 			for (auto wire : mod->wires())
 				if (wire->port_input && match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "o:") == 0) {
 			for (auto wire : mod->wires())
 				if (wire->port_output && match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "x:") == 0) {
 			for (auto wire : mod->wires())
 				if ((wire->port_input || wire->port_output) && match_ids(wire->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "s:") == 0) {
 			size_t delim = arg_memb.substr(2).find(':');
@@ -928,7 +931,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 				int width = atoi(arg_memb.substr(2).c_str());
 				for (auto wire : mod->wires())
 					if (wire->width == width)
-						sel.selected_members[mod->name].insert(wire->name);
+						sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 			} else {
 				std::string min_str = arg_memb.substr(2, delim);
 				std::string max_str = arg_memb.substr(2+delim+1);
@@ -936,18 +939,18 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 				int max_width = max_str.empty() ? -1 : atoi(max_str.c_str());
 				for (auto wire : mod->wires())
 					if (min_width <= wire->width && (wire->width <= max_width || max_width == -1))
-						sel.selected_members[mod->name].insert(wire->name);
+						sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 			}
 		} else
 		if (arg_memb.compare(0, 2, "m:") == 0) {
 			for (auto &it : mod->memories)
-				if (match_ids(it.first, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb.substr(2)))
+					sel.selected_members[mod->meta_->name].insert(it.first);
 		} else
 		if (arg_memb.compare(0, 2, "c:") == 0) {
 			for (auto cell : mod->cells())
 				if (match_ids(cell->name, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 		} else
 		if (arg_memb.compare(0, 2, "t:") == 0) {
 			if (arg_memb.compare(2, 1, "@") == 0) {
@@ -957,59 +960,59 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 
 				auto &muster = design->selection_vars[set_name];
 				for (auto cell : mod->cells())
-					if (muster.selected_modules.count(cell->type))
-						sel.selected_members[mod->name].insert(cell->name);
+					if (muster.selected_modules.count(cell->type.ref()))
+						sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 			} else {
 				for (auto cell : mod->cells())
 					if (match_ids(cell->type, arg_memb.substr(2)))
-						sel.selected_members[mod->name].insert(cell->name);
+						sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 			}
 		} else
 		if (arg_memb.compare(0, 2, "p:") == 0) {
 			for (auto &it : mod->processes)
-				if (match_ids(it.first, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb.substr(2)))
+					sel.selected_members[mod->meta_->name].insert(it.first);
 		} else
 		if (arg_memb.compare(0, 2, "a:") == 0) {
 			for (auto wire : mod->wires())
 				if (match_attr(design, wire, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 			for (auto &it : mod->memories)
 				if (match_attr(design, it.second, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+					sel.selected_members[mod->meta_->name].insert(it.first);
 			for (auto cell : mod->cells())
 				if (match_attr(design, cell, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 			for (auto &it : mod->processes)
 				if (match_attr(design, it.second, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(it.first);
+					sel.selected_members[mod->meta_->name].insert(it.first);
 		} else
 		if (arg_memb.compare(0, 2, "r:") == 0) {
 			for (auto cell : mod->cells())
 				if (match_attr(cell->parameters, arg_memb.substr(2)))
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 		} else {
 			std::string orig_arg_memb = arg_memb;
 			if (arg_memb.compare(0, 2, "n:") == 0)
 				arg_memb = arg_memb.substr(2);
 			for (auto wire : mod->wires())
 				if (match_ids(wire->name, arg_memb)) {
-					sel.selected_members[mod->name].insert(wire->name);
+					sel.selected_members[mod->meta_->name].insert(wire->name.ref());
 					arg_memb_found[orig_arg_memb] = true;
 				}
 			for (auto &it : mod->memories)
-				if (match_ids(it.first, arg_memb)) {
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb)) {
+					sel.selected_members[mod->meta_->name].insert(it.first);
 					arg_memb_found[orig_arg_memb] = true;
 				}
 			for (auto cell : mod->cells())
 				if (match_ids(cell->name, arg_memb)) {
-					sel.selected_members[mod->name].insert(cell->name);
+					sel.selected_members[mod->meta_->name].insert(cell->name.ref());
 					arg_memb_found[orig_arg_memb] = true;
 				}
 			for (auto &it : mod->processes)
-				if (match_ids(it.first, arg_memb)) {
-					sel.selected_members[mod->name].insert(it.first);
+				if (match_ids(RTLIL::IdString(design->twines.str(it.first)), arg_memb)) {
+					sel.selected_members[mod->meta_->name].insert(it.first);
 					arg_memb_found[orig_arg_memb] = true;
 				}
 		}
@@ -1365,6 +1368,7 @@ struct SelectPass : public Pass {
 
 		work_stack.clear();
 
+		TwineSearch search(&design->twines);
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
@@ -1431,10 +1435,11 @@ struct SelectPass : public Pass {
 				continue;
 			}
 			if (arg == "-module" && argidx+1 < args.size()) {
-				RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
-				if (design->module(mod_name) == nullptr)
-					log_cmd_error("No such module: %s\n", mod_name.unescape());
-				design->selected_active_module = mod_name.str();
+				std::string mod_name = RTLIL::escape_id(args[++argidx]);
+				TwineRef t = search.find(mod_name);
+				if (t == Twine::Null || design->module(t) == nullptr)
+					log_cmd_error("No such module: %s\n", RTLIL::unescape_id(mod_name));
+				design->selected_active_module = t;
 				got_module = true;
 				continue;
 			}
@@ -1475,7 +1480,7 @@ struct SelectPass : public Pass {
 				}
 				IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos));
 				IdString obj_name = RTLIL::escape_id(line.substr(slash_pos+1));
-				sel.selected_members[mod_name].insert(obj_name);
+				sel.selected_members[design->twines.add(Twine{mod_name.str()})].insert(design->twines.add(Twine{obj_name.str()}));
 			}
 
 			select_filter_active_mod(design, sel);
@@ -1493,7 +1498,7 @@ struct SelectPass : public Pass {
 		const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min";
 
 		if (common_flagset_tally > 1)
-			log_cmd_error("Options %s can not be combined.\n", common_flagset);                
+			log_cmd_error("Options %s can not be combined.\n", common_flagset);
 
 		if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
 			log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset);
@@ -1519,7 +1524,7 @@ struct SelectPass : public Pass {
 
 		if (clear_mode) {
 			design->selection() = RTLIL::Selection::FullSelection(design);
-			design->selected_active_module = std::string();
+			design->selected_active_module = TwineRef{};
 			return;
 		}
 
@@ -1545,11 +1550,11 @@ struct SelectPass : public Pass {
 			sel->optimize(design);
 			for (auto mod : design->all_selected_modules())
 			{
-				if (sel->selected_whole_module(mod->name) && list_mode)
+				if (sel->selected_whole_module(mod->meta_->name) && list_mode)
 					log("%s\n", mod);
 				if (!list_mod_mode)
 					for (auto it : mod->selected_members())
-						LOG_OBJECT("%s/%s\n", mod->name.unescape().c_str(), it->name.unescape().c_str())
+						LOG_OBJECT("%s/%s\n", design->twines.unescaped_str(mod->name).c_str(), mod->design->twines.unescaped_str(it->meta_->name).c_str())
 			}
 			if (count_mode)
 			{
@@ -1673,10 +1678,10 @@ struct SelectPass : public Pass {
 			if (sel.full_selection)
 				log("*\n");
 			for (auto &it : sel.selected_modules)
-				log("%s\n", it.unescape());
+				log("%s\n", design->twines.unescaped_str(it).c_str());
 			for (auto &it : sel.selected_members)
 				for (auto &it2 : it.second)
-					log("%s/%s\n", it.first.unescape(), it2.unescape());
+					log("%s/%s\n", design->twines.unescaped_str(it.first).c_str(), design->twines.unescaped_str(it2).c_str());
 			return;
 		}
 
@@ -1728,17 +1733,17 @@ struct CdPass : public Pass {
 		if (args.size() == 1 || args[1] == "/") {
 			design->pop_selection();
 			design->push_full_selection();
-			design->selected_active_module = std::string();
+			design->selected_active_module = TwineRef{};
 			return;
 		}
 
 		if (args[1] == "..")
 		{
-			string modname = design->selected_active_module;
+			string modname = design->twines.str(design->selected_active_module);
 
 			design->pop_selection();
 			design->push_full_selection();
-			design->selected_active_module = std::string();
+			design->selected_active_module = TwineRef{};
 
 			while (1)
 			{
@@ -1748,12 +1753,12 @@ struct CdPass : public Pass {
 					break;
 
 				modname = modname.substr(0, pos);
-				Module *mod = design->module(modname);
+				Module *mod = design->module(RTLIL::IdString(modname));
 
 				if (mod == nullptr)
 					continue;
 
-				design->selected_active_module = modname;
+				design->selected_active_module = design->twines.add(Twine{modname});
 				design->pop_selection();
 				design->push_full_selection();
 				select_filter_active_mod(design, design->selection());
@@ -1766,14 +1771,15 @@ struct CdPass : public Pass {
 
 		std::string modname = RTLIL::escape_id(args[1]);
 
-		if (design->module(modname) == nullptr && !design->selected_active_module.empty()) {
+		if (design->module(RTLIL::IdString(modname)) == nullptr && design->selected_active_module) {
 			RTLIL::Module *module = design->module(design->selected_active_module);
-			if (module != nullptr && module->cell(modname) != nullptr)
-				modname = module->cell(modname)->type.str();
+			TwineRef cell_ref = design->twines.lookup(modname);
+			if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
+				modname = design->twines.str(module->cell(cell_ref)->type.ref());
 		}
 
-		if (design->module(modname) != nullptr) {
-			design->selected_active_module = modname;
+		if (design->module(RTLIL::IdString(modname)) != nullptr) {
+			design->selected_active_module = design->twines.add(Twine{modname});
 			design->pop_selection();
 			design->push_full_selection();
 			select_filter_active_mod(design, design->selection());
@@ -1788,17 +1794,20 @@ struct CdPass : public Pass {
 template<typename T>
 static void log_matches(const char *title, Module *module, const T &list)
 {
-	std::vector<IdString> matches;
+	std::vector<TwineRef> matches;
 
 	for (auto &it : list)
 		if (module->selected(it.second))
-			matches.push_back(RTLIL::IdString(it.second->name));
+			matches.push_back(it.first);
 
 	if (!matches.empty()) {
 		log("\n%d %s:\n", int(matches.size()), title);
-		std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
-		for (auto id : matches)
-			log("  %s\n", id.unescape());
+		auto &twines = module->design->twines;
+		std::sort(matches.begin(), matches.end(), [&](TwineRef a, TwineRef b) {
+			return twines.str(a) < twines.str(b);
+		});
+		for (auto ref : matches)
+			log("  %s\n", twines.unescaped_str(ref).c_str());
 	}
 }
 
@@ -1825,7 +1834,7 @@ struct LsPass : public Pass {
 		size_t argidx = 1;
 		extra_args(args, argidx, design);
 
-		if (design->selected_active_module.empty())
+		if (!design->selected_active_module)
 		{
 			std::vector<IdString> matches;
 
@@ -1836,7 +1845,7 @@ struct LsPass : public Pass {
 				log("\n%d %s:\n", int(matches.size()), "modules");
 				std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
 				for (auto id : matches)
-					log("  %s%s\n", id.unescape(), design->selected_whole_module(design->module(id)) ? "" : "*");
+					log("  %s%s\n", design->twines.unescaped_str(id), design->selected_whole_module(design->module(id)) ? "" : "*");
 			}
 		}
 		else
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 22cd858be..4c5cbc29e 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -39,7 +39,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
 	RTLIL::Wire *wire = NULL;
 	TwineRef t = module->design->twines.add(Twine{name});
 
-	if (module->count_id(name) != 0)
+	if (module->count_id(t) != 0)
 	{
 		log("Module %s already has such an object %s.\n", module->name, name);
 		name += "$";
@@ -47,7 +47,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
 	}
 	else
 	{
-		wire = module->addWire(name, width);
+		wire = module->addWire(t, width);
 		wire->port_input = flag_input;
 		wire->port_output = flag_output;
 
@@ -305,7 +305,7 @@ struct SetundefPass : public Pass {
 					CellTypes ct(design);
 					for (auto &it : module->cells_)
 					for (auto &conn : it.second->connections())
-						if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+						if (!ct.cell_known(it.second->type.ref()) || ct.cell_output(it.second->type.ref(), conn.first))
 							undriven_signals.del(sigmap(conn.second));
 
 					RTLIL::SigSpec sig = undriven_signals.export_all();
@@ -340,7 +340,7 @@ struct SetundefPass : public Pass {
 					CellTypes ct(design);
 					for (auto &it : module->cells_)
 					for (auto &conn : it.second->connections())
-						if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+						if (!ct.cell_known(it.second->type.ref()) || ct.cell_output(it.second->type.ref(), conn.first))
 							undriven_signals.del(sigmap(conn.second));
 
 					RTLIL::SigSpec sig = undriven_signals.export_all();
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 02c9ba649..365f3f2bc 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -148,14 +148,15 @@ struct ShowWorker
 
 	std::string findColor(IdString member_name)
 	{
+		TwineRef member_ref = design->twines.lookup(member_name.str());
 		for (auto &s : color_selections)
-			if (s.second.selected_member(module->name, member_name)) {
+			if (member_ref && s.second.selected_member(module->meta_->name, member_ref)) {
 				return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first);
 			}
 
 		RTLIL::Const colorattr_value;
-		RTLIL::Cell *cell = module->cell(member_name);
-		RTLIL::Wire *wire = module->wire(member_name);
+		RTLIL::Cell *cell = member_ref ? module->cell(member_ref) : nullptr;
+		RTLIL::Wire *wire = member_ref ? module->wire(member_ref) : nullptr;
 
 		if (cell && cell->attributes.count(colorattr))
 			colorattr_value = cell->attributes.at(colorattr);
@@ -174,8 +175,9 @@ struct ShowWorker
 
 	const char *findLabel(std::string member_name)
 	{
+		TwineRef member_ref = design->twines.lookup(member_name);
 		for (auto &s : label_selections)
-			if (s.second.selected_member(module->name, member_name))
+			if (member_ref && s.second.selected_member(module->meta_->name, member_ref))
 				return escape(s.first);
 		return escape(member_name, true);
 	}
@@ -240,7 +242,7 @@ struct ShowWorker
 
 		if (sig.is_chunk()) {
 			const RTLIL::SigChunk &c = sig.as_chunk();
-			if (c.wire != nullptr && design->selected_member(module->name, c.wire->name)) {
+			if (c.wire != nullptr && design->selected_member(module->meta_->name, c.wire->name.ref())) {
 				if (!range_check || c.wire->width == c.width)
 						return stringf("n%d", id2num(c.wire->name));
 			} else {
@@ -472,10 +474,10 @@ struct ShowWorker
 			std::vector<std::string> in_label_pieces, out_label_pieces;
 
 			for (auto &conn : cell->connections()) {
-				if (!ct.cell_output(cell->type, conn.first))
-					in_ports.push_back(conn.first);
+				if (!ct.cell_output(cell->type.ref(), conn.first))
+					in_ports.push_back(RTLIL::IdString(design->twines.str(conn.first)));
 				else
-					out_ports.push_back(conn.first);
+					out_ports.push_back(RTLIL::IdString(design->twines.str(conn.first)));
 			}
 
 			std::sort(in_ports.begin(), in_ports.end(), RTLIL::sort_by_id_str());
@@ -501,8 +503,8 @@ struct ShowWorker
 
 			std::string code;
 			for (auto &conn : cell->connections()) {
-				code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)),
-						conn.second, ct.cell_output(cell->type, conn.first));
+				code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(RTLIL::IdString(design->twines.str(conn.first)))),
+						conn.second, ct.cell_output(cell->type.ref(), conn.first));
 			}
 
 			std::string src_href;
@@ -523,7 +525,7 @@ struct ShowWorker
 		{
 			RTLIL::Process *proc = it.second;
 
-			if (!design->selected_member(module->name, proc->name))
+			if (!design->selected_member(module->meta_->name, it.first))
 				continue;
 
 			std::set<RTLIL::SigSpec> input_signals, output_signals;
@@ -549,22 +551,23 @@ struct ShowWorker
 				net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
 			}
 
-			std::string proc_src = proc->name.unescape();
+			std::string proc_name_str = design->twines.str(it.first);
+			std::string proc_src = design->twines.unescaped_str(it.first);
 			if (proc->has_attribute(ID::src) > 0)
 				proc_src = proc->get_src_attribute();
-			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str());
+			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc_name_str), proc_src.c_str(), findColor(RTLIL::IdString(proc_name_str)).c_str());
 		}
 
 		for (auto &conn : module->connections())
 		{
 			bool found_lhs_wire = false;
 			for (auto &c : conn.first.chunks()) {
-				if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
+				if (c.wire == nullptr || design->selected_member(module->meta_->name, c.wire->name.ref()))
 					found_lhs_wire = true;
 			}
 			bool found_rhs_wire = false;
 			for (auto &c : conn.second.chunks()) {
-				if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
+				if (c.wire == nullptr || design->selected_member(module->meta_->name, c.wire->name.ref()))
 					found_rhs_wire = true;
 			}
 			if (!found_lhs_wire || !found_rhs_wire)
@@ -645,16 +648,16 @@ struct ShowWorker
 			module = mod;
 			if (design->selected_whole_module(module->name)) {
 				if (module->get_blackbox_attribute()) {
-						//log("Skipping blackbox module %s.\n", module->name.unescape());
+						//log("Skipping blackbox module %s.\n", design->twines.unescaped_str(module->name));
 					continue;
 				} else
 				if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
-					log("Skipping empty module %s.\n", module->name.unescape());
+					log("Skipping empty module %s.\n", design->twines.unescaped_str(module->name));
 					continue;
 				} else
-					log("Dumping module %s to page %d.\n", module->name.unescape(), ++page_counter);
+					log("Dumping module %s to page %d.\n", design->twines.unescaped_str(module->name), ++page_counter);
 			} else
-				log("Dumping selected parts of module %s to page %d.\n", module->name.unescape(), ++page_counter);
+				log("Dumping selected parts of module %s to page %d.\n", design->twines.unescaped_str(module->name), ++page_counter);
 			handle_module();
 		}
 	}
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 3e57a91ae..c767ba4d3 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -75,7 +75,7 @@ struct SpliceWorker
 		RTLIL::SigSpec new_sig = sig;
 
 		if (sig_a.size() != sig.size()) {
-			RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($slice));
+			RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$slice);
 			cell->parameters[ID::OFFSET] = offset;
 			cell->parameters[ID::A_WIDTH] = sig_a.size();
 			cell->parameters[ID::Y_WIDTH] = sig.size();
@@ -132,7 +132,7 @@ struct SpliceWorker
 		RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
 		for (size_t i = 1; i < chunks.size(); i++) {
 			RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
-			RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($concat));
+			RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$concat);
 			cell->parameters[ID::A_WIDTH] = new_sig.size();
 			cell->parameters[ID::B_WIDTH] = sig2.size();
 			cell->setPort(TW::A, new_sig);
@@ -149,7 +149,7 @@ struct SpliceWorker
 
 	void run()
 	{
-		log("Splicing signals in module %s:\n", module->name.unescape());
+		log("Splicing signals in module %s:\n", design->twines.unescaped_str(module->name));
 
 		driven_bits.push_back(RTLIL::State::Sm);
 		driven_bits.push_back(RTLIL::State::Sm);
@@ -165,7 +165,7 @@ struct SpliceWorker
 
 		for (auto cell : module->cells())
 		for (auto &conn : cell->connections())
-			if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) {
+			if (!ct.cell_known(cell->type.ref()) || ct.cell_output(cell->type.ref(), conn.first)) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				driven_chunks.insert(sig);
 				for (auto &bit : sig.to_sigbit_vector())
@@ -189,10 +189,10 @@ struct SpliceWorker
 			if (!sel_by_wire && !design->selected(module, cell))
 				continue;
 			for (auto &conn : cell->connections_)
-				if (ct.cell_input(cell->type, conn.first)) {
-					if (ports.size() > 0 && !ports.count(conn.first))
+				if (ct.cell_input(cell->type.ref(), conn.first)) {
+					if (ports.size() > 0 && !ports.count(RTLIL::IdString(design->twines.str(conn.first))))
 						continue;
-					if (no_ports.size() > 0 && no_ports.count(conn.first))
+					if (no_ports.size() > 0 && no_ports.count(RTLIL::IdString(design->twines.str(conn.first))))
 						continue;
 					RTLIL::SigSpec sig = sigmap(conn.second);
 					if (!sel_by_cell) {
@@ -231,8 +231,8 @@ struct SpliceWorker
 
 		for (auto &it : rework_wires)
 		{
-			RTLIL::IdString orig_name = it.first->name;
-			module->rename(it.first, NEW_ID);
+			TwineRef orig_name = it.first->name.ref();
+			module->rename(it.first, design->twines.add(NEW_TWINE));
 
 			RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
 			it.first->port_id = 0;
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index dd7b3c616..08f66a3a3 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -181,9 +181,9 @@ struct SplitnetsPass : public Pass {
 				for (auto c : module->cells())
 				for (auto &p : c->connections())
 				{
-					if (!ct.cell_known(c->type))
+					if (!ct.cell_known(c->type.ref()))
 						continue;
-					if (!ct.cell_output(c->type, p.first))
+					if (!ct.cell_output(c->type.ref(), p.first))
 						continue;
 
 					RTLIL::SigSpec sig = p.second;
diff --git a/passes/cmds/sta.cc b/passes/cmds/sta.cc
index 259794d32..663f69dd1 100644
--- a/passes/cmds/sta.cc
+++ b/passes/cmds/sta.cc
@@ -35,8 +35,8 @@ struct StaWorker
 
 	struct t_data {
 		Cell* driver;
-		IdString dst_port, src_port;
-		vector<tuple<SigBit,int,IdString>> fanouts;
+		TwineRef dst_port, src_port;
+		vector<tuple<SigBit,int,TwineRef>> fanouts;
 		SigBit backtrack;
 		t_data() : driver(nullptr) {}
 	};
@@ -44,7 +44,7 @@ struct StaWorker
 	std::deque<SigBit> queue;
 	struct t_endpoint {
 		Cell *sink;
-		IdString port;
+		TwineRef port;
 		int required;
 		t_endpoint() : sink(nullptr), required(0) {}
 	};
@@ -66,23 +66,23 @@ struct StaWorker
 			Module *inst_module = design->module(cell->type);
 			if (!inst_module) {
 				if (unrecognised_cells.insert(cell->type).second)
-					log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescape());
+					log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescaped());
 				continue;
 			}
 
 			if (!inst_module->get_blackbox_attribute()) {
-				log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescape());
+				log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescaped());
 				continue;
 			}
 
-			IdString derived_type = inst_module->derive(design, cell->parameters);
+			TwineRef derived_type = inst_module->derive(design, cell->parameters);
 			inst_module = design->module(derived_type);
 			log_assert(inst_module);
 
 			if (!timing.count(derived_type)) {
 				auto &t = timing.setup_module(inst_module);
 				if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
-					log_warning("Module '%s' has no timing arcs!\n", cell->type.unescape());
+					log_warning("Module '%s' has no timing arcs!\n", cell->type.unescaped());
 			}
 
 			auto &t = timing.at(derived_type);
@@ -206,7 +206,7 @@ struct StaWorker
 		log("Latest arrival time in '%s' is %d:\n", module, maxarrival);
 		auto it = endpoints.find(maxbit);
 		if (it != endpoints.end() && it->second.sink)
-			log("  %6d %s (%s.%s)\n", maxarrival, it->second.sink, it->second.sink->type.unescape(), it->second.port.unescape());
+			log("  %6d %s (%s.%s)\n", maxarrival, it->second.sink, design->twines.unescaped_str(it->second.sink->type), design->twines.unescaped_str(it->second.port));
 		else {
 			log("  %6d (%s)\n", maxarrival, b.wire->port_output ? "<primary output>" : "<unknown>");
 			if (!b.wire->port_output)
@@ -217,7 +217,7 @@ struct StaWorker
 			int arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
 			if (jt->second.driver) {
 				log("           %s\n", log_signal(b));
-				log("  %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, jt->second.driver->type.unescape(), jt->second.src_port.unescape(), jt->second.dst_port.unescape());
+				log("  %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, design->twines.unescaped_str(jt->second.driver->type), design->twines.unescaped_str(jt->second.src_port), design->twines.unescaped_str(jt->second.dst_port));
 			}
 			else if (b.wire->port_input)
 				log("  %6d   %s (%s)\n", arrival, log_signal(b), "<primary input>");
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 93215720f..ab2f97be7 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -59,18 +59,18 @@ struct statdata_t {
 	double local_sequential_area = 0;
 	double submodule_area = 0;
 	int num_submodules = 0;
-	std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> submodules_area_by_type;
+	std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_submodules_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> submodules_area_by_type;
 
-	std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
+	std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> local_num_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> local_area_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> local_seq_area_cells_by_type;
 	string tech;
 
-	std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> area_cells_by_type;
-	std::map<RTLIL::IdString, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
-	std::set<RTLIL::IdString> unknown_cell_area;
+	std::map<TwineRef, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> area_cells_by_type;
+	std::map<TwineRef, double, RTLIL::sort_by_id_str> seq_area_cells_by_type;
+	std::set<TwineRef> unknown_cell_area;
 
 	statdata_t operator+(const statdata_t &other) const
 	{
@@ -141,7 +141,7 @@ struct statdata_t {
 		}
 	}
 
-	statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
+	statdata_t(RTLIL::Design *design, const RTLIL::Module *mod, bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
 	{
 		tech = techname;
 
@@ -183,35 +183,35 @@ struct statdata_t {
 			local_num_memory_bits += it.second->width * it.second->size;
 		}
 		for (auto cell : mod->selected_cells()) {
-			RTLIL::IdString cell_type = cell->type;
+			TwineRef cell_type = cell->type_impl;
 			if (width_mode) {
-				if (cell_type.in(ID($not), ID($pos), ID($neg), ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_and),
-						 ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($lut), ID($and), ID($or),
-						 ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt),
-						 ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul),
-						 ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
+				if (cell_type.in(TW($not), TW($pos), TW($neg), TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_and),
+						 TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($lut), TW($and), TW($or),
+						 TW($xor), TW($xnor), TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx), TW($lt),
+						 TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt), TW($add), TW($sub), TW($mul),
+						 TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow), TW($alu))) {
 					int width_a = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : 0;
 					int width_b = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : 0;
 					int width_y = cell->hasPort(TW::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
-					cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
-				} else if (cell_type.in(ID($mux)))
-					cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)));
-				else if (cell_type.in(ID($bmux), ID($pmux)))
+					cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}))});
+				} else if (cell_type.in(TW($mux)))
+					cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)))});
+				else if (cell_type.in(TW($bmux), TW($pmux)))
 					cell_type =
-					  stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)));
-				else if (cell_type == ID($demux))
+					  design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)))});
+				else if (cell_type == TW($demux))
 					cell_type =
-					  stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)));
-				else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
-						      ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
-						      ID($dlatchsr)))
-					cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)));
+					  design->twines.add(Twine{stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)))});
+				else if (cell_type.in(TW($sr), TW($ff), TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe),
+						      TW($sdff), TW($sdffe), TW($sdffce), TW($aldff), TW($aldffe), TW($dlatch), TW($adlatch),
+						      TW($dlatchsr)))
+					cell_type = design->twines.add(Twine{stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)))});
 			}
 
 			if (!cell_area.empty()) {
 				// check if cell_area provides a area calculator
-				if (cell_area.count(cell->type)) {
-					cell_area_t cell_data = cell_area.at(cell->type);
+				if (cell_area.count(cell->type_impl)) {
+					cell_area_t cell_data = cell_area.at(cell->type_impl);
 					if (cell_data.single_parameter_area.size() > 0) {
 						// assume that we just take the max of the A,B,Y ports
 
@@ -337,18 +337,16 @@ struct statdata_t {
 			num_processes++;
 			local_num_processes++;
 		}
-		RTLIL::IdString cell_name = mod->name;
-		auto s = cell_name.str();
 	}
 
 	unsigned int estimate_xilinx_lc()
 	{
-		unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
-		unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
-		unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
-		unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
-		unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
-		unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
+		unsigned int lut6_cnt = num_cells_by_type[TW::LUT6];
+		unsigned int lut5_cnt = num_cells_by_type[TW::LUT5];
+		unsigned int lut4_cnt = num_cells_by_type[TW::LUT4];
+		unsigned int lut3_cnt = num_cells_by_type[TW::LUT3];
+		unsigned int lut2_cnt = num_cells_by_type[TW::LUT2];
+		unsigned int lut1_cnt = num_cells_by_type[TW::LUT1];
 		unsigned int lc_cnt = 0;
 
 		lc_cnt += lut6_cnt;
@@ -505,7 +503,7 @@ struct statdata_t {
 		}
 	}
 
-	void log_data(RTLIL::IdString mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
+	void log_data(const TwinePool& twines, TwineRef mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
 	{
 
 		print_log_header(print_area, print_hierarchical, print_global_only);
@@ -523,7 +521,7 @@ struct statdata_t {
 		print_log_line("cells", local_num_cells, local_area, num_cells, area, 0, print_area, print_hierarchical, print_global_only);
 		for (auto &it : num_cells_by_type)
 			if (it.second) {
-				auto name = string(it.first.unescape());
+				auto name = twines.unescaped_str(it.first);
 				print_log_line(name, local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
 					       local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
 					       area_cells_by_type.at(it.first), 1, print_area, print_hierarchical, print_global_only);
@@ -533,7 +531,7 @@ struct statdata_t {
 				       print_global_only);
 			for (auto &it : num_submodules_by_type)
 				if (it.second)
-					print_log_line(string(it.first.unescape()), it.second, 0, it.second,
+					print_log_line(twines.unescaped_str(it.first), it.second, 0, it.second,
 						       submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0, 1,
 						       print_area, print_hierarchical, print_global_only);
 		}
@@ -582,7 +580,7 @@ struct statdata_t {
 			       count_local, area_local);
 	}
 
-	void log_data_json(const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
+	void log_data_json(const TwinePool& twines, const char *mod_name, bool first_module, bool hierarchical = false, bool global_only = false)
 	{
 		if (!first_module)
 			log(",\n");
@@ -607,7 +605,7 @@ struct statdata_t {
 				if (it.second) {
 					if (!first_line)
 						log(",\n");
-					log("            %s: %s", json11::Json(it.first.unescape()).dump(),
+					log("            %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
 					    json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
 						      local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
 						      area_cells_by_type.at(it.first))
@@ -621,7 +619,7 @@ struct statdata_t {
 				if (it.second) {
 					if (!first_line)
 						log(",\n");
-					log("            %s: %s", json11::Json(it.first.unescape()).dump(),
+					log("            %s: %s", json11::Json(twines.unescaped_str(it.first)).dump(),
 					    json_line(0, 0, it.second,
 						      submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
 					      .c_str());
@@ -662,14 +660,14 @@ struct statdata_t {
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				for (auto &it : num_submodules_by_type)
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				log("\n");
@@ -697,14 +695,14 @@ struct statdata_t {
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				for (auto &it : num_submodules_by_type)
 					if (it.second) {
 						if (!first_line)
 							log(",\n");
-						log("            %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
+						log("            %s: %u", json11::Json(twines.unescaped_str(it.first)).dump(), it.second);
 						first_line = false;
 					}
 				log("\n");
@@ -726,7 +724,7 @@ struct statdata_t {
 	}
 };
 
-statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level, bool quiet = false, bool has_area = true,
+statdata_t hierarchy_worker(const TwinePool& twines, std::map<TwineRef, statdata_t> &mod_stat, TwineRef mod, int level, bool quiet = false, bool has_area = true,
 			    bool hierarchy_mode = true)
 {
 	statdata_t mod_data = mod_stat.at(mod);
@@ -734,60 +732,60 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
 	for (auto &it : mod_data.num_submodules_by_type) {
 		if (mod_stat.count(it.first) > 0) {
 			if (!quiet)
-				mod_data.print_log_line(string(it.first.unescape()), mod_stat.at(it.first).local_num_cells,
+				mod_data.print_log_line(twines.unescaped_str(it.first), mod_stat.at(it.first).local_num_cells,
 							mod_stat.at(it.first).local_area, mod_stat.at(it.first).num_cells, mod_stat.at(it.first).area,
 							level, has_area, hierarchy_mode);
-			hierarchy_worker(mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
+			hierarchy_worker(twines, mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
 		}
 	}
 
 	return mod_data;
 }
 
-statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<RTLIL::IdString, statdata_t> &mod_stat,
-			     bool width_mode, dict<IdString, cell_area_t> &cell_area, string techname)
+statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod, std::map<TwineRef, statdata_t> &mod_stat,
+			     bool width_mode, dict<TwineRef, cell_area_t> &cell_area, string techname)
 {
 	if (top_mod == nullptr)
 		top_mod = design->top_module();
 	statdata_t mod_data(design, top_mod, width_mode, cell_area, techname);
 	for (auto cell : top_mod->selected_cells()) {
-		if (cell_area.count(cell->type) == 0) {
-			if (design->has(cell->type)) {
+		if (cell_area.count(cell->type_impl) == 0) {
+			if (design->has(cell->type_impl)) {
 				if (!(design->module(cell->type)->attributes.count(ID::blackbox))) {
 					// deal with modules
 					mod_data.add(
 					  hierarchy_builder(design, design->module(cell->type), mod_stat, width_mode, cell_area, techname));
-					mod_data.num_submodules_by_type[cell->type]++;
-					mod_data.submodules_area_by_type[cell->type] += mod_stat.at(cell->type).area;
-					mod_data.submodule_area += mod_stat.at(cell->type).area;
+					mod_data.num_submodules_by_type[cell->type_impl]++;
+					mod_data.submodules_area_by_type[cell->type_impl] += mod_stat.at(cell->type_impl).area;
+					mod_data.submodule_area += mod_stat.at(cell->type_impl).area;
 					mod_data.num_submodules++;
-					mod_data.unknown_cell_area.erase(cell->type);
+					mod_data.unknown_cell_area.erase(cell->type_impl);
 					mod_data.num_cells -=
-					  (mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
-					mod_data.num_cells_by_type.erase(cell->type);
-					mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
-								      ? mod_data.local_num_cells_by_type.at(cell->type)
+					  (mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
+					mod_data.num_cells_by_type.erase(cell->type_impl);
+					mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
+								      ? mod_data.local_num_cells_by_type.at(cell->type_impl)
 								      : 0;
-					mod_data.local_num_cells_by_type.erase(cell->type);
-					mod_data.local_area_cells_by_type.erase(cell->type);
+					mod_data.local_num_cells_by_type.erase(cell->type_impl);
+					mod_data.local_area_cells_by_type.erase(cell->type_impl);
 				} else {
 					// deal with blackbox cells
 					if (design->module(cell->type)->attributes.count(ID::area) &&
 					    design->module(cell->type)->attributes.at(ID::area).size() == 0) {
-						mod_data.num_submodules_by_type[cell->type]++;
+						mod_data.num_submodules_by_type[cell->type_impl]++;
 						mod_data.num_submodules++;
-						mod_data.submodules_area_by_type[cell->type] +=
-						  double(design->module(cell->type)->attributes.at(ID::area).as_int());
-						mod_data.area += double(design->module(cell->type)->attributes.at(ID::area).as_int());
-						mod_data.unknown_cell_area.erase(cell->type);
+						mod_data.submodules_area_by_type[cell->type_impl] +=
+						  double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
+						mod_data.area += double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
+						mod_data.unknown_cell_area.erase(cell->type_impl);
 						mod_data.num_cells -=
-						  (mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;
-						mod_data.num_cells_by_type.erase(cell->type);
-						mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)
-									      ? mod_data.local_num_cells_by_type.at(cell->type)
+						  (mod_data.num_cells_by_type.count(cell->type_impl) != 0) ? mod_data.num_cells_by_type.at(cell->type_impl) : 0;
+						mod_data.num_cells_by_type.erase(cell->type_impl);
+						mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type_impl) != 0)
+									      ? mod_data.local_num_cells_by_type.at(cell->type_impl)
 									      : 0;
-						mod_data.local_num_cells_by_type.erase(cell->type);
-						mod_data.local_area_cells_by_type.erase(cell->type);
+						mod_data.local_num_cells_by_type.erase(cell->type_impl);
+						mod_data.local_area_cells_by_type.erase(cell->type_impl);
 					}
 				}
 			}
@@ -797,7 +795,7 @@ statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod
 	return mod_data;
 }
 
-void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
+void read_liberty_cellarea(TwinePool& twines, dict<TwineRef, cell_area_t> &cell_area, string liberty_file)
 {
 	std::istream *f = uncompressed(liberty_file.c_str());
 	yosys_input_files.insert(liberty_file);
@@ -874,7 +872,8 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
 
 		if (ar != nullptr && !ar->value.empty()) {
 			string prefix = cell->args[0].substr(0, 1) == "$" ? "" : "\\";
-			cell_area[prefix + cell->args[0]] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
+			TwineRef t = twines.add(Twine{prefix + cell->args[0]});
+			cell_area[t] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
 							     port_names};
 		}
 	}
@@ -927,8 +926,8 @@ struct StatPass : public Pass {
 	{
 		bool width_mode = false, json_mode = false, hierarchy_mode = false;
 		RTLIL::Module *top_mod = nullptr;
-		std::map<RTLIL::IdString, statdata_t> mod_stat;
-		dict<IdString, cell_area_t> cell_area;
+		std::map<TwineRef, statdata_t> mod_stat;
+		dict<TwineRef, cell_area_t> cell_area;
 		string techname;
 
 		size_t argidx;
@@ -940,7 +939,7 @@ struct StatPass : public Pass {
 			if (args[argidx] == "-liberty" && argidx + 1 < args.size()) {
 				string liberty_file = args[++argidx];
 				rewrite_filename(liberty_file);
-				read_liberty_cellarea(cell_area, liberty_file);
+				read_liberty_cellarea(design->twines, cell_area, liberty_file);
 				continue;
 			}
 			if (args[argidx] == "-tech" && argidx + 1 < args.size()) {
@@ -1005,13 +1004,13 @@ struct StatPass : public Pass {
 					top_mod = mod;
 			statdata_t data = mod_stat.at(mod->name);
 			if (json_mode) {
-				data.log_data_json(mod->name.c_str(), first_module, hierarchy_mode);
+				data.log_data_json(design->twines, mod->name.c_str(), first_module, hierarchy_mode);
 				first_module = false;
 			} else {
 				log("\n");
-				log("=== %s%s ===\n", mod->name.unescape(), mod->is_selected_whole() ? "" : " (partially selected)");
+				log("=== %s%s ===\n", design->twines.unescaped_str(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
 				log("\n");
-				data.log_data(mod->name, false, has_area, hierarchy_mode);
+				data.log_data(design->twines, mod->name, false, has_area, hierarchy_mode);
 			}
 		}
 
@@ -1031,13 +1030,13 @@ struct StatPass : public Pass {
 								       mod_stat[top_mod->name].area, 0, has_area, hierarchy_mode, true);
 			}
 
-			statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
+			statdata_t data = hierarchy_worker(design->twines, mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);
 
 			if (json_mode)
-				data.log_data_json("design", true, hierarchy_mode, true);
+				data.log_data_json(design->twines, "design", true, hierarchy_mode, true);
 			else if (GetSize(mod_stat) > 1) {
 				log("\n");
-				data.log_data(top_mod->name, true, has_area, hierarchy_mode, true);
+				data.log_data(design->twines, top_mod->name, true, has_area, hierarchy_mode, true);
 			}
 
 			design->scratchpad_set_int("stat.num_wires", data.num_wires);
diff --git a/passes/cmds/test_patch.cc b/passes/cmds/test_patch.cc
index 874610406..d4b90c6f4 100644
--- a/passes/cmds/test_patch.cc
+++ b/passes/cmds/test_patch.cc
@@ -17,12 +17,12 @@ struct TestPatchPass : public Pass {
 		for (auto module : design->selected_modules()) {
 			SigMap sigmap(module);
 			for (auto cell : module->selected_cells()) {
-				if (cell->type == ID($add)) {
+				if (cell->type == TW($add)) {
 					Cell* add = cell;
 					log_assert(add->getPort(TW::B).is_wire());
 					log_assert(add->getPort(TW::B).known_driver());
 					auto neg = add->getPort(TW::B)[0].wire->driverCell();
-					log_assert(neg->type == ID($not));
+					log_assert(neg->type == TW($not));
 					RTLIL::Patch patcher(module, nullptr);
 					int width = cell->getPort(TW::A).size();
 					auto sub = patcher.addSub(NEW_TWINE,
diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc
index 579a9c48e..ad055ac16 100644
--- a/passes/cmds/timeest.cc
+++ b/passes/cmds/timeest.cc
@@ -66,8 +66,8 @@ struct EstimateSta {
 	// and to account for the AIG model not being balanced
 	int cell_type_factor(IdString type)
 	{
-		if (type.in(ID($gt), ID($ge), ID($lt), ID($le), ID($add), ID($sub),
-					ID($logic_not), ID($reduce_and), ID($reduce_or), ID($eq)))
+		if (type.in(TW($gt), TW($ge), TW($lt), TW($le), TW($add), TW($sub),
+					TW($logic_not), TW($reduce_and), TW($reduce_or), TW($eq)))
 			return 1;
 		else
 			return 2;
@@ -97,7 +97,7 @@ struct EstimateSta {
 				FfData ff(nullptr, cell);
 				if (!ff.has_clk) {
 					log_warning("Ignoring unsupported storage element '%s' (%s)\n",
-								cell, cell->type.unescape());
+								cell, cell->type.unescaped());
 					continue;
 				}
 				if (!clk || ff.sig_clk.as_bit() != *clk)
@@ -112,7 +112,7 @@ struct EstimateSta {
 			} else if (cell->is_mem_cell()) {
 				// memories handled separately
 				continue;
-			} else if (cell->type == ID($scopeinfo)) {
+			} else if (cell->type == TW($scopeinfo)) {
 				continue;
 			} else {
 				// find or build AIG model of combinational cell
@@ -121,7 +121,7 @@ struct EstimateSta {
 					aigs.emplace(fingerprint, Aig(cell));
 					if (aigs.at(fingerprint).name.empty()) {
 						log_error("Unsupported cell '%s' in module '%s'",
-								  cell->type.unescape(), m);
+								  cell->type.unescaped(), m);
 					}					
 				}
 
@@ -342,7 +342,7 @@ struct EstimateSta {
 						std::string src_attr = cell->get_src_attribute();
 						cell_src = stringf(" source: %s", src_attr);
 					}
-					log("    cell %s (%s)%s\n", cell, cell->type.unescape(), cell_src);
+					log("    cell %s (%s)%s\n", cell, cell->type.unescaped(), cell_src);
 					printed.insert(cell);
 				}
 			} else {
diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc
index 828b65c24..b7ee3880c 100644
--- a/passes/cmds/torder.cc
+++ b/passes/cmds/torder.cc
@@ -83,13 +83,13 @@ struct TorderPass : public Pass {
 			for (auto cell : module->selected_cells())
 			for (auto conn : cell->connections())
 			{
-				if (stop_db.count(cell->type) && stop_db.at(cell->type).count(conn.first))
+				if (stop_db.count(RTLIL::IdString(cell->type)) && stop_db.at(RTLIL::IdString(cell->type)).count(RTLIL::IdString(design->twines.str(conn.first))))
 					continue;
 
-				if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
+				if (!noautostop && yosys_celltypes.cell_known(cell->type.ref())) {
 					if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
 						continue;
-					if (cell->type.in(ID($memrd), ID($memrd_v2)) && conn.first == ID::DATA)
+					if (cell->type.in(TW($memrd), TW($memrd_v2)) && conn.first == ID::DATA)
 						continue;
 				}
 
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
index e64459cba..557cda282 100644
--- a/passes/cmds/trace.cc
+++ b/passes/cmds/trace.cc
@@ -38,7 +38,7 @@ struct TraceMonitor : public RTLIL::Monitor
 
 	void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
 	{
-		log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
+		log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, cell->module->design->twines.unescaped_str(port).c_str(), log_signal(sig), log_signal(old_sig));
 	}
 
 	void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc
index 0d4e3efda..ccbe8ae42 100644
--- a/passes/cmds/viz.cc
+++ b/passes/cmds/viz.cc
@@ -309,12 +309,12 @@ struct Graph {
 		{
 			GraphNode *g = nullptr;
 
-			if (!grp.second.selected_module(module->name))
+			if (!grp.second.selected_module(module->meta_->name))
 				continue;
 
 			for (auto wire : module->wires()) {
 				if (!wire->name.isPublic()) continue;
-				if (!grp.second.selected_member(module->name, wire->name)) continue;
+				if (!grp.second.selected_member(module->meta_->name, wire->name.ref())) continue;
 				for (auto bit : sigmap(wire)) {
 					auto it = wire_nodes.find(bit);
 					if (it == wire_nodes.end())
@@ -708,8 +708,8 @@ struct VizWorker
 			c->attributes.erase(vg_id);
 		for (auto g : graph.nodes) {
 			for (auto name : g->names()) {
-				auto w = module->wire(name);
-				auto c = module->cell(name);
+				auto w = module->wire(module->design->twines.lookup(name.str()));
+				auto c = module->cell(module->design->twines.lookup(name.str()));
 				if (w) w->attributes[vg_id] = g->index;
 				if (c) c->attributes[vg_id] = g->index;
 			}
@@ -718,7 +718,7 @@ struct VizWorker
 
 	void write_dot(FILE *f)
 	{
-		fprintf(f, "digraph \"%s\" {\n", module->name.unescape().c_str());
+		fprintf(f, "digraph \"%s\" {\n", design->twines.unescaped_str(module->name).c_str());
 		fprintf(f, "  rankdir = LR;\n");
 
 		dict<GraphNode*, std::vector<std::vector<std::string>>> extra_lines;
@@ -782,7 +782,7 @@ struct VizWorker
 				g->names().sort();
 				std::string label; // = stringf("vg=%d\\n", g->index);
 				for (auto n : g->names())
-					label = label + (label.empty() ? "" : "\\n") + n.unescape();
+					label = label + (label.empty() ? "" : "\\n") + design->twines.unescaped_str(n);
 				fprintf(f, "\tn%d [shape=rectangle,label=\"%s\"];\n", g->index, label.c_str());
 			} else {
 				std::string label = stringf("vg=%d | %d cells", g->index, GetSize(g->names()));
diff --git a/passes/cmds/wrapcell.cc b/passes/cmds/wrapcell.cc
index 4b863a752..f53d5849f 100644
--- a/passes/cmds/wrapcell.cc
+++ b/passes/cmds/wrapcell.cc
@@ -208,13 +208,13 @@ struct WrapcellPass : Pass {
 				Module *subm;
 				Cell *subcell;
 
-				if (!ct.cell_known(cell->type))
+				if (!ct.cell_known(cell->type_impl))
 					log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
-							  cell->type.unescape(), cell, module);
+							  cell->type.unescaped(), cell, module);
 
 				std::vector<std::pair<IdString, int>> unused_outputs, used_outputs;
 				for (auto conn : cell->connections()) {
-					if (ct.cell_output(cell->type, conn.first))
+					if (ct.cell_output(cell->type_impl, conn.first))
 					for (int i = 0; i < conn.second.size(); i++) {
 						if (tracking_unused && unused.check(conn.second[i]))
 							unused_outputs.emplace_back(conn.first, i);
@@ -227,7 +227,7 @@ struct WrapcellPass : Pass {
 				if (!unused_outputs.empty()) {
 					context.unused_outputs += "_unused";
 					for (auto chunk : collect_chunks(unused_outputs))
-						context.unused_outputs += "_" + chunk.format(cell).unescape();
+						context.unused_outputs += "_" + design->twines.unescaped_str(chunk.format(cell));
 				}
 
 				std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);
@@ -242,7 +242,7 @@ struct WrapcellPass : Pass {
 				subm = d->addModule(name);
 				subcell = subm->addCell("$1", cell->type);
 				for (auto conn : cell->connections()) {
-					if (ct.cell_output(cell->type, conn.first)) {
+					if (ct.cell_output(cell->type_impl, conn.first)) {
 						// Insert marker bits as placehodlers which need to be replaced
 						subcell->setPort(conn.first, SigSpec(RTLIL::Sm, conn.second.size()));
 					} else {
@@ -286,7 +286,7 @@ struct WrapcellPass : Pass {
 				dict<IdString, SigSpec> new_connections;
 
 				for (auto conn : cell->connections())
-				if (!ct.cell_output(cell->type, conn.first))
+				if (!ct.cell_output(cell->type_impl, conn.first))
 					new_connections[conn.first] = conn.second;
 
 				for (auto chunk : collect_chunks(used_outputs))
diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc
index 9f51a6ae7..993fc39d0 100644
--- a/passes/cmds/xprop.cc
+++ b/passes/cmds/xprop.cc
@@ -294,18 +294,18 @@ struct XpropWorker
 	}
 
 	void mark_maybe_x(Cell *cell) {
-		if (cell->type.in(ID($bweqx), ID($eqx), ID($nex), ID($initstate), ID($assert), ID($assume), ID($cover), ID($anyseq), ID($anyconst)))
+		if (cell->type.in(TW($bweqx), TW($eqx), TW($nex), TW($initstate), TW($assert), TW($assume), TW($cover), TW($anyseq), TW($anyconst)))
 			return;
 
-		if (cell->type.in(ID($pmux))) {
+		if (cell->type.in(TW($pmux))) {
 			mark_outputs_maybe_x(cell);
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 
-			if (cell->type != ID($anyinit))
+			if (cell->type != TW($anyinit))
 				for (int i = 0; i < ff.width; i++)
 					if (ff.val_init[i] == State::Sx)
 						mark_maybe_x(ff.sig_q[i]);
@@ -318,7 +318,7 @@ struct XpropWorker
 				return;
 		}
 
-		if (cell->type == ID($not)) {
+		if (cell->type == TW($not)) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			for (int i = 0; i < GetSize(sig_y); i++)
@@ -327,7 +327,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
+		if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 			auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@@ -337,7 +337,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($bwmux))) {
+		if (cell->type.in(TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -348,7 +348,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
+		if (cell->type.in(TW($_MUX_), TW($mux), TW($bmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -372,7 +372,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($demux))) {
+		if (cell->type.in(TW($demux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_s = cell->getPort(TW::S);
@@ -387,7 +387,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
+		if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift))) {
 			auto &sig_b = cell->getPort(TW::B);
 			auto &sig_y = cell->getPort(TW::Y);
 
@@ -407,7 +407,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($shiftx))) {
+		if (cell->type.in(TW($shiftx))) {
 			auto &sig_b = cell->getPort(TW::B);
 			auto &sig_y = cell->getPort(TW::Y);
 
@@ -438,24 +438,24 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($add), ID($sub), ID($mul), ID($neg))) {
+		if (cell->type.in(TW($add), TW($sub), TW($mul), TW($neg))) {
 			if (inputs_maybe_x(cell))
 				mark_outputs_maybe_x(cell);
 			return;
 		}
 
-		if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+		if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 			mark_outputs_maybe_x(cell);
 			return;
 		}
 
 		if (cell->type.in(
-			ID($le), ID($lt), ID($ge), ID($gt),
-			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
-			ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
-			ID($eq), ID($ne),
+			TW($le), TW($lt), TW($ge), TW($gt),
+			TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor),
+			TW($reduce_bool), TW($logic_not), TW($logic_or), TW($logic_and),
+			TW($eq), TW($ne),
 
-			ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
+			TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_ANDNOT_), TW($_OR_), TW($_NOR_), TW($_ORNOT_), TW($_XOR_), TW($_XNOR_)
 		)) {
 			auto &sig_y = cell->getPort(TW::Y);
 			if (inputs_maybe_x(cell))
@@ -463,11 +463,11 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($scopeinfo))) {
+		if (cell->type.in(TW($scopeinfo))) {
 			return;
 		}
 
-		log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescape());
+		log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescaped());
 		mark_outputs_maybe_x(cell);
 	}
 
@@ -481,7 +481,7 @@ struct XpropWorker
 	{
 		if (!ports_maybe_x(cell)) {
 
-			if (cell->type == ID($bweq)) {
+			if (cell->type == TW($bweq)) {
 				auto sig_y = cell->getPort(TW::Y);
 				auto sig_a = cell->getPort(TW::A);
 				auto sig_b = cell->getPort(TW::B);
@@ -492,7 +492,7 @@ struct XpropWorker
 				return;
 			}
 
-			if (cell->type.in(ID($nex), ID($eqx))) {
+			if (cell->type.in(TW($nex), TW($eqx))) {
 				auto sig_y = cell->getPort(TW::Y);
 				auto sig_a = cell->getPort(TW::A);
 				auto sig_b = cell->getPort(TW::B);
@@ -500,7 +500,7 @@ struct XpropWorker
 				RTLIL::IdString name(cell->name);
 				auto type = cell->type;
 				module->remove(cell);
-				if (type == ID($eqx))
+				if (type == TW($eqx))
 					module->addEq(name, sig_a, sig_b, sig_y);
 				else
 					module->addNe(name, sig_a, sig_b, sig_y);
@@ -510,10 +510,10 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($not), ID($_NOT_))) {
+		if (cell->type.in(TW($not), TW($_NOT_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
-			if (cell->type == ID($not))
+			if (cell->type == TW($not))
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 
 			auto enc_a = encoded(sig_a);
@@ -527,11 +527,11 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
+		if (cell->type.in(TW($and), TW($or), TW($_AND_), TW($_OR_), TW($_NAND_), TW($_NOR_), TW($_ANDNOT_), TW($_ORNOT_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($and), ID($or))) {
+			if (cell->type.in(TW($and), TW($or))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -540,11 +540,11 @@ struct XpropWorker
 			auto enc_b = encoded(sig_b);
 			auto enc_y = encoded(sig_y, true);
 
-			if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
+			if (cell->type.in(TW($or), TW($_OR_), TW($_NOR_), TW($_ORNOT_)))
 				enc_a.invert(), enc_b.invert(), enc_y.invert();
-			if (cell->type.in(ID($_NAND_), ID($_NOR_)))
+			if (cell->type.in(TW($_NAND_), TW($_NOR_)))
 				enc_y.invert();
-			if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+			if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 				enc_b.invert();
 
 			enc_y.connect_0(module->Or(NEW_TWINE, enc_a.is_0, enc_b.is_0));
@@ -554,7 +554,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+		if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($logic_not))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 
@@ -563,9 +563,9 @@ struct XpropWorker
 
 			enc_y.connect_as_bool();
 
-			if (cell->type.in(ID($reduce_or), ID($reduce_bool)))
+			if (cell->type.in(TW($reduce_or), TW($reduce_bool)))
 				enc_a.invert(), enc_y.invert();
-			if (cell->type == ID($logic_not))
+			if (cell->type == TW($logic_not))
 				enc_a.invert();
 
 			enc_y.connect_0(module->ReduceOr(NEW_TWINE, enc_a.is_0));
@@ -576,7 +576,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+		if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 
@@ -584,7 +584,7 @@ struct XpropWorker
 			auto enc_y = encoded(sig_y, true);
 
 			enc_y.connect_as_bool();
-			if (cell->type == ID($reduce_xnor))
+			if (cell->type == TW($reduce_xnor))
 				enc_y.invert();
 
 
@@ -596,7 +596,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($logic_and), ID($logic_or))) {
+		if (cell->type.in(TW($logic_and), TW($logic_or))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -612,7 +612,7 @@ struct XpropWorker
 			auto b_is_1 = module->ReduceOr(NEW_TWINE, enc_b.is_1);
 			auto b_is_0 = module->ReduceAnd(NEW_TWINE, enc_b.is_0);
 
-			if (cell->type == ID($logic_or))
+			if (cell->type == TW($logic_or))
 				 enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1);
 
 			enc_y.connect_0(module->Or(NEW_TWINE, a_is_0, b_is_0));
@@ -622,11 +622,11 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
+		if (cell->type.in(TW($xor), TW($xnor), TW($_XOR_), TW($_XNOR_))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
-			if (cell->type.in(ID($xor), ID($xnor))) {
+			if (cell->type.in(TW($xor), TW($xnor))) {
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
 			}
@@ -635,7 +635,7 @@ struct XpropWorker
 			auto enc_b = encoded(sig_b);
 			auto enc_y = encoded(sig_y, true);
 
-			if (cell->type.in(ID($xnor), ID($_XNOR_)))
+			if (cell->type.in(TW($xnor), TW($_XNOR_)))
 				enc_y.invert();
 
 			enc_y.connect_x(module->Or(NEW_TWINE, enc_a.is_x, enc_b.is_x));
@@ -645,7 +645,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($eq), ID($ne))) {
+		if (cell->type.in(TW($eq), TW($ne))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -658,7 +658,7 @@ struct XpropWorker
 			auto enc_y = encoded(sig_y, true);
 			enc_y.connect_as_bool();
 
-			if (cell->type == ID($ne))
+			if (cell->type == TW($ne))
 				enc_y.invert();
 
 			auto delta = module->Xor(NEW_TWINE, enc_a.is_1, enc_b.is_1);
@@ -671,7 +671,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($eqx), ID($nex))) {
+		if (cell->type.in(TW($eqx), TW($nex))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto sig_a = cell->getPort(TW::A);
 			auto sig_b = cell->getPort(TW::B);
@@ -687,7 +687,7 @@ struct XpropWorker
 
 			auto eq = module->ReduceAnd(NEW_TWINE, {delta_0, delta_1});
 
-			auto res = cell->type == ID($nex) ? module->Not(NEW_TWINE, eq) : eq;
+			auto res = cell->type == TW($nex) ? module->Not(NEW_TWINE, eq) : eq;
 
 			module->connect(sig_y[0], res);
 			if (GetSize(sig_y) > 1)
@@ -696,7 +696,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($bweqx))) {
+		if (cell->type.in(TW($bweqx))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -711,13 +711,13 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
+		if (cell->type.in(TW($_MUX_), TW($mux), TW($bwmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
 			auto sig_s = cell->getPort(TW::S);
 
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
 
 			auto enc_a = encoded(sig_a);
@@ -736,7 +736,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($pmux))) {
+		if (cell->type.in(TW($pmux))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -771,7 +771,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
+		if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx))) {
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
 			auto &sig_b = cell->getPort(TW::B);
@@ -787,9 +787,9 @@ struct XpropWorker
 			SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y));
 			SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y));
 
-			auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
+			auto encoded_type = cell->type == TW($shiftx) ? TW($shift) : cell->type;
 
-			if (cell->type == ID($shiftx)) {
+			if (cell->type == TW($shiftx)) {
 				std::swap(enc_a.is_0, enc_a.is_x);
 			}
 
@@ -813,7 +813,7 @@ struct XpropWorker
 
 			SigSpec y_0 = module->Not(NEW_TWINE, y_not_0);
 
-			if (cell->type == ID($shiftx))
+			if (cell->type == TW($shiftx))
 				std::swap(y_0, y_x);
 
 			enc_y.connect_0(module->And(NEW_TWINE, y_0, SigSpec(not_all_x, GetSize(sig_y))));
@@ -824,7 +824,7 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type.in(ID($ff))) {
+		if (cell->type.in(TW($ff))) {
 			auto &sig_d = cell->getPort(TW::D);
 			auto &sig_q = cell->getPort(TW::Q);
 
@@ -857,12 +857,12 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+		if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 			FfData ff(&initvals, cell);
 
 			if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
 				if (ff.has_clk && maybe_x(ff.sig_clk)) {
-					log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescape());
+					log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescaped());
 				} else {
 					auto init_q = ff.val_init;
 					auto init_q_is_1 = init_q;
@@ -907,15 +907,15 @@ struct XpropWorker
 					return;
 				}
 			} else {
-				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
+				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescaped());
 			}
 		}
 
 		// Celltypes where any input x bit makes the whole output x
 		if (cell->type.in(
-			ID($neg),
-			ID($le), ID($lt), ID($ge), ID($gt),
-			ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)
+			TW($neg),
+			TW($le), TW($lt), TW($ge), TW($gt),
+			TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor)
 		)) {
 
 			SigSpec inbits_x;
@@ -927,7 +927,7 @@ struct XpropWorker
 				}
 			}
 
-			if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+			if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 				auto sig_b = cell->getPort(TW::B);
 				auto invalid = module->LogicNot(NEW_TWINE, sig_b);
 				inbits_x.append(invalid);
@@ -937,7 +937,7 @@ struct XpropWorker
 
 			SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_TWINE, inbits_x));
 
-			bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt));
+			bool bool_out = cell->type.in(TW($le), TW($lt), TW($ge), TW($gt));
 
 			for (auto &conn : cell->connections()) {
 				if (cell->output(conn.first)) {
@@ -958,15 +958,15 @@ struct XpropWorker
 			return;
 		}
 
-		if (cell->type == ID($bmux)) // TODO might want to support bmux natively anyway
+		if (cell->type == TW($bmux)) // TODO might want to support bmux natively anyway
 			log("Running 'bmuxmap' preserves x-propagation and can be run before 'xprop'.\n");
-		if (cell->type == ID($demux)) // TODO might want to support demux natively anyway
+		if (cell->type == TW($demux)) // TODO might want to support demux natively anyway
 			log("Running 'demuxmap' preserves x-propagation and can be run before 'xprop'.\n");
 
 		if (options.required)
-			log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
+			log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
 		else
-			log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
+			log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescaped());
 	}
 
 	void split_ports()
diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index bd325e7ea..a489eee74 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -47,7 +47,7 @@ struct EquivInductWorker : public EquivWorker<>
 			if (!satgen.importCell(cell, step)) {
 				report_missing_model(cfg.ignore_unknown_cells, cell);
 			}
-			if (cell->type == ID($equiv)) {
+			if (cell->type == TW($equiv)) {
 				SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit();
 				SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit();
 				if (bit_a != bit_b) {
@@ -88,14 +88,14 @@ struct EquivInductWorker : public EquivWorker<>
 
 		if (satgen.model_undef) {
 			for (auto cell : cells)
-				if (yosys_celltypes.cell_known(cell->type))
+				if (yosys_celltypes.cell_known(cell->type_impl))
 					for (auto &conn : cell->connections())
-						if (yosys_celltypes.cell_input(cell->type, conn.first))
+						if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
 							undriven_signals.add(sigmap(conn.second));
 			for (auto cell : cells)
-				if (yosys_celltypes.cell_known(cell->type))
+				if (yosys_celltypes.cell_known(cell->type_impl))
 					for (auto &conn : cell->connections())
-						if (yosys_celltypes.cell_output(cell->type, conn.first))
+						if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
 							undriven_signals.del(sigmap(conn.second));
 		}
 
@@ -211,7 +211,7 @@ struct EquivInductPass : public Pass {
 			vector<Cell*> assume_cells;
 
 			for (auto cell : module->selected_cells())
-				if (cell->type == ID($equiv)) {
+				if (cell->type == TW($equiv)) {
 					if (cell->getPort(TW::A) != cell->getPort(TW::B))
 						unproven_equiv_cells.insert(cell);
 				}
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 6338db54b..185f95c4a 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -115,7 +115,7 @@ struct EquivMakeWorker
 			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				cell_names.insert(it->name);
 			gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"}));
-			if (it->type.in(ID($input_port), ID($output_port), ID($public)))
+			if (it->type.in(TW($input_port), TW($output_port), TW($public)))
 				gold_clone->remove(it);
 		}
 
@@ -129,7 +129,7 @@ struct EquivMakeWorker
 			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				cell_names.insert(it->name);
 			gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"}));
-			if (it->type.in(ID($input_port), ID($output_port), ID($public)))
+			if (it->type.in(TW($input_port), TW($output_port), TW($public)))
 				gate_clone->remove(it);
 		}
 
@@ -164,7 +164,7 @@ struct EquivMakeWorker
 
 			if (encdata.count(id))
 			{
-				log("Creating encoder/decoder for signal %s.\n", id.unescape());
+				log("Creating encoder/decoder for signal %s.\n", design->twines.unescaped_str(id));
 
 				Wire *dec_wire = equiv_mod->addWire(Twine{id.str() + "_decoded"}, gold_wire->width);
 				Wire *enc_wire = equiv_mod->addWire(Twine{id.str() + "_encoded"}, gate_wire->width);
@@ -239,7 +239,7 @@ struct EquivMakeWorker
 
 			log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
 					gold_wire, log_signal(assign_map(gold_wire)),
-					gate_wire, log_signal(assign_map(gate_wire)), id.unescape());
+					gate_wire, log_signal(assign_map(gate_wire)), design->twines.unescaped_str(id));
 
 			if (gold_wire->port_output || gate_wire->port_output)
 			{
@@ -310,7 +310,7 @@ struct EquivMakeWorker
 
 		for (auto c : cells_list)
 		for (auto &conn : c->connections())
-			if (!ct.cell_output(c->type, conn.first)) {
+			if (!ct.cell_output(c->type_impl, conn.first)) {
 				SigSpec old_sig = assign_map(conn.second);
 				SigSpec new_sig = rd_signal_map(old_sig);
 				for (int i = 0; i < GetSize(old_sig); i++)
@@ -318,7 +318,7 @@ struct EquivMakeWorker
 						new_sig[i] = old_sig[i];
 				if (old_sig != new_sig) {
 					log("Changing input %s of cell %s (%s): %s -> %s\n",
-							equiv_mod->design->twines.str(conn.first).c_str(), c, c->type.unescape(),
+							equiv_mod->design->twines.str(conn.first).c_str(), c, design->twines.unescaped_str(c->type),
 							log_signal(old_sig), log_signal(new_sig));
 					c->setPort(conn.first, new_sig);
 				}
@@ -339,7 +339,7 @@ struct EquivMakeWorker
 			Cell *gold_cell = equiv_mod->cell(gold_id);
 			Cell *gate_cell = equiv_mod->cell(gate_id);
 
-			if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) ||
+			if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type_impl) ||
 					gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections()))
 		try_next_cell_name:
 				continue;
@@ -349,14 +349,14 @@ struct EquivMakeWorker
 					goto try_next_cell_name;
 
 			log("Presumably equivalent cells: %s %s (%s) -> %s\n",
-					gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape());
+					gold_cell, gate_cell, design->twines.unescaped_str(gold_cell->type), design->twines.unescaped_str(id));
 
 			for (auto gold_conn : gold_cell->connections())
 			{
 				SigSpec gold_sig = assign_map(gold_conn.second);
 				SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first));
 
-				if (ct.cell_output(gold_cell->type, gold_conn.first)) {
+				if (ct.cell_output(gold_cell->type_impl, gold_conn.first)) {
 					equiv_mod->connect(gate_sig, gold_sig);
 					continue;
 				}
@@ -403,7 +403,7 @@ struct EquivMakeWorker
 
 		for (auto cell : equiv_mod->cells()) {
 			for (auto &conn : cell->connections())
-				if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
+				if (!ct.cell_known(cell->type_impl) || ct.cell_output(cell->type_impl, conn.first))
 					for (auto bit : assign_map(conn.second))
 						undriven_bits.erase(bit);
 		}
diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
index fad66b3ab..9d26d9d32 100644
--- a/passes/equiv/equiv_mark.cc
+++ b/passes/equiv/equiv_mark.cc
@@ -48,7 +48,7 @@ struct EquivMarkWorker
 	{
 		for (auto cell : module->cells())
 		{
-			if (cell->type == ID($equiv))
+			if (cell->type == TW($equiv))
 				equiv_cells.insert(cell->meta_->name);
 
 			for (auto &port : cell->connections())
@@ -139,7 +139,7 @@ struct EquivMarkWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell_regions.count(cell->meta_->name) || cell->type != ID($equiv))
+			if (cell_regions.count(cell->meta_->name) || cell->type != TW($equiv))
 				continue;
 
 			SigSpec sig_a = sigmap(cell->getPort(TW::A));
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index b72348822..5a0754394 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -47,7 +47,7 @@ struct EquivMiterWorker
 		if (cone.count(c))
 			return;
 
-		if (c->type == ID($equiv) && !seed_cells.count(c)) {
+		if (c->type == TW($equiv) && !seed_cells.count(c)) {
 			leaves.insert(c);
 			return;
 		}
@@ -55,9 +55,9 @@ struct EquivMiterWorker
 		cone.insert(c);
 
 		for (auto &conn : c->connections()) {
-			if (!ct.cell_input(c->type, conn.first))
+			if (!ct.cell_input(c->type_impl, conn.first))
 				continue;
-			if (c->type == ID($equiv) && (conn.first == TW::A) != gold_mode)
+			if (c->type == TW($equiv) && (conn.first == TW::A) != gold_mode)
 				continue;
 			for (auto bit : sigmap(conn.second))
 				if (bit_to_driver.count(bit))
@@ -73,7 +73,7 @@ struct EquivMiterWorker
 
 		for (auto c : source_module->cells())
 			for (auto &conn : c->connections())
-				if (ct.cell_output(c->type, conn.first))
+				if (ct.cell_output(c->type_impl, conn.first))
 					for (auto bit : sigmap(conn.second))
 						if (bit.wire)
 							bit_to_driver[bit] = c;
@@ -81,7 +81,7 @@ struct EquivMiterWorker
 		// find seed cells
 
 		for (auto c : source_module->selected_cells())
-			if (c->type == ID($equiv)) {
+			if (c->type == TW($equiv)) {
 				log("Seed $equiv cell: %s\n", c);
 				seed_cells.insert(c);
 			}
@@ -143,7 +143,7 @@ struct EquivMiterWorker
 		for (auto w :  miter_wires)
 			miter_module->addWire(Twine{w->name.str()}, w->width);
 		for (auto c :  miter_cells) {
-			if (c->type.in(ID($input_port), ID($output_port), ID($public)))
+			if (c->type.in(TW($input_port), TW($output_port), TW($public)))
 				continue;
 			auto mc = miter_module->addCell(Twine{c->name.str()}, c);
 			for (auto &conn : mc->connections())
@@ -175,11 +175,11 @@ struct EquivMiterWorker
 
 		for (auto c : miter_module->cells())
 		for (auto &conn : c->connections()) {
-			if (ct.cell_input(c->type, conn.first))
+			if (ct.cell_input(c->type_impl, conn.first))
 				for (auto bit : conn.second)
 					if (bit.wire)
 						used_bits.insert(bit);
-			if (ct.cell_output(c->type, conn.first))
+			if (ct.cell_output(c->type_impl, conn.first))
 				for (auto bit : conn.second)
 					if (bit.wire)
 						driven_bits.insert(bit);
@@ -214,7 +214,7 @@ struct EquivMiterWorker
 		vector<Cell*> equiv_cells;
 
 		for (auto c : miter_module->cells())
-			if (c->type == ID($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
+			if (c->type == TW($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
 				equiv_cells.push_back(c);
 
 		for (auto c : equiv_cells)
@@ -324,7 +324,7 @@ struct EquivMiterPass : public Pass {
 		design->sigNormalize(false);
 
 		if (design->module(design->twines.lookup(worker.miter_name.str())))
-			log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape());
+			log_cmd_error("Miter module %s already exists.\n", design->twines.unescaped_str(worker.miter_name));
 
 		worker.source_module = nullptr;
 		for (auto m : design->selected_modules()) {
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index 10ce5f862..0ef35946e 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -37,7 +37,7 @@ struct EquivPurgeWorker
 			Wire *wire = sig.as_wire();
 			if (wire->name.isPublic()) {
 				if (!wire->port_output) {
-					log("  Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
+					log("  Module output: %s (%s)\n", log_signal(wire), design->twines.unescaped_str(cellname));
 					wire->port_output = true;
 				}
 				return wire;
@@ -53,7 +53,7 @@ struct EquivPurgeWorker
 			Wire *wire = module->addWire(Twine{name}, GetSize(sig));
 			wire->port_output = true;
 			module->connect(wire, sig);
-			log("  Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
+			log("  Module output: %s (%s)\n", log_signal(wire), design->twines.unescaped_str(cellname));
 			return wire;
 		}
 	}
@@ -102,7 +102,7 @@ struct EquivPurgeWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type != ID($equiv)) {
+			if (cell->type != TW($equiv)) {
 				for (auto &port : cell->connections()) {
 					if (cell->input(port.first))
 						for (auto bit : sigmap(port.second))
@@ -167,7 +167,7 @@ struct EquivPurgeWorker
 				rewrite_sigmap.add(chunk, make_input(chunk));
 
 		for (auto cell : module->cells())
-			if (cell->type == ID($equiv))
+			if (cell->type == TW($equiv))
 				cell->setPort(TW::Y, rewrite_sigmap(sigmap(cell->getPort(TW::Y))));
 
 		module->fixup_ports();
diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc
index 0926e2492..b60df609d 100644
--- a/passes/equiv/equiv_remove.cc
+++ b/passes/equiv/equiv_remove.cc
@@ -68,7 +68,7 @@ struct EquivRemovePass : public Pass {
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
-				if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
+				if (cell->type == TW($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
 					log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(TW::Y)));
 					module->connect(cell->getPort(TW::Y), mode_gate ? cell->getPort(TW::B) : cell->getPort(TW::A));
 					module->remove(cell);
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index 95c7d80b4..e1f4cb89b 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -111,7 +111,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
 				return true;
 
 			for (auto &conn : cell->connections())
-				if (yosys_celltypes.cell_input(cell->type, conn.first))
+				if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
 					for (auto bit : model.sigmap(conn.second)) {
 						if (cell->is_builtin_ff()) {
 							if (conn.first != TW::CLK && conn.first != TW::C)
@@ -461,14 +461,14 @@ struct EquivSimplePass : public Pass {
 			int unproven_cells_counter = 0;
 
 			for (auto cell : module->selected_cells()) {
-				if (cell->type == ID($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
+				if (cell->type == TW($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
 					auto bit = sigmap(cell->getPort(TW::Y).as_bit());
 					auto bit_group = bit;
 					if (cfg.group && bit_group.wire)
 						bit_group.offset = 0;
 					unproven_equiv_cells[bit_group][bit] = cell;
 					unproven_cells_counter++;
-				} else if (cell->type == ID($assume)) {
+				} else if (cell->type == TW($assume)) {
 					assumes.push_back(cell);
 				}
 			}
@@ -480,10 +480,10 @@ struct EquivSimplePass : public Pass {
 					unproven_cells_counter, GetSize(unproven_equiv_cells), module);
 
 			for (auto cell : module->cells()) {
-				if (!ct.cell_known(cell->type))
+				if (!ct.cell_known(cell->type_impl))
 					continue;
 				for (auto &conn : cell->connections())
-					if (yosys_celltypes.cell_output(cell->type, conn.first))
+					if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
 						for (auto bit : sigmap(conn.second))
 							bit2driver[bit] = cell;
 			}
diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc
index aabc03b1f..6b33a9317 100644
--- a/passes/equiv/equiv_status.cc
+++ b/passes/equiv/equiv_status.cc
@@ -59,7 +59,7 @@ struct EquivStatusPass : public Pass {
 			int proven_equiv_cells = 0;
 
 			for (auto cell : module->selected_cells())
-				if (cell->type == ID($equiv)) {
+				if (cell->type == TW($equiv)) {
 					if (cell->getPort(TW::A) != cell->getPort(TW::B))
 						unproven_equiv_cells.push_back(cell);
 					else
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index a58cd7832..39291b6fb 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -124,7 +124,7 @@ struct EquivStructWorker
 		pool<TwineRef> cells;
 
 		for (auto cell : module->selected_cells())
-			if (cell->type == ID($equiv)) {
+			if (cell->type == TW($equiv)) {
 				SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
 				equiv_bits.add(sig_b, sig_a);
@@ -137,7 +137,7 @@ struct EquivStructWorker
 			}
 
 		for (auto cell : module->selected_cells())
-			if (cell->type == ID($equiv)) {
+			if (cell->type == TW($equiv)) {
 				SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
 				SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
 				SigBit sig_y = sigmap(cell->getPort(TW::Y).as_bit());
@@ -264,7 +264,7 @@ struct EquivStructWorker
 			run_strategy:
 				int total_group_size = GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells);
 				log("    %s merging %d %s cells (from group of %d) using strategy %s:\n", phase ? "Bwd" : "Fwd",
-						2*GetSize(cell_pairs), cells_type.unescape(), total_group_size, strategy);
+						2*GetSize(cell_pairs), design->twines.unescaped_str(cells_type), total_group_size, strategy);
 				for (auto it : cell_pairs) {
 					log("      Merging cells %s and %s.\n", it.first,  it.second);
 					merge_cell_pair(it.first, it.second);
@@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
-		pool<IdString> fwonly_cells({ ID($equiv) });
+		pool<IdString> fwonly_cells({ TW($equiv) });
 		bool mode_icells = false;
 		bool mode_fwd = false;
 		int max_iter = -1;
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index cb17b0e7a..6593794bb 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -55,7 +55,7 @@ ret_false:
 	sig2driver.find(sig, cellport_list);
 	for (auto &cellport : cellport_list)
 	{
-		if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != TW::Y) {
+		if ((cellport.first->type != TW($mux) && cellport.first->type != TW($pmux)) || cellport.second != TW::Y) {
 			goto ret_false;
 		}
 
@@ -99,9 +99,9 @@ static bool check_state_users(RTLIL::SigSpec sig)
 		RTLIL::Cell *cell = cellport.first;
 		if (muxtree_cells.count(cell) > 0)
 			continue;
-		if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+		if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 			continue;
-		if (cell->type == ID($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
+		if (cell->type == TW($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
 			continue;
 		if (cellport.second != TW::A && cellport.second != TW::B)
 			return false;
@@ -145,7 +145,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
 
 	for (auto &cellport : cellport_list)
 	{
-		if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != TW::Q)
+		if ((cellport.first->type != TW($dff) && cellport.first->type != TW($adff)) || cellport.second != TW::Q)
 			continue;
 
 		muxtree_cells.clear();
@@ -175,10 +175,10 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
 			RTLIL::Cell *cell = cellport.first;
 			bool set_output = false, clr_output = false;
 
-			if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
+			if (cell->type.in(TW($ne), TW($reduce_or), TW($reduce_bool)))
 				set_output = true;
 
-			if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
+			if (cell->type.in(TW($eq), TW($logic_not), TW($reduce_and)))
 				clr_output = true;
 
 			if (set_output || clr_output) {
@@ -202,7 +202,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
 
 		SigSpec sig_y = sig_d, sig_undef;
 		if (!ignore_self_reset) {
-			if (cellport.first->type == ID($adff)) {
+			if (cellport.first->type == TW($adff)) {
 				SigSpec sig_arst = assign_map(cellport.first->getPort(TW::ARST));
 				if (ce.eval(sig_arst, sig_undef))
 					is_self_resetting = true;
@@ -328,12 +328,12 @@ struct FsmDetectPass : public Pass {
 			sig_at_port.clear();
 			for (auto cell : module->cells())
 				for (auto &conn_it : cell->connections()) {
-					if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
+					if (ct.cell_output(cell->type_impl, conn_it.first) || !ct.cell_known(cell->type_impl)) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
 					}
-					if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
+					if (!ct.cell_known(cell->type_impl) || ct.cell_input(cell->type_impl, conn_it.first)) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 9b2e03bf6..3e0609ca8 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -47,10 +47,10 @@ struct FsmExpand
 
 	bool is_cell_merge_candidate(RTLIL::Cell *cell)
 	{
-		if (full_mode || cell->type == ID($_MUX_))
+		if (full_mode || cell->type == TW($_MUX_))
 			return true;
 
-		if (cell->type.in(ID($mux), ID($pmux)))
+		if (cell->type.in(TW($mux), TW($pmux)))
 			if (cell->getPort(TW::A).size() < 2)
 				return true;
 
@@ -147,7 +147,7 @@ struct FsmExpand
 		RTLIL::SigSpec input_sig, output_sig;
 
 		for (auto &p : cell->connections())
-			if (ct.cell_output(cell->type, p.first))
+			if (ct.cell_output(cell->type_impl, p.first))
 				output_sig.append(assign_map(p.second));
 			else
 				input_sig.append(assign_map(p.second));
@@ -189,7 +189,7 @@ struct FsmExpand
 
 		if (GetSize(input_sig) > 10)
 			log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
-					cell->module, cell, cell->type.unescape(),
+					cell->module, cell, cell->type.unescaped(),
 					GetSize(input_sig), fsm_cell->module, fsm_cell);
 
 		if (GetSize(fsm_data.transition_table) > 10000)
@@ -230,9 +230,9 @@ struct FsmExpand
 
 		for (auto &cell_it : module->cells_) {
 			RTLIL::Cell *c = cell_it.second;
-			if (ct.cell_known(c->type) && design->selected(mod, c))
+			if (ct.cell_known(c->type_impl) && design->selected(mod, c))
 				for (auto &p : c->connections()) {
-					if (ct.cell_output(c->type, p.first))
+					if (ct.cell_output(c->type_impl, p.first))
 						sig2driver.insert(assign_map(p.second), c);
 					else
 						sig2user.insert(assign_map(p.second), c);
@@ -298,7 +298,7 @@ struct FsmExpandPass : public Pass {
 		for (auto mod : design->selected_modules()) {
 			std::vector<RTLIL::Cell*> fsm_cells;
 			for (auto cell : mod->selected_cells())
-				if (cell->type == ID($fsm))
+				if (cell->type == TW($fsm))
 					fsm_cells.push_back(cell);
 			for (auto c : fsm_cells) {
 				FsmExpand fsm_expand(c, design, mod, full_mode);
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index 6fc4f0d19..345bff08a 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -175,7 +175,7 @@ struct FsmExportPass : public Pass {
 
 		for (auto mod : design->selected_modules())
 			for (auto cell : mod->selected_cells())
-				if (cell->type == ID($fsm)) {
+				if (cell->type == TW($fsm)) {
 					attr_it = cell->attributes.find(ID::fsm_export);
 					if (!flag_noauto || (attr_it != cell->attributes.end())) {
 						write_kiss2(mod, cell, filename, flag_origenc);
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 1b0943f1e..fea1d3ffd 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -70,7 +70,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 	for (auto &cellport : cellport_list)
 	{
 		RTLIL::Cell *cell = module->cell(cellport.first);
-		if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != TW::Y) {
+		if ((cell->type != TW($mux) && cell->type != TW($pmux)) || cellport.second != TW::Y) {
 			log("  unexpected cell type %s (%s) found in state selection tree.\n", cell->type, log_id(cell));
 			return false;
 		}
@@ -272,14 +272,14 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2driver.find(dff_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cell(cellport.first);
-		if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != TW::Q)
+		if ((cell->type != TW($dff) && cell->type != TW($adff)) || cellport.second != TW::Q)
 			continue;
 		log("  found %s cell for state register: %s\n", cell->type, log_id(cell));
 		RTLIL::SigSpec sig_q = assign_map(cell->getPort(TW::Q));
 		RTLIL::SigSpec sig_d = assign_map(cell->getPort(TW::D));
 		clk = cell->getPort(TW::CLK);
 		clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
-		if (cell->type == ID($adff)) {
+		if (cell->type == TW($adff)) {
 			arst = cell->getPort(TW::ARST);
 			arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
 			reset_state = cell->parameters[ID::ARST_VALUE];
@@ -368,7 +368,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 
 	// create fsm cell
 
-	RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, ID($fsm));
+	RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, TW($fsm));
 	fsm_cell->setPort(TW::CLK, clk);
 	fsm_cell->setPort(TW::ARST, arst);
 	fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
@@ -446,19 +446,19 @@ struct FsmExtractPass : public Pass {
 			exclusive_ctrls.clear();
 			for (auto cell : module->cells()) {
 				for (auto &conn_it : cell->connections()) {
-					if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
+					if (ct.cell_output(cell->type_impl, conn_it.first) || !ct.cell_known(cell->type_impl)) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2driver.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first));
 					}
-					if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(TW::Y) &&
+					if (ct.cell_input(cell->type_impl, conn_it.first) && cell->hasPort(TW::Y) &&
 							cell->getPort(TW::Y).size() == 1 && (conn_it.first == TW::A || conn_it.first == TW::B)) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2trigger.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first));
 					}
 				}
-				if (cell->type == ID($pmux)) {
+				if (cell->type == TW($pmux)) {
 					RTLIL::SigSpec sel_sig = assign_map(cell->getPort(TW::S));
 					for (auto &bit1 : sel_sig)
 					for (auto &bit2 : sel_sig)
diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc
index 7b3b59ee9..a60c4fd3b 100644
--- a/passes/fsm/fsm_info.cc
+++ b/passes/fsm/fsm_info.cc
@@ -48,7 +48,7 @@ struct FsmInfoPass : public Pass {
 
 		for (auto mod : design->selected_modules())
 			for (auto cell : mod->selected_cells())
-				if (cell->type == ID($fsm)) {
+				if (cell->type == TW($fsm)) {
 					log("\n");
 					log("FSM `%s' from module `%s':\n", cell, mod);
 					FsmData fsm_data;
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 0b1f0ae28..62386154e 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -74,7 +74,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			RTLIL::Wire *eq_wire = module->addWire(NEW_TWINE);
 			and_sig.append(RTLIL::SigSpec(eq_wire));
 
-			RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
+			RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, TW($eq));
 			eq_cell->setPort(TW::A, eq_sig_a);
 			eq_cell->setPort(TW::B, eq_sig_b);
 			eq_cell->setPort(TW::Y, RTLIL::SigSpec(eq_wire));
@@ -102,7 +102,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				RTLIL::Wire *or_wire = module->addWire(NEW_TWINE);
 				and_sig.append(RTLIL::SigSpec(or_wire));
 
-				RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
+				RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
 				or_cell->setPort(TW::A, or_sig);
 				or_cell->setPort(TW::Y, RTLIL::SigSpec(or_wire));
 				or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
@@ -118,7 +118,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				RTLIL::Wire *and_wire = module->addWire(NEW_TWINE);
 				cases_vector.append(RTLIL::SigSpec(and_wire));
 
-				RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, ID($and));
+				RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, TW($and));
 				and_cell->setPort(TW::A, and_sig.extract(0, 1));
 				and_cell->setPort(TW::B, and_sig.extract(1, 1));
 				and_cell->setPort(TW::Y, RTLIL::SigSpec(and_wire));
@@ -141,7 +141,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 	}
 
 	if (cases_vector.size() > 1) {
-		RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
+		RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
 		or_cell->setPort(TW::A, cases_vector);
 		or_cell->setPort(TW::Y, output);
 		or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
@@ -212,7 +212,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		{
 			encoding_is_onehot = false;
 
-			RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
+			RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, TW($eq));
 			eq_cell->setPort(TW::A, sig_a);
 			eq_cell->setPort(TW::B, sig_b);
 			eq_cell->setPort(TW::Y, RTLIL::SigSpec(state_onehot, i));
@@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 				}
 			}
 
-			RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, ID($pmux));
+			RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, TW($pmux));
 			mux_cell->setPort(TW::A, sig_a);
 			mux_cell->setPort(TW::B, sig_b);
 			mux_cell->setPort(TW::S, sig_s);
@@ -339,7 +339,7 @@ struct FsmMapPass : public Pass {
 		for (auto mod : design->selected_modules()) {
 			std::vector<RTLIL::Cell*> fsm_cells;
 			for (auto cell : mod->selected_cells())
-				if (cell->type == ID($fsm))
+				if (cell->type == TW($fsm))
 					fsm_cells.push_back(cell);
 			for (auto cell : fsm_cells)
 					map_fsm(cell, mod);
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index e26b67456..b0f32de18 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -348,7 +348,7 @@ struct FsmOptPass : public Pass {
 
 		for (auto mod : design->selected_modules())
 			for (auto cell : mod->selected_cells())
-				if (cell->type == ID($fsm))
+				if (cell->type == TW($fsm))
 					FsmData::optimize_fsm(cell, mod);
 	}
 } FsmOptPass;
diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc
index f05e24fd9..9fb3950a1 100644
--- a/passes/fsm/fsm_recode.cc
+++ b/passes/fsm/fsm_recode.cc
@@ -184,7 +184,7 @@ struct FsmRecodePass : public Pass {
 
 		for (auto mod : design->selected_modules())
 			for (auto cell : mod->selected_cells())
-				if (cell->type == ID($fsm))
+				if (cell->type == TW($fsm))
 					fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding);
 
 		if (fm_set_fsm_file != NULL)
diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc
index 51cd7809e..139a6dd00 100644
--- a/passes/hierarchy/flatten.cc
+++ b/passes/hierarchy/flatten.cc
@@ -209,7 +209,7 @@ struct FlattenWorker
 		}
 
 		for (auto tpl_cell : tpl->cells()) {
-			if (tpl_cell->type.in(ID($input_port), ID($output_port), ID($public)))
+			if (tpl_cell->type.in(TW($input_port), TW($output_port), TW($public)))
 				continue;
 			RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell, separator), tpl_cell);
 			map_attributes(cell, new_cell, tpl_cell->name);
@@ -308,7 +308,7 @@ struct FlattenWorker
 		if (create_scopeinfo && cell_name.isPublic())
 		{
 			// The $scopeinfo's name will be changed below after removing the flattened cell
-			scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo));
+			scopeinfo = module->addCell(NEW_TWINE, TW($scopeinfo));
 			scopeinfo->setParam(ID::TYPE, RTLIL::Const("module"));
 
 			for (auto const &attr : cell->attributes)
@@ -316,7 +316,7 @@ struct FlattenWorker
 				if (attr.first == ID::hdlname)
 					scopeinfo->attributes.insert(attr);
 				else
-					scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second);
+					scopeinfo->attributes.emplace(stringf("\\cell_%s", design->twines.unescaped_str(attr.first)), attr.second);
 			}
 			// src lives outside cell->attributes after the typed-src
 			// migration — fold it into the renamed-attribute view by
@@ -325,7 +325,7 @@ struct FlattenWorker
 				scopeinfo->attributes.emplace(ID(cell_src), RTLIL::Const(cell->get_src_attribute()));
 
 			for (auto const &attr : tpl->attributes)
-				scopeinfo->attributes.emplace(stringf("\\module_%s", attr.first.unescape()), attr.second);
+				scopeinfo->attributes.emplace(stringf("\\module_%s", design->twines.unescaped_str(attr.first)), attr.second);
 			if (tpl->src_id() != Twine::Null)
 				scopeinfo->attributes.emplace(ID(module_src), RTLIL::Const(tpl->get_src_attribute()));
 
@@ -364,7 +364,7 @@ struct FlattenWorker
 				continue;
 			}
 
-			log_debug("Flattening %s.%s (%s).\n", module, cell, cell->type.unescape());
+			log_debug("Flattening %s.%s (%s).\n", module, cell, cell->type.unescaped());
 			// If a design is fully selected and has a top module defined, topological sorting ensures that all cells
 			// added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
 			// individual modules, this isn't the case, and the newly added cells might have to be flattened further.
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index dd2455bc3..5ce34119f 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -50,7 +50,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 		if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
 			continue;
 		for (auto &pattern : celltypes)
-			if (patmatch(pattern.c_str(), cell->type.unescape().c_str()))
+			if (patmatch(pattern.c_str(), cell->type.unescaped().c_str()))
 				found_celltypes.insert(cell->type);
 	}
 
@@ -132,7 +132,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 		mod->fixup_ports();
 
 		for (auto &para : parameters)
-			log("  ignoring parameter %s.\n", para.unescape());
+			log("  ignoring parameter %s.\n", design->twines.unescaped_str(para));
 
 		log("  module %s created.\n", mod);
 	}
@@ -238,7 +238,7 @@ struct IFExpander
 		// about it and don't set has_interfaces_not_found (to avoid a
 		// loop).
 		log_warning("Could not find interface instance for `%s' in `%s'\n",
-			    interface_name.unescape(), &module);
+			    design->twines.unescaped_str(interface_name), &module);
 	}
 
 	// Handle an interface connection from the module
@@ -282,8 +282,8 @@ struct IFExpander
 		// Go over all wires in interface, and add replacements to lists.
 		std::string conn_name_str(design.twines.str(conn_name));
 		for (auto mod_wire : mod_replace_ports->wires()) {
-			std::string signal_name1 = conn_name_str + "." + mod_wire->name.unescape();
-			std::string signal_name2 = interface_name.str() + "." + mod_wire->name.unescape();
+			std::string signal_name1 = conn_name_str + "." + design->twines.unescaped_str(mod_wire->name);
+			std::string signal_name2 = interface_name.str() + "." + design->twines.unescaped_str(mod_wire->name);
 			connections_to_add.push_back(design.twines.add(Twine{signal_name1}));
 			TwineRef signal_name2_ref = design.twines.lookup(signal_name2);
 			if(module.wire(signal_name2_ref) == nullptr) {
@@ -412,7 +412,7 @@ RTLIL::Module *get_module(RTLIL::Design                  &design,
 			};
 
 		for (auto &ext : extensions_list) {
-			std::string filename = dir + "/" + cell.type.unescape() + ext.first;
+			std::string filename = dir + "/" + design->twines.unescaped_str(cell.type) + ext.first;
 			if (!check_file_exists(filename))
 				continue;
 
@@ -447,7 +447,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
 			if (id <= 0 || id > GetSize(mod.ports))
 				log_error("Module `%s' referenced in module `%s' in cell `%s' "
 				          "has only %d ports, requested port %d.\n",
-				          cell.type.unescape(), &module, &cell,
+				          design->twines.unescaped_str(cell.type), &module, &cell,
 				          GetSize(mod.ports), id);
 			continue;
 		}
@@ -456,7 +456,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
 		if (!wire || wire->port_id == 0) {
 			log_error("Module `%s' referenced in module `%s' in cell `%s' "
 			          "does not have a port named '%s'.\n",
-			          cell.type.unescape(), &module, &cell,
+			          design->twines.unescaped_str(cell.type), &module, &cell,
 			          module.design->twines.str(conn.first).data());
 		}
 	}
@@ -465,7 +465,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
 			if (id <= 0 || id > GetSize(mod.avail_parameters))
 				log_error("Module `%s' referenced in module `%s' in cell `%s' "
 				          "has only %d parameters, requested parameter %d.\n",
-				          cell.type.unescape(), &module, &cell,
+				          design->twines.unescaped_str(cell.type), &module, &cell,
 				          GetSize(mod.avail_parameters), id);
 			continue;
 		}
@@ -475,8 +475,8 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
 		    strchr(param.first.c_str(), '.') == NULL) {
 			log_error("Module `%s' referenced in module `%s' in cell `%s' "
 			          "does not have a parameter named '%s'.\n",
-			          cell.type.unescape(), &module, &cell,
-			          param.first.unescape());
+			          design->twines.unescaped_str(cell.type), &module, &cell,
+			          design->twines.unescaped_str(param.first));
 		}
 	}
 }
@@ -619,7 +619,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 		int idx = it.second.first, num = it.second.second;
 
 		if (design->module(cell->type) == nullptr)
-			log_error("Array cell `%s.%s' of unknown type `%s'.\n", module, cell, cell->type.unescape());
+			log_error("Array cell `%s.%s' of unknown type `%s'.\n", module, cell, cell->type.unescaped());
 
 		RTLIL::Module *mod = design->module(cell->type);
 
@@ -715,7 +715,7 @@ bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 			if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()}))
 				continue;
 			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
+			if ((m != nullptr && set_keep_print(cache, m)) || c->type == TW($print))
 				return cache[mod] = true;
 		}
 	return cache[mod];
@@ -728,7 +728,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 			if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()}))
 				continue;
 			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(TW($check), TW($assert), TW($assume), TW($live), TW($fair), TW($cover)))
 				return cache[mod] = true;
 		}
 	return cache[mod];
@@ -1221,7 +1221,7 @@ struct HierarchyPass : public Pass {
 		if (flag_simcheck || flag_smtcheck) {
 			for (auto mod : design->modules()) {
 				for (auto cell : mod->cells()) {
-					if (!cell->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+					if (!cell->type.in(TW($check), TW($assert), TW($assume), TW($live), TW($fair), TW($cover)))
 						continue;
 					if (!cell->has_attribute(ID(unsupported_sva)))
 						continue;
@@ -1263,7 +1263,7 @@ struct HierarchyPass : public Pass {
 					if (read_id_num(p.first, &id)) {
 						if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) {
 							log("  Failed to map positional parameter %d of cell %s.%s (%s).\n",
-									id, mod, cell, cell->type.unescape());
+									id, mod, cell, cell->type.unescaped());
 						} else {
 							params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1]));
 						}
@@ -1285,7 +1285,7 @@ struct HierarchyPass : public Pass {
 				RTLIL::Module *module = work.first;
 				RTLIL::Cell *cell = work.second;
 				log("Mapping positional arguments of cell %s.%s (%s).\n",
-						module, cell, cell->type.unescape());
+						module, cell, cell->type.unescaped());
 				dict<TwineRef, RTLIL::SigSpec> new_connections_twine;
 				for (auto &conn : cell->connections()) {
 					int id;
@@ -1293,7 +1293,7 @@ struct HierarchyPass : public Pass {
 						std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
 						if (pos_map.count(key) == 0) {
 							log("  Failed to map positional argument %d of cell %s.%s (%s).\n",
-									id, module, cell, cell->type.unescape());
+									id, module, cell, cell->type.unescaped());
 							new_connections_twine[conn.first] = conn.second;
 						} else
 							new_connections_twine[design->twines.add(Twine{pos_map.at(key).str()})] = conn.second;
@@ -1327,7 +1327,7 @@ struct HierarchyPass : public Pass {
 
 				if (m == nullptr)
 					log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n",
-							module, cell, cell->type.unescape());
+							module, cell, cell->type.unescaped());
 
 				// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
 				if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
@@ -1356,11 +1356,11 @@ struct HierarchyPass : public Pass {
 
 					if (parent_wire == nullptr)
 						log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n",
-								wire, module, cell, cell->type.unescape());
+								wire, module, cell, cell->type.unescaped());
 					if (parent_wire->width != wire->width)
 						log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n",
 								parent_wire->width, wire->width,
-								wire, module, cell, cell->type.unescape());
+								wire, module, cell, cell->type.unescaped());
 					cell->setPort(wire->meta_->name, parent_wire);
 				}
 				cell->attributes.erase(ID::wildcard_port_conns);
@@ -1578,7 +1578,7 @@ struct HierarchyPass : public Pass {
 
 					if (w->port_output && !w->port_input && sig.has_const())
 						log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
-								module, cell, design->twines.str(conn.first).data(), cell->type.unescape(), log_signal(sig));
+								module, cell, design->twines.str(conn.first).data(), cell->type.unescaped(), log_signal(sig));
 				}
 			}
 		}
diff --git a/passes/hierarchy/keep_hierarchy.cc b/passes/hierarchy/keep_hierarchy.cc
index aa3ac72e3..18cbec3b2 100644
--- a/passes/hierarchy/keep_hierarchy.cc
+++ b/passes/hierarchy/keep_hierarchy.cc
@@ -61,7 +61,7 @@ struct ThresholdHierarchyKeeping {
 				RTLIL::Module *submodule = design->module(cell->type);
 				if (!submodule)
 					log_error("Hierarchy contains unknown module '%s' (instanced as %s in %s)\n",
-							  cell->type.unescape(), cell, module);
+							  cell->type.unescaped(), cell, module);
 				size += visit(submodule);
 			}
 		}
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 9203718e5..5d90a561e 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -91,9 +91,9 @@ struct SubmodWorker
 
 		wire_flags.clear();
 		for (RTLIL::Cell *cell : submod.cells) {
-			if (ct.cell_known(cell->type)) {
+			if (ct.cell_known(cell->type_impl)) {
 				for (auto &conn : cell->connections())
-					flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
+					flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type_impl, conn.first), false, false);
 			} else {
 				log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type);
 				for (auto &conn : cell->connections())
@@ -103,9 +103,9 @@ struct SubmodWorker
 		for (auto cell : module->cells()) {
 			if (submod.cells.count(cell) > 0)
 				continue;
-			if (ct.cell_known(cell->type)) {
+			if (ct.cell_known(cell->type_impl)) {
 				for (auto &conn : cell->connections())
-					flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first));
+					flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type_impl, conn.first));
 			} else {
 				flag_found_something = false;
 				for (auto &conn : cell->connections())
diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
index de59d3799..03aced9de 100644
--- a/passes/hierarchy/uniquify.cc
+++ b/passes/hierarchy/uniquify.cc
@@ -84,7 +84,7 @@ struct UniquifyPass : public Pass {
 					if (tmod->get_bool_attribute(ID::unique) && newname_ref == tmod->meta_->name)
 						continue;
 
-					log("Creating module %s from %s.\n", newname.unescape(), tmod);
+					log("Creating module %s from %s.\n", design->twines.unescaped_str(newname), tmod);
 
 					auto smod = tmod->clone();
 					smod->meta_->name = newname_ref;
diff --git a/passes/memory/memlib.h b/passes/memory/memlib.h
index 7394baf4e..0d4116632 100644
--- a/passes/memory/memlib.h
+++ b/passes/memory/memlib.h
@@ -140,7 +140,7 @@ struct RamClock {
 };
 
 struct Ram {
-	IdString id;
+	TwineRef id;
 	RamKind kind;
 	dict<std::string, Const> options;
 	std::vector<PortGroup> port_groups;
diff --git a/passes/memory/memory_bmux2rom.cc b/passes/memory/memory_bmux2rom.cc
index 105afd392..97d7c5412 100644
--- a/passes/memory/memory_bmux2rom.cc
+++ b/passes/memory/memory_bmux2rom.cc
@@ -47,7 +47,7 @@ struct MemoryBmux2RomPass : public Pass {
 
 		for (auto module : design->selected_modules()) {
 			for (auto cell : module->selected_cells()) {
-				if (cell->type != ID($bmux))
+				if (cell->type != TW($bmux))
 					continue;
 
 				SigSpec sig_a = cell->getPort(TW::A);
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 70f5ce65f..bde9ec61f 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -44,7 +44,7 @@ struct rules_t
 
 		void dump_config() const
 		{
-			log("      bram %s # variant %d\n", name.unescape(), variant);
+			log("      bram %s # variant %d\n", design->twines.unescaped_str(name), variant);
 			log("        init %d\n", init);
 			log("        abits %d\n", abits);
 			log("        dbits %d\n", dbits);
@@ -61,16 +61,16 @@ struct rules_t
 
 		void check_vectors() const
 		{
-			if (groups != GetSize(ports))  log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n",  name.unescape(), variant, groups, GetSize(ports));
-			if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", name.unescape(), variant, groups, GetSize(wrmode));
-			if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", name.unescape(), variant, groups, GetSize(enable));
-			if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", name.unescape(), variant, groups, GetSize(transp));
-			if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", name.unescape(), variant, groups, GetSize(clocks));
-			if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", name.unescape(), variant, groups, GetSize(clkpol));
+			if (groups != GetSize(ports))  log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n",  design->twines.unescaped_str(name), variant, groups, GetSize(ports));
+			if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(wrmode));
+			if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(enable));
+			if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(transp));
+			if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(clocks));
+			if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", design->twines.unescaped_str(name), variant, groups, GetSize(clkpol));
 
 			int group = 0;
 			for (auto e : enable)
-				if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", name.unescape(), variant, group, e, dbits);
+				if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", design->twines.unescaped_str(name), variant, group, e, dbits);
 		}
 
 		vector<portinfo_t> make_portinfos() const
@@ -100,7 +100,7 @@ struct rules_t
 			log_assert(name == other.name);
 
 			if (groups != other.groups)
-				log_error("Bram %s variants %d and %d have different values for 'groups'.\n", name.unescape(), variant, other.variant);
+				log_error("Bram %s variants %d and %d have different values for 'groups'.\n", design->twines.unescaped_str(name), variant, other.variant);
 
 			if (abits != other.abits)
 				variant_params[ID::CFG_ABITS] = abits;
@@ -112,7 +112,7 @@ struct rules_t
 			for (int i = 0; i < groups; i++)
 			{
 				if (ports[i] != other.ports[i])
-					log_error("Bram %s variants %d and %d have different number of %c-ports.\n", name.unescape(), variant, other.variant, 'A'+i);
+					log_error("Bram %s variants %d and %d have different number of %c-ports.\n", design->twines.unescaped_str(name), variant, other.variant, 'A'+i);
 				if (wrmode[i] != other.wrmode[i])
 					variant_params[stringf("\\CFG_WRMODE_%c", 'A' + i)] = wrmode[i];
 				if (enable[i] != other.enable[i])
@@ -490,7 +490,7 @@ bool replace_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals, const
 		transp_max = max(transp_max, pi.transp);
 	}
 
-	log("    Mapping to bram type %s (variant %d):\n", bram.name.unescape(), bram.variant);
+	log("    Mapping to bram type %s (variant %d):\n", design->twines.unescaped_str(bram.name), bram.variant);
 	// bram.dump_config();
 
 	std::vector<int> shuffle_map;
@@ -777,7 +777,7 @@ grow_read_ports:;
 		for (auto it : match.min_limits) {
 			if (!match_properties.count(it.first))
 				log_error("Unknown property '%s' in match rule for bram type %s.\n",
-						it.first.c_str(), match.name.unescape());
+						it.first.c_str(), design->twines.unescaped_str(match.name));
 			if (match_properties[it.first] >= it.second)
 				continue;
 			log("    Rule for bram type %s rejected: requirement 'min %s %d' not met.\n",
@@ -787,7 +787,7 @@ grow_read_ports:;
 		for (auto it : match.max_limits) {
 			if (!match_properties.count(it.first))
 				log_error("Unknown property '%s' in match rule for bram type %s.\n",
-						it.first.c_str(), match.name.unescape());
+						it.first.c_str(), design->twines.unescaped_str(match.name));
 			if (match_properties[it.first] <= it.second)
 				continue;
 			log("    Rule for bram type %s rejected: requirement 'max %s %d' not met.\n",
@@ -821,7 +821,7 @@ grow_read_ports:;
 				if (!exists)
 					ss << "!";
 				IdString key = std::get<1>(sums.front());
-				ss << key.unescape();
+				ss << design->twines.unescaped_str(key);
 				const Const &value = rules.map_case(std::get<2>(sums.front()));
 				if (exists && value != Const(1))
 					ss << "=\"" << value.decode_string() << "\"";
@@ -936,7 +936,7 @@ grow_read_ports:;
 		for (int dupidx = 0; dupidx < dup_count; dupidx++)
 		{
 			Cell *c = module->addCell(module->uniquify(module->design->twines.add(Twine{stringf("%s.%d.%d.%d", mem.memid.str(), grid_d, grid_a, dupidx)})), bram.name);
-			log("      Creating %s cell at grid position <%d %d %d>: %s\n", bram.name.unescape(), grid_d, grid_a, dupidx, c);
+			log("      Creating %s cell at grid position <%d %d %d>: %s\n", design->twines.unescaped_str(bram.name), grid_d, grid_a, dupidx, c);
 
 			for (auto &vp : variant_params)
 				c->setParam(vp.first, vp.second);
@@ -1066,7 +1066,7 @@ grow_read_ports:;
 
 void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 {
-	log("Processing %s.%s:\n", mem.module, mem.memid.unescape());
+	log("Processing %s.%s:\n", mem.module, design->twines.unescaped_str(mem.memid));
 	mem.narrow();
 
 	bool cell_init = !mem.inits.empty();
@@ -1093,7 +1093,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 		auto &match = rules.matches.at(i);
 
 		if (!rules.brams.count(rules.matches[i].name))
-			log_error("No bram description for resource %s found!\n", rules.matches[i].name.unescape());
+			log_error("No bram description for resource %s found!\n", design->twines.unescaped_str(rules.matches[i].name));
 
 		for (int vi = 0; vi < GetSize(rules.brams.at(match.name)); vi++)
 		{
@@ -1109,7 +1109,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 					avail_wr_ports += GetSize(bram.ports) < j ? bram.ports.at(j) : 0;
 			}
 
-			log("  Checking rule #%d for bram type %s (variant %d):\n", i+1, bram.name.unescape(), bram.variant);
+			log("  Checking rule #%d for bram type %s (variant %d):\n", i+1, design->twines.unescaped_str(bram.name), bram.variant);
 			log("    Bram geometry: abits=%d dbits=%d wports=%d rports=%d\n", bram.abits, bram.dbits, avail_wr_ports, avail_rd_ports);
 
 			int dups = avail_rd_ports ? (match_properties["rports"] + avail_rd_ports - 1) / avail_rd_ports : 1;
@@ -1143,7 +1143,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 
 			if (cell_init && bram.init == 0) {
 				log("    Rule #%d for bram type %s (variant %d) rejected: cannot be initialized.\n",
-						i+1, bram.name.unescape(), bram.variant);
+						i+1, design->twines.unescaped_str(bram.name), bram.variant);
 				goto next_match_rule;
 			}
 
@@ -1152,11 +1152,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 					continue;
 				if (!match_properties.count(it.first))
 					log_error("Unknown property '%s' in match rule for bram type %s.\n",
-							it.first.c_str(), match.name.unescape());
+							it.first.c_str(), design->twines.unescaped_str(match.name));
 				if (match_properties[it.first] >= it.second)
 					continue;
 				log("    Rule #%d for bram type %s (variant %d) rejected: requirement 'min %s %d' not met.\n",
-						i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
+						i+1, design->twines.unescaped_str(bram.name), bram.variant, it.first.c_str(), it.second);
 				goto next_match_rule;
 			}
 
@@ -1165,11 +1165,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 					continue;
 				if (!match_properties.count(it.first))
 					log_error("Unknown property '%s' in match rule for bram type %s.\n",
-							it.first.c_str(), match.name.unescape());
+							it.first.c_str(), design->twines.unescaped_str(match.name));
 				if (match_properties[it.first] <= it.second)
 					continue;
 				log("    Rule #%d for bram type %s (variant %d) rejected: requirement 'max %s %d' not met.\n",
-						i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
+						i+1, design->twines.unescaped_str(bram.name), bram.variant, it.first.c_str(), it.second);
 				goto next_match_rule;
 			}
 
@@ -1199,7 +1199,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 					if (!exists)
 						ss << "!";
 					IdString key = std::get<1>(sums.front());
-					ss << key.unescape();
+					ss << design->twines.unescaped_str(key);
 					const Const &value = rules.map_case(std::get<2>(sums.front()));
 					if (exists && value != Const(1))
 						ss << "=\"" << value.decode_string() << "\"";
@@ -1210,7 +1210,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 				}
 			}
 
-			log("    Rule #%d for bram type %s (variant %d) accepted.\n", i+1, bram.name.unescape(), bram.variant);
+			log("    Rule #%d for bram type %s (variant %d) accepted.\n", i+1, design->twines.unescaped_str(bram.name), bram.variant);
 
 			if (or_next_if_better || !best_rule_cache.empty())
 			{
@@ -1218,7 +1218,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 					log_error("Found 'or_next_if_better' in last match rule.\n");
 
 				if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 1)) {
-					log("    Mapping to bram type %s failed.\n", match.name.unescape());
+					log("    Mapping to bram type %s failed.\n", design->twines.unescaped_str(match.name));
 					failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
 					goto next_match_rule;
 				}
@@ -1245,12 +1245,12 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 
 				auto &best_bram = rules.brams.at(rules.matches.at(best_rule.first).name).at(best_rule.second);
 				if (!replace_memory(mem, rules, initvals, best_bram, rules.matches.at(best_rule.first), match_properties, 2))
-					log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", best_bram.name.unescape(), best_bram.variant);
+					log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", design->twines.unescaped_str(best_bram.name), best_bram.variant);
 				return;
 			}
 
 			if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 0)) {
-				log("    Mapping to bram type %s failed.\n", match.name.unescape());
+				log("    Mapping to bram type %s failed.\n", design->twines.unescaped_str(match.name));
 				failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
 				goto next_match_rule;
 			}
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index e7513a67f..3588752cf 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -174,7 +174,7 @@ struct MemQueryCache
 		if (GetSize(drivers) != 1)
 			return false;
 		auto driver = *drivers.begin();
-		if (!driver.cell->type.in(ID($mux), ID($pmux)))
+		if (!driver.cell->type.in(TW($mux), TW($pmux)))
 			return false;
 		log_assert(driver.port == TW::Y);
 		SigSpec sig_s = driver.cell->getPort(TW::S);
@@ -247,7 +247,7 @@ struct MemoryDffWorker
 					continue;
 				auto consumer = *consumers.begin();
 				bool is_b;
-				if (consumer.cell->type == ID($mux)) {
+				if (consumer.cell->type == TW($mux)) {
 					if (consumer.port == TW::A) {
 						is_b = false;
 					} else if (consumer.port == TW::B) {
@@ -255,7 +255,7 @@ struct MemoryDffWorker
 					} else {
 						continue;
 					}
-				} else if (consumer.cell->type == ID($pmux)) {
+				} else if (consumer.cell->type == TW($pmux)) {
 					if (consumer.port == TW::A) {
 						is_b = false;
 					} else {
diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc
index d17db2769..61b499681 100644
--- a/passes/memory/memory_libmap.cc
+++ b/passes/memory/memory_libmap.cc
@@ -140,7 +140,7 @@ struct MapWorker {
 	MapWorker(Module *module) : module(module), modwalker(module->design, module), sigmap(module), sigmap_xmux(module), initvals(&sigmap, module) {
 		for (auto cell : module->cells())
 		{
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 			{
 				RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
 				RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
@@ -204,7 +204,7 @@ struct MemMapping {
 			if (!check_init(rdef))
 				continue;
 			if (rdef.prune_rom && mem.wr_ports.empty()) {
-				log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module), mem.memid.unescape(), rdef.id.unescape());
+				log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module), design->twines.unescaped_str(mem.memid), mem.module->design->twines.unescaped_str(rdef.id));
 				continue;
 			}
 			MemConfig cfg;
@@ -323,7 +323,7 @@ struct MemMapping {
 
 	void log_reject(const Ram &ram, std::string message) {
 		if(ys_debug(1)) {
-			rejected_cfg_debug_msgs += stringf("can't map to to %s: ", ram.id.unescape());
+			rejected_cfg_debug_msgs += stringf("can't map to to %s: ", mem.module->design->twines.unescaped_str(ram.id));
 			rejected_cfg_debug_msgs += message;
 			rejected_cfg_debug_msgs += "\n";
 		}
@@ -338,7 +338,7 @@ struct MemMapping {
 				rejected_cfg_debug_msgs += portname;
 				first = false;
 			}
-			rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
+			rejected_cfg_debug_msgs += stringf("] of %s: ", mem.module->design->twines.unescaped_str(ram.id));
 			rejected_cfg_debug_msgs += message;
 			rejected_cfg_debug_msgs += "\n";
 		}
@@ -361,7 +361,7 @@ struct MemMapping {
 				rejected_cfg_debug_msgs += portname;
 				first = false;
 			}
-			rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
+			rejected_cfg_debug_msgs += stringf("] of %s: ", mem.module->design->twines.unescaped_str(ram.id));
 			rejected_cfg_debug_msgs += message;
 			rejected_cfg_debug_msgs += "\n";
 		}
@@ -380,7 +380,7 @@ void MemMapping::dump_configs(int stage) {
 		default:
 			abort();
 	}
-	log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module), mem.memid.unescape(), stage_name);
+	log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module), design->twines.unescaped_str(mem.memid), stage_name);
 	if (logic_ok) {
 		log_debug("- logic fallback\n");
 		log_debug("  - cost: %f\n", logic_cost);
@@ -391,7 +391,7 @@ void MemMapping::dump_configs(int stage) {
 }
 
 void MemMapping::dump_config(MemConfig &cfg) {
-	log_debug("- %s:\n", cfg.def->id.unescape());
+	log_debug("- %s:\n", mem.module->design->twines.unescaped_str(cfg.def->id));
 	for (auto &it: cfg.def->options)
 		log_debug("  - option %s %s\n", it.first, log_const(it.second));
 	log_debug("  - emulation score: %d\n", cfg.score_emu);
@@ -527,7 +527,7 @@ void MemMapping::determine_style() {
 	auto find_attr = search_for_attribute(mem, ID::lram);
 	if (find_attr.first && find_attr.second.as_bool()) {
 		kind = RamKind::Huge;
-		log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module), mem.memid.unescape());
+		log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module), design->twines.unescaped_str(mem.memid));
 		return;
 	}
 	for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) {
@@ -536,7 +536,7 @@ void MemMapping::determine_style() {
 			Const val = find_attr.second;
 			if (val == 1) {
 				kind = RamKind::NotLogic;
-				log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", attr.unescape(), log_id(mem.module), mem.memid.unescape());
+				log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", design->twines.unescaped_str(attr), log_id(mem.module), design->twines.unescaped_str(mem.memid));
 				return;
 			}
 			std::string val_s = val.decode_string();
@@ -549,20 +549,20 @@ void MemMapping::determine_style() {
 				// Nothing.
 			} else if (val_s == "logic" || val_s == "registers") {
 				kind = RamKind::Logic;
-				log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
+				log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
 			} else if (val_s == "distributed") {
 				kind = RamKind::Distributed;
-				log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
+				log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
 			} else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") {
 				kind = RamKind::Block;
-				log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
+				log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
 			} else if (val_s == "huge" || val_s == "ultra") {
 				kind = RamKind::Huge;
-				log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape());
+				log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid));
 			} else {
 				kind = RamKind::NotLogic;
 				style = val_s;
-				log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape(), val_s);
+				log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", design->twines.unescaped_str(attr), val_s, log_id(mem.module), design->twines.unescaped_str(mem.memid), val_s);
 			}
 			return;
 		}
@@ -1991,7 +1991,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
 }
 
 void MemMapping::emit(const MemConfig &cfg) {
-	log("mapping memory %s.%s via %s\n", log_id(mem.module), mem.memid.unescape(), cfg.def->id.unescape());
+	log("mapping memory %s.%s via %s\n", log_id(mem.module), design->twines.unescaped_str(mem.memid), mem.module->design->twines.unescaped_str(cfg.def->id));
 	// First, handle emulations.
 	if (cfg.emu_read_first)
 		mem.emulate_read_first(&worker.initvals);
@@ -2068,7 +2068,7 @@ void MemMapping::emit(const MemConfig &cfg) {
 	for (int rp = 0; rp < cfg.repl_port; rp++) {
 		std::vector<Cell *> cells;
 		for (int rd = 0; rd < cfg.repl_d; rd++) {
-			Cell *cell = mem.module->addCell(mem.module->design->twines.add(Twine{stringf("%s.%d.%d", mem.memid.str(), rp, rd)}), cfg.def->id);
+			Cell *cell = mem.module->addCell(Twine{stringf("%s.%d.%d", mem.memid.str(), rp, rd)}, cfg.def->id);
 			if (cfg.def->width_mode == WidthMode::Global || opts.force_params)
 				cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]);
 			if (opts.force_params)
@@ -2252,9 +2252,9 @@ struct MemoryLibMapPass : public Pass {
 				int best = map.logic_cost;
 				if (!map.logic_ok) {
 					if (map.cfgs.empty()) {
-						log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module), mem.memid.unescape());
+						log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module), design->twines.unescaped_str(mem.memid));
 						log_debug("%s", map.rejected_cfg_debug_msgs);
-						log_error("no valid mapping found for memory %s.%s\n", log_id(module), mem.memid.unescape());
+						log_error("no valid mapping found for memory %s.%s\n", log_id(module), design->twines.unescaped_str(mem.memid));
 					}
 					idx = 0;
 					best = map.cfgs[0].cost;
@@ -2266,7 +2266,7 @@ struct MemoryLibMapPass : public Pass {
 					}
 				}
 				if (idx == -1) {
-					log("using FF mapping for memory %s.%s\n", log_id(module), mem.memid.unescape());
+					log("using FF mapping for memory %s.%s\n", log_id(module), design->twines.unescaped_str(mem.memid));
 				} else {
 					map.emit(map.cfgs[idx]);
 					// Rebuild indices after modifying module
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 25bdb3f53..076099a04 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -238,17 +238,17 @@ struct MemoryMapWorker
 				if (static_only) {
 					// non-static part is a ROM, we only reach this with keepdc
 					if (formal) {
-						c = module->addCell(design->twines.add(Twine{ff_id}), ID($ff));
+						c = module->addCell(Twine{ff_id}, TW($ff));
 					} else {
-						c = module->addCell(design->twines.add(Twine{ff_id}), ID($dff));
+						c = module->addCell(Twine{ff_id}, TW($dff));
 						c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
 						c->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::S0));
 					}
 				} else if (async_wr) {
 					log_assert(formal); // General async write not implemented yet, checked against above
-					c = module->addCell(design->twines.add(Twine{ff_id}), ID($ff));
+					c = module->addCell(Twine{ff_id}, TW($ff));
 				} else {
-					c = module->addCell(design->twines.add(Twine{ff_id}), ID($dff));
+					c = module->addCell(Twine{ff_id}, TW($dff));
 					c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
 					c->setPort(TW::CLK, refclock);
 				}
@@ -306,15 +306,15 @@ struct MemoryMapWorker
 
 				for (size_t k = 0; k < rd_signals.size(); k++)
 				{
-					RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k)}), ID($mux));
+					RTLIL::Cell *c = module->addCell(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k)}, TW($mux));
 					c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src}));
 					c->parameters[ID::WIDTH] = GetSize(port.data);
 					c->setPort(TW::Y, rd_signals[k]);
 					c->setPort(TW::S, rd_addr.extract(abits-j-1, 1));
 					count_mux++;
 
-					c->setPort(TW::A, module->addWire(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$a")}), GetSize(port.data)));
-					c->setPort(TW::B, module->addWire(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$b")}), GetSize(port.data)));
+					c->setPort(TW::A, module->addWire(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$a")}, GetSize(port.data)));
+					c->setPort(TW::B, module->addWire(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$b")}, GetSize(port.data)));
 
 					next_rd_signals.push_back(c->getPort(TW::A));
 					next_rd_signals.push_back(c->getPort(TW::B));
@@ -366,7 +366,7 @@ struct MemoryMapWorker
 
 						if (wr_bit != State::S1)
 						{
-							RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wren", addr, "", j, "", wr_offset)}), ID($and));
+							RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wren", addr, "", j, "", wr_offset)}), TW($and));
 							c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src}));
 							c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
 							c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
@@ -380,7 +380,7 @@ struct MemoryMapWorker
 							c->setPort(TW::Y, RTLIL::SigSpec(w));
 						}
 
-						RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset)}), ID($mux));
+						RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset)}), TW($mux));
 						c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src}));
 						c->parameters[ID::WIDTH] = wr_width;
 						c->setPort(TW::A, sig.extract(wr_offset, wr_width));
diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc
index 680e2e6bf..2093ace64 100644
--- a/passes/memory/memory_memx.cc
+++ b/passes/memory/memory_memx.cc
@@ -60,7 +60,7 @@ struct MemoryMemxPass : public Pass {
 			{
 				if (port.clk_enable)
 					log_error("Memory %s.%s has a synchronous read port.  Synchronous read ports are not supported by memory_memx!\n",
-							module, mem.memid.unescape());
+							module, design->twines.unescaped_str(mem.memid));
 
 				SigSpec addr_ok = make_addr_check(mem, port.addr);
 				Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data));
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 5fb187095..b4deeef35 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -80,7 +80,7 @@ struct MemoryShareWorker
 		if (GetSize(mem.rd_ports) <= 1)
 			return false;
 
-		log("Consolidating read ports of memory %s.%s by address:\n", module, mem.memid.unescape());
+		log("Consolidating read ports of memory %s.%s by address:\n", module, design->twines.unescaped_str(mem.memid));
 
 		bool changed = false;
 		int abits = 0;
@@ -197,7 +197,7 @@ struct MemoryShareWorker
 		if (GetSize(mem.wr_ports) <= 1)
 			return false;
 
-		log("Consolidating write ports of memory %s.%s by address:\n", module, mem.memid.unescape());
+		log("Consolidating write ports of memory %s.%s by address:\n", module, design->twines.unescaped_str(mem.memid));
 
 		bool changed = false;
 		int abits = 0;
@@ -316,7 +316,7 @@ struct MemoryShareWorker
 		if (eligible_ports.size() <= 1)
 			return;
 
-		log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, mem.memid.unescape());
+		log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, design->twines.unescaped_str(mem.memid));
 
 		// Group eligible ports by clock domain and width.
 
@@ -482,7 +482,7 @@ struct MemoryShareWorker
 		sigmap_xmux = sigmap;
 		for (auto cell : module->cells())
 		{
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 			{
 				RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
 				RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 1b006842f..de5c3063d 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -37,7 +37,7 @@ struct ExclusiveDatabase
 		SigBit y_port;
 		pool<Cell*> reduce_or;
 		for (auto cell : module->cells()) {
-			if (cell->type == ID($eq)) {
+			if (cell->type == TW($eq)) {
 				SigSpec y_sig = sigmap(cell->getPort(TW::Y));
 				if (GetSize(y_sig) == 0)
 					continue;
@@ -50,7 +50,7 @@ struct ExclusiveDatabase
 				}
 				y_port = y_sig[0];
 			}
-			else if (cell->type == ID($logic_not)) {
+			else if (cell->type == TW($logic_not)) {
 				SigSpec y_sig = sigmap(cell->getPort(TW::Y));
 				if (GetSize(y_sig) == 0)
 					continue;
@@ -58,7 +58,7 @@ struct ExclusiveDatabase
 				const_sig = Const(State::S0, GetSize(nonconst_sig));
 				y_port = y_sig[0];
 			}
-			else if (cell->type == ID($reduce_or)) {
+			else if (cell->type == TW($reduce_or)) {
 				reduce_or.insert(cell);
 				continue;
 			}
@@ -152,11 +152,11 @@ struct MuxpackWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
+			if (cell->type.in(TW($mux), TW($pmux)) && !cell->get_bool_attribute(ID::keep))
 			{
 				SigSpec a_sig = sigmap(cell->getPort(TW::A));
 				SigSpec b_sig;
-				if (cell->type == ID($mux))
+				if (cell->type == TW($mux))
 					b_sig = sigmap(cell->getPort(TW::B));
 				SigSpec y_sig = sigmap(cell->getPort(TW::Y));
    
@@ -193,10 +193,10 @@ struct MuxpackWorker
 	{
 		for (auto cell : candidate_cells)
 		{
-			log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
+			log_debug("Considering %s (%s)\n", cell, cell->type.unescaped());
 
 			SigSpec a_sig = sigmap(cell->getPort(TW::A));
-			if (cell->type == ID($mux)) {
+			if (cell->type == TW($mux)) {
 				SigSpec b_sig = sigmap(cell->getPort(TW::B));
 				if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
 					goto start_cell;
@@ -204,7 +204,7 @@ struct MuxpackWorker
 				if (!sig_chain_prev.count(a_sig))
 					a_sig = b_sig;
 			}
-			else if (cell->type == ID($pmux)) {
+			else if (cell->type == TW($pmux)) {
 				if (!sig_chain_prev.count(a_sig))
 					goto start_cell;
 			}
@@ -289,7 +289,7 @@ struct MuxpackWorker
 					s_sig.append(cursor_cell->getPort(TW::S));
 				}
 				else {
-					log_assert(cursor_cell->type == ID($mux));
+					log_assert(cursor_cell->type == TW($mux));
 					b_sig.append(cursor_cell->getPort(TW::A));
 					s_sig.append(module->LogicNot(NEW_TWINE, cursor_cell->getPort(TW::S)));
 				}
diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc
index f839606fb..2de24deef 100644
--- a/passes/opt/opt_balance_tree.cc
+++ b/passes/opt/opt_balance_tree.cc
@@ -48,10 +48,10 @@ struct OptBalanceTreeWorker {
 
 		// Calculate the "natural" output width for this operation
 		int natural_width;
-		if (cell_type == ID($add)) {
+		if (cell_type == TW($add)) {
 			// Addition produces max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
 			natural_width = std::max(a_width, b_width) + 1;
-		} else if (cell_type == ID($mul)) {
+		} else if (cell_type == TW($mul)) {
 			// Multiplication produces A_WIDTH + B_WIDTH
 			natural_width = a_width + b_width;
 		} else {
@@ -84,9 +84,9 @@ struct OptBalanceTreeWorker {
 			
 			// Create output wire
 			int out_width = cell->getParam(ID::Y_WIDTH).as_int();
-			if (cell_type == ID($add))
+			if (cell_type == TW($add))
 				out_width = max(sources[0].size(), sources[1].size()) + 1;
-			else if (cell_type == ID($mul))
+			else if (cell_type == TW($mul))
 				out_width = sources[0].size() + sources[1].size();
 			Wire* out_wire = module->addWire(NEW_TWINE, out_width);
 			
@@ -119,9 +119,9 @@ struct OptBalanceTreeWorker {
 		
 		// Create output wire
 		int out_width = cell->getParam(ID::Y_WIDTH).as_int();
-		if (cell_type == ID($add))
+		if (cell_type == TW($add))
 			out_width = max(left_tree.size(), right_tree.size()) + 1;
-		else if (cell_type == ID($mul))
+		else if (cell_type == TW($mul))
 			out_width = left_tree.size() + right_tree.size();
 		Wire* out_wire = module->addWire(NEW_TWINE, out_width);
 		
@@ -344,14 +344,14 @@ struct OptBalanceTreePass : public Pass {
 
 		// Handle arguments
 		size_t argidx;
-		vector<IdString> cell_types = {ID($and), ID($or), ID($xor), ID($add), ID($mul)};
+		vector<IdString> cell_types = {TW($and), TW($or), TW($xor), TW($add), TW($mul)};
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			if (args[argidx] == "-arith") {
-				cell_types = {ID($add), ID($mul)};
+				cell_types = {TW($add), TW($mul)};
 				continue;
 			}
 			if (args[argidx] == "-logic") {
-				cell_types = {ID($and), ID($or), ID($xor)};
+				cell_types = {TW($and), TW($or), TW($xor)};
 				continue;
 			}
 			break;
@@ -369,7 +369,7 @@ struct OptBalanceTreePass : public Pass {
 
 		// Log stats
 		for (auto cell_type : cell_types)
-			log("Converted %d %s cells into trees.\n", cell_count[cell_type], cell_type.unescape());
+			log("Converted %d %s cells into trees.\n", cell_count[cell_type], design->twines.unescaped_str(cell_type));
 
 		// Clean up
 		Yosys::run_pass("clean -purge");
diff --git a/passes/opt/opt_clean/cells_all.cc b/passes/opt/opt_clean/cells_all.cc
index c1125f5ca..ed8e6edc2 100644
--- a/passes/opt/opt_clean/cells_all.cc
+++ b/passes/opt/opt_clean/cells_all.cc
@@ -120,7 +120,7 @@ struct ConflictLogs {
 			// We could do this in parallel but hopefully this is rare.
 			for (auto [_, cell] : mod->cells_) {
 				for (auto &[port, sig] : cell->connections()) {
-					if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_input(cell->type, port))
+					if (clean_ctx.ct_all.cell_known(cell->type_impl) && !clean_ctx.ct_all.cell_input(cell->type_impl, port))
 						continue;
 					for (auto raw_bit : wire_map(sig))
 						used_raw_bits.insert(raw_bit);
@@ -189,17 +189,17 @@ ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const Sig
 	actx.subpool.run([&analysis, &traversal, &logs, &wire_map, &mem2cells_vector, &wire2driver_builder, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
 		for (int i : ctx.item_range(actx.mod->cells_size())) {
 			Cell *cell = actx.mod->cell_at(i);
-			if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
+			if (cell->type.in(TW($memwr), TW($memwr_v2), TW($meminit), TW($meminit_v2)))
 				mem2cells_vector.insert(ctx, {cell->getParam(ID::MEMID).decode_string(), i});
 
 			for (auto &it2 : cell->connections()) {
-				if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_output(cell->type, it2.first))
+				if (clean_ctx.ct_all.cell_known(cell->type_impl) && !clean_ctx.ct_all.cell_output(cell->type_impl, it2.first))
 					continue;
 				for (auto raw_bit : it2.second) {
 					if (raw_bit.wire == nullptr)
 						continue;
 					auto bit = actx.assign_map(raw_bit);
-					if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
+					if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type_impl)) {
 						auto twines = cell->module->design->twines;
 						std::string msg = stringf("Driver-driver conflict "
 							"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
@@ -257,11 +257,11 @@ void fixup_unused_cells_and_mems(CellAnalysis& analysis, MemAnalysis& mem_analys
 			for (auto cell_index : cell_indices) {
 				Cell *cell = actx.mod->cell_at(cell_index);
 				for (auto &it : cell->connections())
-					if (!clean_ctx.ct_all.cell_known(cell->type) || clean_ctx.ct_all.cell_input(cell->type, it.first))
+					if (!clean_ctx.ct_all.cell_known(cell->type_impl) || clean_ctx.ct_all.cell_input(cell->type_impl, it.first))
 						for (auto bit : actx.assign_map(it.second))
 							bits.insert(bit);
 
-				if (cell->type.in(ID($memrd), ID($memrd_v2))) {
+				if (cell->type.in(TW($memrd), TW($memrd_v2))) {
 					std::string mem_id = cell->getParam(ID::MEMID).decode_string();
 					if (mem_analysis.indices.count(mem_id)) {
 						int mem_index = mem_analysis.indices[mem_id];
diff --git a/passes/opt/opt_clean/cells_temp.cc b/passes/opt/opt_clean/cells_temp.cc
index 56611de61..919aabc13 100644
--- a/passes/opt/opt_clean/cells_temp.cc
+++ b/passes/opt/opt_clean/cells_temp.cc
@@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 bool is_signed(RTLIL::Cell* cell) {
-	return cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
+	return cell->type == TW($pos) && cell->getParam(ID::A_SIGNED).as_bool();
 }
 
 bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
@@ -56,16 +56,16 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
 	bool did_something = false;
 	for (RTLIL::Cell *cell : cells) {
 		if (verbose) {
-			if (cell->type == ID($connect)) {
+			if (cell->type == TW($connect)) {
 				log_debug("  removing connect cell `%s': %s <-> %s\n", cell->name,
 						log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B)));
-			} else if (cell->type == ID($input_port)) {
+			} else if (cell->type == TW($input_port)) {
 				log_debug("  removing input port marker cell `%s': %s\n", cell->name,
 						log_signal(cell->getPort(TW::Y)));
-			} else if (cell->type == ID($output_port)) {
+			} else if (cell->type == TW($output_port)) {
 				log_debug("  removing output port marker cell `%s': %s\n", cell->name,
 						log_signal(cell->getPort(TW::A)));
-			} else if (cell->type == ID($public)) {
+			} else if (cell->type == TW($public)) {
 				log_debug("  removing public wire marker cell `%s': %s\n", cell->name,
 						log_signal(cell->getPort(TW::A)));
 			} else {
@@ -89,17 +89,17 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
 	subpool.run([const_module, &delcells, &new_connections](const ParallelDispatchThreadPool::RunCtx &ctx) {
 		for (int i : ctx.item_range(const_module->cells_size())) {
 			RTLIL::Cell *cell = const_module->cell_at(i);
-			if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
+			if (cell->type.in(TW($pos), TW($_BUF_), TW($buf)) && !cell->has_keep_attr()) {
 				if (trim_buf(cell, new_connections, ctx))
 					delcells.insert(ctx, cell);
-			} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
+			} else if (cell->type.in(TW($connect)) && !cell->has_keep_attr()) {
 				RTLIL::SigSpec a = cell->getPort(TW::A);
 				RTLIL::SigSpec b = cell->getPort(TW::B);
 				if (a.has_const() && !b.has_const())
 					std::swap(a, b);
 				new_connections.insert(ctx, {a, b});
 				delcells.insert(ctx, cell);
-			} else if (cell->type.in(ID($input_port), ID($output_port), ID($public)) && !cell->has_keep_attr()) {
+			} else if (cell->type.in(TW($input_port), TW($output_port), TW($public)) && !cell->has_keep_attr()) {
 				delcells.insert(ctx, cell);
 			}
 		}
diff --git a/passes/opt/opt_clean/inits.cc b/passes/opt/opt_clean/inits.cc
index 4e94f1957..3d8af9387 100644
--- a/passes/opt/opt_clean/inits.cc
+++ b/passes/opt/opt_clean/inits.cc
@@ -27,7 +27,7 @@ ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
 	actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
 		for (int i : ctx.item_range(actx.mod->cells_size())) {
 			RTLIL::Cell *cell = actx.mod->cell_at(i);
-			if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(TW::Q))
+			if (StaticCellTypes::Compat::internals_mem_ff(cell->type_impl) && cell->hasPort(TW::Q))
 			{
 				SigSpec sig = cell->getPort(TW::Q);
 
diff --git a/passes/opt/opt_clean/keep_cache.h b/passes/opt/opt_clean/keep_cache.h
index 7405f24fc..01cf404c2 100644
--- a/passes/opt/opt_clean/keep_cache.h
+++ b/passes/opt/opt_clean/keep_cache.h
@@ -75,7 +75,7 @@ struct KeepCache
 	{
 		if (keep_cell(cell, purge_mode))
 			return true;
-		if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
+		if (cell->type.in(TW($specify2), TW($specify3), TW($specrule)))
 			return true;
 		if (cell->module && cell->module->design) {
 			RTLIL::Module *cell_module = cell->module->design->module(cell->type);
@@ -145,19 +145,19 @@ private:
 
 	static bool keep_cell(Cell *cell, bool purge_mode)
 	{
-		if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+		if (cell->type.in(TW($assert), TW($assume), TW($live), TW($fair), TW($cover)))
 			return true;
 
-		if (cell->type.in(ID($overwrite_tag)))
+		if (cell->type.in(TW($overwrite_tag)))
 			return true;
 
-		if (cell->type == ID($print) || cell->type == ID($check))
+		if (cell->type == TW($print) || cell->type == TW($check))
 			return true;
 
 		if (cell->has_keep_attr())
 			return true;
 
-		if (!purge_mode && cell->type == ID($scopeinfo))
+		if (!purge_mode && cell->type == TW($scopeinfo))
 			return true;
 		return false;
 	}
diff --git a/passes/opt/opt_clean/wires.cc b/passes/opt/opt_clean/wires.cc
index 944552f81..a682ed7cf 100644
--- a/passes/opt/opt_clean/wires.cc
+++ b/passes/opt/opt_clean/wires.cc
@@ -251,20 +251,20 @@ struct SigConnKinds {
 			for (int i : ctx.item_range(actx.mod->cells_size())) {
 				RTLIL::Cell *cell = actx.mod->cell_at(i);
 				if (!purge_mode) {
-					if (clean_ctx.ct_reg(cell->type)) {
+					if (clean_ctx.ct_reg(cell->type_impl)) {
 						// Improve witness signal naming when clk2fflogic used
 						// see commit message e36c71b5
 						bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic);
 						for (auto &[port, sig] : cell->connections())
-							if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type, port))
+							if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type_impl, port))
 								add_spec(raw_register_builder, ctx, sig);
 					}
 					for (auto &[_, sig] : cell->connections())
 						add_spec(raw_cell_connected_builder, ctx, sig);
 				}
-				if (clean_ctx.ct_all.cell_known(cell->type))
+				if (clean_ctx.ct_all.cell_known(cell->type_impl))
 					for (auto &[port, sig] : cell->connections())
-						if (clean_ctx.ct_all.cell_output(cell->type, port)) {
+						if (clean_ctx.ct_all.cell_output(cell->type_impl, port)) {
 							RTLIL::SigSpec spec = actx.assign_map(sig);
 							unsigned int hash = spec.hash_into(Hasher()).yield();
 							exact_cell_output_builder.insert(ctx, {std::move(spec), hash});
@@ -367,7 +367,7 @@ DeferredUpdates analyse_connectivity(UsedSignals& used, SigConnKinds& sig_analys
 					deferred.update_connections.insert(ctx, {cell, port, spec});
 				add_spec(raw_conn_builder, ctx, spec);
 				add_spec(conn_builder, ctx, spec);
-				if (!clean_ctx.ct_all.cell_output(cell->type, port))
+				if (!clean_ctx.ct_all.cell_output(cell->type_impl, port))
 					add_spec(used_builder, ctx, spec);
 			}
 		}
diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc
index a4b3060f8..7d0734ca7 100644
--- a/passes/opt/opt_demorgan.cc
+++ b/passes/opt/opt_demorgan.cc
@@ -35,7 +35,7 @@ void demorgan_worker(
 	//TODO: Add support for reduce_xor
 	//DeMorgan of XOR is either XOR (if even number of inputs) or XNOR (if odd number)
 
-	if( (cell->type != ID($reduce_and)) && (cell->type != ID($reduce_or)) )
+	if( (cell->type != TW($reduce_and)) && (cell->type != TW($reduce_or)) )
 		return;
 
 	auto insig = sigmap(cell->getPort(TW::A));
@@ -43,7 +43,7 @@ void demorgan_worker(
 	if (GetSize(insig) < 1)
 		return;
 
-	log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescape(), cell->module->design->twines.str(cell->meta_->name), GetSize(insig));
+	log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescaped(), cell->module->design->twines.str(cell->meta_->name), GetSize(insig));
 	int num_inverted = 0;
 	for(int i=0; i<GetSize(insig); i++)
 	{
@@ -55,7 +55,7 @@ void demorgan_worker(
 		bool inverted = false;
 		for(auto x : ports)
 		{
-			if(x.port == TW::Y && x.cell->type == ID($_NOT_))
+			if(x.port == TW::Y && x.cell->type == TW($_NOT_))
 			{
 				inverted = true;
 				break;
@@ -89,7 +89,7 @@ void demorgan_worker(
 		RTLIL::Cell* srcinv = NULL;
 		for(auto x : ports)
 		{
-			if(x.port == TW::Y && x.cell->type == ID($_NOT_))
+			if(x.port == TW::Y && x.cell->type == TW($_NOT_))
 			{
 				srcinv = x.cell;
 				break;
@@ -158,9 +158,9 @@ void demorgan_worker(
 	cell->setPort(TW::A, insig);
 
 	//Change the cell type
-	if(cell->type == ID($reduce_and))
+	if(cell->type == TW($reduce_and))
 		cell->type_impl = TW::$reduce_or;
-	else if(cell->type == ID($reduce_or))
+	else if(cell->type == TW($reduce_or))
 		cell->type_impl = TW::$reduce_and;
 	//don't change XOR
 
diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc
index 9ae4a4ac3..d7f2cf83b 100644
--- a/passes/opt/opt_dff.cc
+++ b/passes/opt/opt_dff.cc
@@ -123,7 +123,7 @@ struct OptDffWorker
 					bitusers[bit]++;
 
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
+			if (cell->type.in(TW($mux), TW($pmux), TW($_MUX_))) {
 				RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
 				for (int i = 0; i < GetSize(sig_y); i++)
 					bit2mux[sig_y[i]] = cell_int_t(cell, i);
@@ -302,7 +302,7 @@ struct OptDffWorker
 				initvals.remove_init(ff.sig_q[i]);
 				module->connect(ff.sig_q[i], State::S0);
 				log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n",
-						i, cell, cell->type.unescape(), module);
+						i, cell, cell->type.unescaped(), module);
 				sr_removed = true;
 			} else if (is_always_active(ff.sig_set[i], ff.pol_set)) {
 				initvals.remove_init(ff.sig_q[i]);
@@ -313,7 +313,7 @@ struct OptDffWorker
 				else
 					module->addNot(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
 				log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
-						i, cell, cell->type.unescape(), module);
+						i, cell, cell->type.unescaped(), module);
 				sr_removed = true;
 			} else {
 				keep_bits.push_back(i);
@@ -336,7 +336,7 @@ struct OptDffWorker
 
 		if (clr_inactive && signal_all_same(ff.sig_set)) {
 			log("Removing never-active CLR on %s (%s) from module %s.\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_sr = false;
 			ff.has_arst = true;
 			ff.pol_arst = ff.pol_set;
@@ -345,7 +345,7 @@ struct OptDffWorker
 			changed = true;
 		} else if (set_inactive && signal_all_same(ff.sig_clr)) {
 			log("Removing never-active SET on %s (%s) from module %s.\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_sr = false;
 			ff.has_arst = true;
 			ff.pol_arst = ff.pol_clr;
@@ -371,7 +371,7 @@ struct OptDffWorker
 
 			if (!failed) {
 				log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
-						cell, cell->type.unescape(), module);
+						cell, cell->type.unescaped(), module);
 				ff.has_sr = false;
 				ff.has_arst = true;
 				ff.val_arst = val_arst_builder.build();
@@ -390,7 +390,7 @@ struct OptDffWorker
 		// Converts constant Async Load to ARST
 		if (is_always_inactive(ff.sig_aload, ff.pol_aload)) {
 			log("Removing never-active async load on %s (%s) from module %s.\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_aload = false;
 			changed = true;
 			return false;
@@ -399,7 +399,7 @@ struct OptDffWorker
 		if (is_active(ff.sig_aload, ff.pol_aload)) {
 			// ALOAD always active
 			log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.remove();
 
 			if (ff.has_sr) {
@@ -434,7 +434,7 @@ struct OptDffWorker
 		// AD is constant -> ARST
 		if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {
 			log("Changing const-value async load to async reset on %s (%s) from module %s.\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_arst = true;
 			ff.has_aload = false;
 			ff.sig_arst = ff.sig_aload;
@@ -451,12 +451,12 @@ struct OptDffWorker
 		// Removes ARST if never active or replaces FF if always active
 		if (is_inactive(ff.sig_arst, ff.pol_arst)) {
 			log("Removing never-active ARST on %s (%s) from module %s.\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_arst = false;
 			changed = true;
 		} else if (is_always_active(ff.sig_arst, ff.pol_arst)) {
 			log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.remove();
 			module->connect(ff.sig_q, ff.val_arst);
 			return true;
@@ -470,12 +470,12 @@ struct OptDffWorker
 		// Removes SRST if never active or forces D to reset value if always active
 		if (is_inactive(ff.sig_srst, ff.pol_srst)) {
 			log("Removing never-active SRST on %s (%s) from module %s.\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_srst = false;
 			changed = true;
 		} else if (is_always_active(ff.sig_srst, ff.pol_srst)) {
 			log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_srst = false;
 			if (!ff.ce_over_srst)
 				ff.has_ce = false;
@@ -490,7 +490,7 @@ struct OptDffWorker
 		if (is_always_inactive(ff.sig_ce, ff.pol_ce)) {
 			if (ff.has_srst && !ff.ce_over_srst) {
 				log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",
-						cell, cell->type.unescape(), module);
+						cell, cell->type.unescaped(), module);
 				ff.pol_ce = ff.pol_srst;
 				ff.sig_ce = ff.sig_srst;
 				ff.has_srst = false;
@@ -498,7 +498,7 @@ struct OptDffWorker
 				changed = true;
 			} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
 				log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
-						cell, cell->type.unescape(), module);
+						cell, cell->type.unescaped(), module);
 				ff.has_ce = ff.has_clk = ff.has_srst = false;
 				changed = true;
 			} else {
@@ -508,7 +508,7 @@ struct OptDffWorker
 			}
 		} else if (is_active(ff.sig_ce, ff.pol_ce)) {
 			log("Removing always-active EN on %s (%s) from module %s.\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_ce = false;
 			changed = true;
 		}
@@ -518,7 +518,7 @@ struct OptDffWorker
 	{
 		if (!opt.keepdc || ff.val_init.is_fully_def()) {
 			log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_ce = ff.has_clk = ff.has_srst = false;
 			changed = true;
 		} else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) {
@@ -533,7 +533,7 @@ struct OptDffWorker
 		// Detect feedback loops where D is hardwired to Q
 		if (ff.has_clk && ff.has_srst) {
 			log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			if (ff.has_ce && ff.ce_over_srst) {
 				SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine);
 				SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine);
@@ -550,7 +550,7 @@ struct OptDffWorker
 			changed = true;
 		} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
 			log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
-					cell, cell->type.unescape(), module);
+					cell, cell->type.unescaped(), module);
 			ff.has_gclk = ff.has_clk = ff.has_ce = false;
 			changed = true;
 		}
@@ -623,7 +623,7 @@ struct OptDffWorker
 				dff_cells.push_back(new_cell);
 
 			log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n",
-					cell, cell->type.unescape(), module,
+					cell, cell->type.unescaped(), module,
 					log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst));
 		}
 
@@ -693,7 +693,7 @@ struct OptDffWorker
 				dff_cells.push_back(new_cell);
 
 			log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n",
-					cell, cell->type.unescape(), module,
+					cell, cell->type.unescaped(), module,
 					log_signal(new_ff.sig_d), log_signal(new_ff.sig_q));
 		}
 
@@ -760,7 +760,7 @@ struct OptDffWorker
 
 			if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
 				log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",
-						cell, cell->type.unescape(), module);
+						cell, cell->type.unescaped(), module);
 				ff.has_aload = false;
 				changed = true;
 			}
@@ -878,7 +878,7 @@ struct OptDffWorker
 				}
 
 				log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
-						val ? 1 : 0, i, cell, cell->type.unescape(), module);
+						val ? 1 : 0, i, cell, cell->type.unescaped(), module);
 
 				// Replace the Q output with the constant value
 				initvals.remove_init(ff.sig_q[i]);
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index eeb7b556b..ee26c5131 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -46,9 +46,9 @@ void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
 
 	for (auto cell : module->cells())
 	for (auto &conn : cell->connections()) {
-		if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
+		if (!ct.cell_known(cell->type_impl) || ct.cell_output(cell->type_impl, conn.first))
 			driven_signals.add(sigmap(conn.second));
-		if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn.first))
+		if (!ct.cell_known(cell->type_impl) || ct.cell_input(cell->type_impl, conn.first))
 			used_signals.add(sigmap(conn.second));
 	}
 
@@ -180,20 +180,20 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 		int group_idx = GRP_DYN;
 		RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i];
 
-		if (cell->type == ID($or)) {
+		if (cell->type == TW($or)) {
 			if (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1)
 				bit_a = bit_b = RTLIL::State::S1;
 		}
-		else if (cell->type == ID($and)) {
+		else if (cell->type == TW($and)) {
 			if (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0)
 				bit_a = bit_b = RTLIL::State::S0;
 		}
 		else if (!keepdc) {
-			if (cell->type == ID($xor)) {
+			if (cell->type == TW($xor)) {
 				if (bit_a == bit_b)
 					bit_a = bit_b = RTLIL::State::S0;
 			}
-			else if (cell->type == ID($xnor)) {
+			else if (cell->type == TW($xnor)) {
 				if (bit_a == bit_b)
 					bit_a = bit_b = RTLIL::State::S1; // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_
 			}
@@ -257,15 +257,15 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 			slot++;
 		}
 
-		if (cell->type.in(ID($and), ID($or)) && kind == GRP_CONST_A) {
+		if (cell->type.in(TW($and), TW($or)) && kind == GRP_CONST_A) {
 			if (!keepdc) {
-				if (cell->type == ID($and))
+				if (cell->type == TW($and))
 					new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S0}, {State::Sz, State::S0}}, &new_b);
-				else if (cell->type == ID($or))
+				else if (cell->type == TW($or))
 					new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b);
 				else log_abort();
 			}
-			log_debug("  Direct Connection: %s (%s with %s)\n", log_signal(new_b), cell->type.unescape(), log_signal(new_a));
+			log_debug("  Direct Connection: %s (%s with %s)\n", log_signal(new_b), cell->type.unescaped(), log_signal(new_a));
 			// new_y becomes new_b directly: rewrite any bit_map entries pointing at new_y bits.
 			dict<SigBit, SigBit> remap;
 			for (int j = 0; j < group_size; j++)
@@ -277,26 +277,26 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 			continue;
 		}
 
-		if (cell->type.in(ID($xor), ID($xnor)) && kind == GRP_CONST_A) {
+		if (cell->type.in(TW($xor), TW($xnor)) && kind == GRP_CONST_A) {
 			SigSpec undef_a, undef_y, undef_b;
 			SigSpec def_y, def_a, def_b;
 			for (int j = 0; j < GetSize(new_y); j++) {
 				bool undef = new_a[j] == State::Sx || new_a[j] == State::Sz;
 				if (!keepdc && (undef || new_a[j] == new_b[j])) {
 					undef_a.append(new_a[j]);
-					if (cell->type == ID($xor))
+					if (cell->type == TW($xor))
 						undef_b.append(State::S0);
 					// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
-					else if (cell->type == ID($xnor))
+					else if (cell->type == TW($xnor))
 						undef_b.append(State::S1);
 					else log_abort();
 					undef_y.append(new_y[j]);
 				}
 				else if (new_a[j] == State::S0 || new_a[j] == State::S1) {
 					undef_a.append(new_a[j]);
-					if (cell->type == ID($xor))
+					if (cell->type == TW($xor))
 						undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_TWINE, new_b[j]).as_bit() : new_b[j]);
-					else if (cell->type == ID($xnor))
+					else if (cell->type == TW($xnor))
 						undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_TWINE, new_b[j]).as_bit());
 					else log_abort();
 					undef_y.append(new_y[j]);
@@ -308,7 +308,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 				}
 			}
 			if (!undef_y.empty()) {
-				log_debug("  Direct Connection: %s (%s with %s)\n", log_signal(undef_b), cell->type.unescape(), log_signal(undef_a));
+				log_debug("  Direct Connection: %s (%s with %s)\n", log_signal(undef_b), cell->type.unescaped(), log_signal(undef_a));
 				dict<SigBit, SigBit> remap;
 				for (int j = 0; j < GetSize(undef_y); j++)
 					remap[undef_y[j]] = undef_b[j];
@@ -324,7 +324,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 			new_y = std::move(def_y);
 		}
 
-		RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
+		RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type_impl);
 
 		c->setPort(TW::A, new_a);
 		c->parameters[ID::A_WIDTH] = new_a.size();
@@ -362,7 +362,7 @@ std::optional<SigBit> get_inverted_raw(SigBit s)
 	if (!s.is_wire() || !s.wire->known_driver())
 		return std::nullopt;
 	Cell* cell = s.wire->driverCell();
-	if (!cell->type.in(ID($_NOT_), ID($not), ID($logic_not)))
+	if (!cell->type.in(TW($_NOT_), TW($not), TW($logic_not)))
 		return std::nullopt;
 	if (GetSize(cell->getPort(TW::A)) != 1 || GetSize(cell->getPort(TW::Y)) != 1)
 		return std::nullopt;
@@ -385,8 +385,9 @@ void handle_polarity_inv(Cell *cell, TwineRef port, IdString param, const SigMap
 	SigBit sig = assign_map(raw);
 	if (auto inv_a = get_inverted_raw(sig)) {
 		SigBit new_sig = assign_map(*inv_a);
+		auto twines = cell->module->design->twines;
 		log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
-				IdString(RTLIL::StaticId(port)).unescape(), cell->type.unescape(), cell, cell->module,
+				twines.unescaped_str(port), cell->type.unescaped(), cell, cell->module,
 				log_signal(sig), log_signal(new_sig));
 		cell->setPort(port, new_sig);
 		cell->setParam(param, !cell->getParam(param).as_bool());
@@ -413,10 +414,11 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, TwineRe
 
 	if (cell->type.in(type1, type2)) {
 		SigSpec sig = assign_map(cell->getPort(port));
+		auto twines = cell->module->design->twines;
 		if (auto inv_a = get_inverted_raw(sig)) {
 			SigSpec new_sig = assign_map(*inv_a);
 			log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
-					IdString(RTLIL::StaticId(port)).unescape(), cell->type.unescape(), cell, cell->module,
+					twines.unescaped_str(port), cell->type.unescaped(), cell, cell->module,
 					log_signal(sig), log_signal(new_sig));
 			cell->setPort(port, new_sig);
 			cell->type_impl = cell->module->design->twines.add(Twine{cell->type == type1 ? type2 : type1});
@@ -480,27 +482,27 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	if (!noclkinv)
 	for (auto cell : dirty_cells)
 	if (design->selected(module, cell)) {
-		if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
+		if (cell->type.in(TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($sdff), TW($sdffe), TW($sdffce), TW($fsm), TW($memrd), TW($memrd_v2), TW($memwr), TW($memwr_v2)))
 			handle_polarity_inv(cell, TW::CLK, ID::CLK_POLARITY, assign_map);
 
-		if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
+		if (cell->type.in(TW($sr), TW($dffsr), TW($dffsre), TW($dlatchsr))) {
 			handle_polarity_inv(cell, TW::SET, ID::SET_POLARITY, assign_map);
 			handle_polarity_inv(cell, TW::CLR, ID::CLR_POLARITY, assign_map);
 		}
 
-		if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
+		if (cell->type.in(TW($adff), TW($adffe), TW($adlatch)))
 			handle_polarity_inv(cell, TW::ARST, ID::ARST_POLARITY, assign_map);
 
-		if (cell->type.in(ID($aldff), ID($aldffe)))
+		if (cell->type.in(TW($aldff), TW($aldffe)))
 			handle_polarity_inv(cell, TW::ALOAD, ID::ALOAD_POLARITY, assign_map);
 
-		if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+		if (cell->type.in(TW($sdff), TW($sdffe), TW($sdffce)))
 			handle_polarity_inv(cell, TW::SRST, ID::SRST_POLARITY, assign_map);
 
-		if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
+		if (cell->type.in(TW($dffe), TW($adffe), TW($aldffe), TW($sdffe), TW($sdffce), TW($dffsre), TW($dlatch), TW($adlatch), TW($dlatchsr)))
 			handle_polarity_inv(cell, TW::EN, ID::EN_POLARITY, assign_map);
 
-		if (!StaticCellTypes::Compat::stdcells_mem(cell->type))
+		if (!StaticCellTypes::Compat::stdcells_mem(cell->type_impl))
 			continue;
 
 		handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", TW::S, assign_map);
@@ -560,19 +562,19 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	dict<RTLIL::SigBit, Cell*> outbit_to_cell;
 
 	for (auto cell : dirty_cells)
-	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
+	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type_impl)) {
 		for (auto &conn : cell->connections())
-		if (yosys_celltypes.cell_output(cell->type, conn.first))
+		if (yosys_celltypes.cell_output(cell->type_impl, conn.first))
 		for (auto bit : assign_map(conn.second))
 			outbit_to_cell[bit] = cell;
 		cells.node(cell);
 	}
 
 	for (auto cell : dirty_cells)
-	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
+	if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type_impl)) {
 		const int r_index = cells.node(cell);
 		for (auto &conn : cell->connections())
-		if (yosys_celltypes.cell_input(cell->type, conn.first))
+		if (yosys_celltypes.cell_input(cell->type_impl, conn.first))
 		for (auto bit : assign_map(conn.second))
 		if (outbit_to_cell.count(bit))
 			cells.edge(cells.node(outbit_to_cell.at(bit)), r_index);
@@ -594,16 +596,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		bool detect_const_and = false;
 		bool detect_const_or = false;
 
-		if (cell->type.in(ID($reduce_and), ID($_AND_)))
+		if (cell->type.in(TW($reduce_and), TW($_AND_)))
 			detect_const_and = true;
 
-		if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
+		if (cell->type.in(TW($and), TW($logic_and)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
 			detect_const_and = true;
 
-		if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_)))
+		if (cell->type.in(TW($reduce_or), TW($reduce_bool), TW($_OR_)))
 			detect_const_or = true;
 
-		if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
+		if (cell->type.in(TW($or), TW($logic_or)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
 			detect_const_or = true;
 
 		if (detect_const_and || detect_const_or)
@@ -656,17 +658,17 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()))
+		if (cell->type.in(TW($_XOR_), TW($_XNOR_)) || (cell->type.in(TW($xor), TW($xnor)) && GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()))
 		{
 			SigBit sig_a = assign_map(cell->getPort(TW::A));
 			SigBit sig_b = assign_map(cell->getPort(TW::B));
 			if (!keepdc && (sig_a == sig_b || sig_a == State::Sx || sig_a == State::Sz || sig_b == State::Sx || sig_b == State::Sz)) {
 				OptExprPatcher patcher(module, &assign_map);
-				if (cell->type.in(ID($xor), ID($_XOR_))) {
+				if (cell->type.in(TW($xor), TW($_XOR_))) {
 					patcher.patch(cell, TW::Y, RTLIL::State::S0, "const_xor");
 					goto next_cell;
 				}
-				if (cell->type.in(ID($xnor), ID($_XNOR_))) {
+				if (cell->type.in(TW($xnor), TW($_XNOR_))) {
 					// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
 					int width = GetSize(cell->getPort(TW::Y));
 					patcher.patch(cell, TW::Y, SigSpec(RTLIL::State::S1, width), "const_xnor");
@@ -679,9 +681,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				std::swap(sig_a, sig_b);
 			if (sig_b == State::S0 || sig_b == State::S1) {
 				OptExprPatcher patcher(module, &assign_map);
-				bool is_gate = cell->type.in(ID($_XOR_), ID($_XNOR_));
+				bool is_gate = cell->type.in(TW($_XOR_), TW($_XNOR_));
 				int width = is_gate ? 1 : cell->getParam(ID::Y_WIDTH).as_int();
-				if (cell->type.in(ID($xor), ID($_XOR_))) {
+				if (cell->type.in(TW($xor), TW($_XOR_))) {
 					if (sig_b == State::S0) {
 						SigSpec sig_y = sig_a;
 						sig_y.append(RTLIL::Const(State::S0, width-1));
@@ -693,7 +695,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					}
 					goto next_cell;
 				}
-				if (cell->type.in(ID($xnor), ID($_XNOR_))) {
+				if (cell->type.in(TW($xnor), TW($_XNOR_))) {
 					if (sig_b == State::S1) {
 						SigSpec sig_y = sig_a;
 						sig_y.append(RTLIL::Const(State::S1, width-1));
@@ -709,10 +711,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&
+		if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool), TW($reduce_xor), TW($reduce_xnor), TW($neg)) &&
 				GetSize(cell->getPort(TW::A)) == 1 && GetSize(cell->getPort(TW::Y)) == 1)
 		{
-			if (cell->type == ID($reduce_xnor)) {
+			if (cell->type == TW($reduce_xnor)) {
 				log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
 						cell->type.unescape(), cell->module->design->twines.str(cell->meta_->name), module);
 				cell->type_impl = TW::$not;
@@ -724,7 +726,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			goto next_cell;
 		}
 
-		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor)))
+		if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor)))
 		{
 			RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 			RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
@@ -750,8 +752,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				// Per-i (group, position_in_group); group = -1 means leave as Sx
 				std::vector<std::pair<int, int>> origin(width, {-1, 0});
 
-				auto group_0 = cell->type == ID($xnor) ? 1 : 0;
-				auto group_1 = cell->type == ID($xnor) ? 0 : 1;
+				auto group_0 = cell->type == TW($xnor) ? 1 : 0;
+				auto group_1 = cell->type == TW($xnor) ? 0 : 1;
 
 				for (int i = 0; i < width; i++) {
 					auto bit_a = sig_a[i].data;
@@ -760,13 +762,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					else if (bit_a == State::Sx) origin[i] = {2, b_group_x.size()}, b_group_x.append(sig_b[i]);
 				}
 
-				if (cell->type == ID($xnor))
+				if (cell->type == TW($xnor))
 					std::swap(b_group_0, b_group_1);
 
 				OptExprPatcher patcher(module, &assign_map);
 				RTLIL::SigSpec y_new_0, y_new_1, y_new_x;
 
-				if (cell->type == ID($and)) {
+				if (cell->type == TW($and)) {
 					if (!b_group_0.empty()) y_new_0 = Const(State::S0, GetSize(b_group_0));
 					if (!b_group_1.empty()) y_new_1 = b_group_1;
 					if (!b_group_x.empty()) {
@@ -775,7 +777,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						else
 							y_new_x = Const(State::S0, GetSize(b_group_x));
 					}
-				} else if (cell->type == ID($or)) {
+				} else if (cell->type == TW($or)) {
 					if (!b_group_0.empty()) y_new_0 = b_group_0;
 					if (!b_group_1.empty()) y_new_1 = Const(State::S1, GetSize(b_group_1));
 					if (!b_group_x.empty()) {
@@ -784,7 +786,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						else
 							y_new_x = Const(State::S1, GetSize(b_group_x));
 					}
-				} else if (cell->type.in(ID($xor), ID($xnor))) {
+				} else if (cell->type.in(TW($xor), TW($xnor))) {
 					if (!b_group_0.empty()) y_new_0 = b_group_0;
 					if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_TWINE, b_group_1);
 					if (!b_group_x.empty()) {
@@ -809,7 +811,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type == ID($bwmux))
+		if (cell->type == TW($bwmux))
 		{
 			RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 			RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
@@ -866,13 +868,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		if (do_fine)
 		{
-			if (cell->type.in(ID($not), ID($pos), ID($and), ID($or), ID($xor), ID($xnor)))
+			if (cell->type.in(TW($not), TW($pos), TW($and), TW($or), TW($xor), TW($xnor)))
 				if (group_cell_inputs(module, cell, true, assign_map, keepdc))
 					goto next_cell;
 
-			if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_or), ID($reduce_and), ID($reduce_bool)))
+			if (cell->type.in(TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_or), TW($reduce_and), TW($reduce_bool)))
 			{
-				SigBit neutral_bit = cell->type == ID($reduce_and) ? State::S1 : State::S0;
+				SigBit neutral_bit = cell->type == TW($reduce_and) ? State::S1 : State::S0;
 
 				RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 				RTLIL::SigSpec new_sig_a;
@@ -892,7 +894,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type.in(ID($logic_and), ID($logic_or)))
+			if (cell->type.in(TW($logic_and), TW($logic_or)))
 			{
 				SigBit neutral_bit = State::S0;
 
@@ -914,7 +916,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type == ID($reduce_and))
+			if (cell->type == TW($reduce_and))
 			{
 				RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 
@@ -939,7 +941,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_or), ID($reduce_bool)))
+			if (cell->type.in(TW($logic_not), TW($logic_and), TW($logic_or), TW($reduce_or), TW($reduce_bool)))
 			{
 				RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 
@@ -964,7 +966,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type.in(ID($logic_and), ID($logic_or)))
+			if (cell->type.in(TW($logic_and), TW($logic_or)))
 			{
 				RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
 
@@ -989,13 +991,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type.in(ID($add), ID($sub)))
+			if (cell->type.in(TW($add), TW($sub)))
 			{
 				RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 				RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
 				RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
 				bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
-				bool sub = cell->type == ID($sub);
+				bool sub = cell->type == TW($sub);
 
 				int minsz = GetSize(sig_y);
 				minsz = std::min(minsz, GetSize(sig_a));
@@ -1015,7 +1017,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						break;
 				}
 				if (i > 0) {
-					log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
+					log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescaped(), cell, module);
 					SigSpec new_a = sig_a.extract_end(i);
 					SigSpec new_b = sig_b.extract_end(i);
 					if (new_a.empty() && is_signed)
@@ -1030,7 +1032,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type == ID($alu))
+			if (cell->type == TW($alu))
 			{
 				RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 				RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
@@ -1071,7 +1073,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						break;
 				}
 				if (i > 0) {
-					log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
+					log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescaped(), cell, module);
 					SigSpec new_a = sig_a.extract_end(i);
 					SigSpec new_b = sig_b.extract_end(i);
 					if (new_a.empty() && is_signed)
@@ -1090,13 +1092,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		}
 skip_fine_alu:
 
-		if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($shift), ID($shiftx), ID($shl), ID($shr), ID($sshl), ID($sshr),
-					ID($lt), ID($le), ID($ge), ID($gt), ID($neg), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
+		if (cell->type.in(TW($reduce_xor), TW($reduce_xnor), TW($shift), TW($shiftx), TW($shl), TW($shr), TW($sshl), TW($sshr),
+					TW($lt), TW($le), TW($ge), TW($gt), TW($neg), TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow)))
 		{
 			RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
 			RTLIL::SigSpec sig_b = cell->hasPort(TW::B) ? assign_map(cell->getPort(TW::B)) : RTLIL::SigSpec();
 
-			if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
+			if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
 				sig_a = RTLIL::SigSpec();
 
 			for (auto &bit : sig_a.to_sigbit_vector())
@@ -1110,7 +1112,7 @@ skip_fine_alu:
 			if (0) {
 		found_the_x_bit:
 				OptExprPatcher patcher(module, &assign_map);
-				if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
+				if (cell->type.in(TW($reduce_xor), TW($reduce_xnor), TW($lt), TW($le), TW($ge), TW($gt)))
 					patcher.patch(cell, TW::Y, RTLIL::State::Sx, "x-bit in input");
 				else
 					patcher.patch(cell, TW::Y, RTLIL::SigSpec(RTLIL::State::Sx, GetSize(cell->getPort(TW::Y))), "x-bit in input");
@@ -1118,11 +1120,11 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($shiftx), ID($shift)) && (cell->type == ID($shiftx) || !cell->getParam(ID::A_SIGNED).as_bool())) {
+		if (cell->type.in(TW($shiftx), TW($shift)) && (cell->type == TW($shiftx) || !cell->getParam(ID::A_SIGNED).as_bool())) {
 			SigSpec sig_a = assign_map(cell->getPort(TW::A));
 			int width;
-			bool trim_x = cell->type == ID($shiftx) || !keepdc;
-			bool trim_0 = cell->type == ID($shift);
+			bool trim_x = cell->type == TW($shiftx) || !keepdc;
+			bool trim_0 = cell->type == TW($shift);
 			for (width = GetSize(sig_a); width > 1; width--) {
 				if ((trim_x && sig_a[width-1] == State::Sx) ||
 					(trim_0 && sig_a[width-1] == State::S0))
@@ -1139,7 +1141,7 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && GetSize(cell->getPort(TW::Y)) == 1 && GetSize(cell->getPort(TW::A)) == 1) {
+		if (cell->type.in(TW($_NOT_), TW($not), TW($logic_not)) && GetSize(cell->getPort(TW::Y)) == 1 && GetSize(cell->getPort(TW::A)) == 1) {
 			if (auto inv_a = get_inverted(cell->getPort(TW::A), assign_map)) {
 				OptExprPatcher patcher(module, &assign_map);
 				patcher.patch(cell, TW::Y, *inv_a, "double_invert");
@@ -1147,9 +1149,9 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($_MUX_), ID($mux))) {
+		if (cell->type.in(TW($_MUX_), TW($mux))) {
 			if (auto inv_a = get_inverted(cell->getPort(TW::S), assign_map)) {
-				log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", cell->type.unescape(), cell, module);
+				log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", cell->type.unescaped(), cell, module);
 				RTLIL::SigSpec tmp = cell->getPort(TW::A);
 				cell->setPort(TW::A, cell->getPort(TW::B));
 				cell->setPort(TW::B, tmp);
@@ -1159,7 +1161,7 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type == ID($_NOT_)) {
+		if (cell->type == TW($_NOT_)) {
 			RTLIL::SigSpec input = cell->getPort(TW::A);
 			assign_map.apply(input);
 			if (input.match("1")) ACTION_DO_Y(0);
@@ -1167,7 +1169,7 @@ skip_fine_alu:
 			if (input.match("*")) ACTION_DO_Y(x);
 		}
 
-		if (cell->type == ID($_AND_)) {
+		if (cell->type == TW($_AND_)) {
 			RTLIL::SigSpec input;
 			input.append(cell->getPort(TW::B));
 			input.append(cell->getPort(TW::A));
@@ -1186,7 +1188,7 @@ skip_fine_alu:
 			if (input.match("1 ")) ACTION_DO(TW::Y, input.extract(0, 1));
 		}
 
-		if (cell->type == ID($_OR_)) {
+		if (cell->type == TW($_OR_)) {
 			RTLIL::SigSpec input;
 			input.append(cell->getPort(TW::B));
 			input.append(cell->getPort(TW::A));
@@ -1205,7 +1207,7 @@ skip_fine_alu:
 			if (input.match("0 ")) ACTION_DO(TW::Y, input.extract(0, 1));
 		}
 
-		if (cell->type == ID($_XOR_)) {
+		if (cell->type == TW($_XOR_)) {
 			RTLIL::SigSpec input;
 			input.append(cell->getPort(TW::B));
 			input.append(cell->getPort(TW::A));
@@ -1220,7 +1222,7 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type == ID($_MUX_)) {
+		if (cell->type == TW($_MUX_)) {
 			RTLIL::SigSpec input;
 			input.append(cell->getPort(TW::S));
 			input.append(cell->getPort(TW::B));
@@ -1250,8 +1252,8 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($_TBUF_), ID($tribuf))) {
-			RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? TW::E : TW::EN);
+		if (cell->type.in(TW($_TBUF_), TW($tribuf))) {
+			RTLIL::SigSpec input = cell->getPort(cell->type == TW($_TBUF_) ? TW::E : TW::EN);
 			RTLIL::SigSpec a = cell->getPort(TW::A);
 			assign_map.apply(input);
 			assign_map.apply(a);
@@ -1266,7 +1268,7 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
+		if (cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex)))
 		{
 			RTLIL::SigSpec a = cell->getPort(TW::A);
 			RTLIL::SigSpec b = cell->getPort(TW::B);
@@ -1282,7 +1284,7 @@ skip_fine_alu:
 			log_assert(GetSize(a) == GetSize(b));
 			for (int i = 0; i < GetSize(a); i++) {
 				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
-					RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ?  RTLIL::State::S0 : RTLIL::State::S1);
+					RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(TW($eq), TW($eqx)) ?  RTLIL::State::S0 : RTLIL::State::S1);
 					new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
 					OptExprPatcher patcher(module, &assign_map);
 					patcher.patch(cell, TW::Y, new_y, "isneq");
@@ -1300,7 +1302,7 @@ skip_fine_alu:
 			}
 
 			if (new_a.size() == 0) {
-				RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ?  RTLIL::State::S1 : RTLIL::State::S0);
+				RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(TW($eq), TW($eqx)) ?  RTLIL::State::S1 : RTLIL::State::S0);
 				new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
 				OptExprPatcher patcher(module, &assign_map);
 				patcher.patch(cell, TW::Y, new_y, "empty");
@@ -1315,7 +1317,7 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 &&
+		if (cell->type.in(TW($eq), TW($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 &&
 				cell->parameters[ID::A_WIDTH].as_int() == 1 && cell->parameters[ID::B_WIDTH].as_int() == 1)
 		{
 			RTLIL::SigSpec a = assign_map(cell->getPort(TW::A));
@@ -1332,11 +1334,11 @@ skip_fine_alu:
 					RTLIL::SigSpec input = b;
 					ACTION_DO(TW::Y, Const(State::Sx, GetSize(cell->getPort(TW::Y))));
 				} else
-				if (b.as_bool() == (cell->type == ID($eq))) {
+				if (b.as_bool() == (cell->type == TW($eq))) {
 					RTLIL::SigSpec input = b;
 					ACTION_DO(TW::Y, cell->getPort(TW::A));
 				} else {
-					log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
+					log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescaped(), cell, module);
 					cell->parameters.erase(ID::B_WIDTH);
 					cell->parameters.erase(ID::B_SIGNED);
 					cell->unsetPort(TW::B);
@@ -1347,11 +1349,11 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($eq), ID($ne)) &&
+		if (cell->type.in(TW($eq), TW($ne)) &&
 				(assign_map(cell->getPort(TW::A)).is_fully_zero() || assign_map(cell->getPort(TW::B)).is_fully_zero()))
 		{
-			log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescape(), cell,
-					module, cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
+			log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescaped(), cell,
+					module, cell->type == TW($eq) ? "$logic_not" : "$reduce_bool");
 			if (assign_map(cell->getPort(TW::A)).is_fully_zero()) {
 				cell->setPort(TW::A, cell->getPort(TW::B));
 				cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
@@ -1360,28 +1362,28 @@ skip_fine_alu:
 			cell->unsetPort(TW::B);
 			cell->unsetParam(ID::B_SIGNED);
 			cell->unsetParam(ID::B_WIDTH);
-			cell->type_impl = (cell->type == ID($eq)) ? TW::$logic_not : TW::$reduce_bool;
+			cell->type_impl = (cell->type == TW($eq)) ? TW::$logic_not : TW::$reduce_bool;
 			did_something = true;
 			goto next_cell;
 		}
 
-		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && (keepdc ? assign_map(cell->getPort(TW::B)).is_fully_def() : assign_map(cell->getPort(TW::B)).is_fully_const()))
+		if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)) && (keepdc ? assign_map(cell->getPort(TW::B)).is_fully_def() : assign_map(cell->getPort(TW::B)).is_fully_const()))
 		{
-			bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
+			bool sign_ext = cell->type == TW($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
 			RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
-			const bool b_sign_ext = cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool();
+			const bool b_sign_ext = cell->type.in(TW($shift), TW($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool();
 			// We saturate the value to prevent overflow, but note that this could
 			// cause incorrect opimization in the impractical case that A is 2^32 bits
 			// wide
 			int shift_bits = sig_b.as_int_saturating(b_sign_ext);
 
-			if (cell->type.in(ID($shl), ID($sshl)))
+			if (cell->type.in(TW($shl), TW($sshl)))
 				shift_bits *= -1;
 
 			RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
-			RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
+			RTLIL::SigSpec sig_y(cell->type == TW($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
 
-			if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y))
+			if (cell->type != TW($shiftx) && GetSize(sig_a) < GetSize(sig_y))
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 
 			// Limit indexing to the size of a, which is behaviourally identical (result is all 0)
@@ -1411,14 +1413,14 @@ skip_fine_alu:
 			bool identity_wrt_b = false;
 			bool arith_inverse = false;
 
-			if (cell->type.in(ID($add), ID($sub), ID($alu), ID($or), ID($xor)))
+			if (cell->type.in(TW($add), TW($sub), TW($alu), TW($or), TW($xor)))
 			{
 				RTLIL::SigSpec a = assign_map(cell->getPort(TW::A));
 				RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
 
-				bool sub = cell->type == ID($sub);
+				bool sub = cell->type == TW($sub);
 
-				if (cell->type == ID($alu)) {
+				if (cell->type == TW($alu)) {
 					RTLIL::SigBit sig_ci = assign_map(cell->getPort(TW::CI));
 					RTLIL::SigBit sig_bi = assign_map(cell->getPort(TW::BI));
 
@@ -1437,7 +1439,7 @@ skip_fine_alu:
 					identity_wrt_a = true;
 			}
 
-			if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
+			if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
 			{
 				RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
 
@@ -1445,7 +1447,7 @@ skip_fine_alu:
 					identity_wrt_a = true;
 			}
 
-			if (cell->type == ID($mul))
+			if (cell->type == TW($mul))
 			{
 				RTLIL::SigSpec a = assign_map(cell->getPort(TW::A));
 				RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
@@ -1457,7 +1459,7 @@ skip_fine_alu:
 					identity_wrt_a = true;
 			}
 
-			if (cell->type == ID($div))
+			if (cell->type == TW($div))
 			{
 				RTLIL::SigSpec b = assign_map(cell->getPort(TW::B));
 
@@ -1470,7 +1472,7 @@ skip_fine_alu:
 				log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
 					cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), identity_wrt_a ? 'A' : 'B');
 
-				if (cell->type == ID($alu)) {
+				if (cell->type == TW($alu)) {
 					bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
 					bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
 					bool is_signed = a_signed && b_signed;
@@ -1502,7 +1504,7 @@ skip_fine_alu:
 						a_port_width = cell->getParam(identity_wrt_a ? ID::A_WIDTH : ID::B_WIDTH).as_int();
 					}
 
-					IdString new_type = arith_inverse ? ID($neg) : ID($pos);
+					TwineRef new_type = arith_inverse ? TW($neg) : TW($pos);
 					SigSpec new_y = patcher.addWire(NEW_TWINE, y_width);
 					Cell *new_cell = patcher.addCell(NEW_TWINE, new_type);
 					new_cell->setPort(TW::A, a_port);
@@ -1533,20 +1535,20 @@ skip_fine_alu:
 		}
 skip_identity:
 
-		if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
+		if (mux_bool && cell->type.in(TW($mux), TW($_MUX_)) &&
 				cell->getPort(TW::A) == State::S0 && cell->getPort(TW::B) == State::S1) {
 			OptExprPatcher patcher(module, &assign_map);
 			patcher.patch(cell, TW::Y, cell->getPort(TW::S), "mux_bool");
 			goto next_cell;
 		}
 
-		if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
+		if (mux_bool && cell->type.in(TW($mux), TW($_MUX_)) &&
 				cell->getPort(TW::A) == State::S1 && cell->getPort(TW::B) == State::S0) {
-			log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
+			log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescaped(), cell, module);
 			cell->setPort(TW::A, cell->getPort(TW::S));
 			cell->unsetPort(TW::B);
 			cell->unsetPort(TW::S);
-			if (cell->type == ID($mux)) {
+			if (cell->type == TW($mux)) {
 				Const width = cell->parameters[ID::WIDTH];
 				cell->parameters[ID::A_WIDTH] = width;
 				cell->parameters[ID::Y_WIDTH] = width;
@@ -1559,11 +1561,11 @@ skip_identity:
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(TW::A) == State::S0) {
-			log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", cell->type.unescape(), cell, module);
+		if (consume_x && mux_bool && cell->type.in(TW($mux), TW($_MUX_)) && cell->getPort(TW::A) == State::S0) {
+			log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", cell->type.unescaped(), cell, module);
 			cell->setPort(TW::A, cell->getPort(TW::S));
 			cell->unsetPort(TW::S);
-			if (cell->type == ID($mux)) {
+			if (cell->type == TW($mux)) {
 				Const width = cell->parameters[ID::WIDTH];
 				cell->parameters[ID::A_WIDTH] = width;
 				cell->parameters[ID::B_WIDTH] = width;
@@ -1578,11 +1580,11 @@ skip_identity:
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(TW::B) == State::S1) {
-			log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", cell->type.unescape(), cell, module);
+		if (consume_x && mux_bool && cell->type.in(TW($mux), TW($_MUX_)) && cell->getPort(TW::B) == State::S1) {
+			log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", cell->type.unescaped(), cell, module);
 			cell->setPort(TW::B, cell->getPort(TW::S));
 			cell->unsetPort(TW::S);
-			if (cell->type == ID($mux)) {
+			if (cell->type == TW($mux)) {
 				Const width = cell->parameters[ID::WIDTH];
 				cell->parameters[ID::A_WIDTH] = width;
 				cell->parameters[ID::B_WIDTH] = width;
@@ -1597,7 +1599,7 @@ skip_identity:
 			goto next_cell;
 		}
 
-		if (mux_undef && cell->type.in(ID($mux), ID($pmux))) {
+		if (mux_undef && cell->type.in(TW($mux), TW($pmux))) {
 			RTLIL::SigSpec new_a, new_b, new_s;
 			int width = GetSize(cell->getPort(TW::A));
 			if ((cell->getPort(TW::A).is_fully_undef() && cell->getPort(TW::B).is_fully_undef()) ||
@@ -1632,7 +1634,7 @@ skip_identity:
 			}
 			if (cell->getPort(TW::S).size() != new_s.size()) {
 				log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
-						GetSize(cell->getPort(TW::S)) - GetSize(new_s), cell->type.unescape(), cell, module);
+						GetSize(cell->getPort(TW::S)) - GetSize(new_s), cell->type.unescaped(), cell, module);
 				cell->setPort(TW::A, new_a);
 				cell->setPort(TW::B, new_b);
 				cell->setPort(TW::S, new_s);
@@ -1647,10 +1649,10 @@ skip_identity:
 			}
 		}
 
-		if (mux_undef && cell->type.in(ID($_MUX4_), ID($_MUX8_), ID($_MUX16_))) {
+		if (mux_undef && cell->type.in(TW($_MUX4_), TW($_MUX8_), TW($_MUX16_))) {
 			int num_inputs = 4;
-			if (cell->type == ID($_MUX8_)) num_inputs = 8;
-			if (cell->type == ID($_MUX16_)) num_inputs = 16;
+			if (cell->type == TW($_MUX8_)) num_inputs = 8;
+			if (cell->type == TW($_MUX16_)) num_inputs = 16;
 			int undef_inputs = 0;
 			for (auto &conn : cell->connections())
 				if (conn.first != TW::S && conn.first != TW::T && conn.first != TW::U && conn.first != TW::V && conn.first != TW::Y)
@@ -1663,7 +1665,7 @@ skip_identity:
 		}
 
 #define FOLD_1ARG_CELL(_t) \
-		if (cell->type == ID($##_t)) { \
+		if (cell->type == TW($##_t)) { \
 			RTLIL::SigSpec a = cell->getPort(TW::A); \
 			assign_map.apply(a); \
 			if (a.is_fully_const()) { \
@@ -1677,7 +1679,7 @@ skip_identity:
 			} \
 		}
 #define FOLD_2ARG_CELL(_t) \
-		if (cell->type == ID($##_t)) { \
+		if (cell->type == TW($##_t)) { \
 			RTLIL::SigSpec a = cell->getPort(TW::A); \
 			RTLIL::SigSpec b = cell->getPort(TW::B); \
 			assign_map.apply(a), assign_map.apply(b); \
@@ -1692,7 +1694,7 @@ skip_identity:
 			} \
 		}
 #define FOLD_2ARG_SIMPLE_CELL(_t, B_ID) \
-		if (cell->type == ID($##_t)) { \
+		if (cell->type == TW($##_t)) { \
 			RTLIL::SigSpec a = cell->getPort(TW::A); \
 			RTLIL::SigSpec b = cell->getPort(B_ID); \
 			assign_map.apply(a), assign_map.apply(b); \
@@ -1704,7 +1706,7 @@ skip_identity:
 			} \
 		}
 #define FOLD_MUX_CELL(_t) \
-		if (cell->type == ID($##_t)) { \
+		if (cell->type == TW($##_t)) { \
 			RTLIL::SigSpec a = cell->getPort(TW::A); \
 			RTLIL::SigSpec b = cell->getPort(TW::B); \
 			RTLIL::SigSpec s = cell->getPort(TW::S); \
@@ -1770,7 +1772,7 @@ skip_identity:
 		FOLD_MUX_CELL(bwmux);
 
 		// be very conservative with optimizing $mux cells as we do not want to break mux trees
-		if (cell->type == ID($mux)) {
+		if (cell->type == TW($mux)) {
 			RTLIL::SigSpec input = assign_map(cell->getPort(TW::S));
 			RTLIL::SigSpec inA = assign_map(cell->getPort(TW::A));
 			RTLIL::SigSpec inB = assign_map(cell->getPort(TW::B));
@@ -1779,7 +1781,7 @@ skip_identity:
 			else if (inA == inB)
 				ACTION_DO(TW::Y, cell->getPort(TW::A));
 		}
-		if (cell->type == ID($pow) && cell->getPort(TW::A).is_fully_const() && !cell->parameters[ID::B_SIGNED].as_bool()) {
+		if (cell->type == TW($pow) && cell->getPort(TW::A).is_fully_const() && !cell->parameters[ID::B_SIGNED].as_bool()) {
 			SigSpec sig_a = assign_map(cell->getPort(TW::A));
 			SigSpec sig_y = assign_map(cell->getPort(TW::Y));
 			int y_size = GetSize(sig_y);
@@ -1806,7 +1808,7 @@ skip_identity:
 					int a_width = cell->parameters[ID::A_WIDTH].as_int();
 
 					SigSpec y_wire = patcher.addWire(NEW_TWINE, y_size);
-					Cell *mul = patcher.addCell(NEW_TWINE, ID($mul));
+					Cell *mul = patcher.addCell(NEW_TWINE, TW($mul));
 					mul->setPort(TW::A, Const(bit_idx, a_width));
 					mul->setPort(TW::B, cell->getPort(TW::B));
 					mul->setPort(TW::Y, y_wire);
@@ -1826,7 +1828,7 @@ skip_identity:
 				goto next_cell;
 			}
 		}
-		if (!keepdc && cell->type == ID($mul))
+		if (!keepdc && cell->type == TW($mul))
 		{
 			bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
 			bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
@@ -1914,7 +1916,7 @@ skip_identity:
 			}
 		}
 
-		if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))
+		if (cell->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor)))
 		{
 			bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
 			bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
@@ -1937,9 +1939,9 @@ skip_identity:
 				int exp;
 				if (!keepdc && sig_b.is_onehot(&exp) && !(b_signed && exp == GetSize(sig_b) - 1))
 				{
-					if (cell->type.in(ID($div), ID($divfloor)))
+					if (cell->type.in(TW($div), TW($divfloor)))
 					{
-						bool is_truncating = cell->type == ID($div);
+						bool is_truncating = cell->type == TW($div);
 						log_debug("Replacing %s-divide-by-%s cell `%s' in module `%s' with shift-by-%d.\n",
 								is_truncating ? "truncating" : "flooring",
 								log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), exp);
@@ -1965,9 +1967,9 @@ skip_identity:
 
 						cell->check();
 					}
-					else if (cell->type.in(ID($mod), ID($modfloor)))
+					else if (cell->type.in(TW($mod), TW($modfloor)))
 					{
-						bool is_truncating = cell->type == ID($mod);
+						bool is_truncating = cell->type == TW($mod);
 						log_debug("Replacing %s-modulo-by-%s cell `%s' in module `%s' with bitmask.\n",
 								is_truncating ? "truncating" : "flooring",
 								log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
@@ -2010,7 +2012,7 @@ skip_identity:
 		}
 
 		// Find places in $alu cell where the carry is constant, and split it at these points.
-		if (do_fine && !keepdc && cell->type == ID($alu))
+		if (do_fine && !keepdc && cell->type == TW($alu))
 		{
 			bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
 			bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
@@ -2075,7 +2077,7 @@ skip_identity:
 				SigSpec slice_x = patcher.addWire(NEW_TWINE, sz);
 				SigSpec slice_co = patcher.addWire(NEW_TWINE, sz);
 
-				RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
+				RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type_impl);
 				c->setPort(TW::A, sig_a.extract(prev, sz));
 				c->setPort(TW::B, sig_b.extract(prev, sz));
 				c->setPort(TW::BI, sig_bi);
@@ -2107,7 +2109,7 @@ skip_alu_split:
 
 		// remove redundant pairs of bits in ==, ===, !=, and !==
 		// replace cell with const driver if inputs can't be equal
-		if (do_fine && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
+		if (do_fine && cell->type.in(TW($eq), TW($ne), TW($eqx), TW($nex)))
 		{
 			pool<pair<SigBit, SigBit>> redundant_cache;
 			mfp<SigBit> contradiction_cache;
@@ -2153,7 +2155,7 @@ skip_alu_split:
 			if (contradiction_cache.find(State::S0) == contradiction_cache.find(State::S1))
 			{
 				SigSpec y_sig = cell->getPort(TW::Y);
-				Const y_value(cell->type.in(ID($eq), ID($eqx)) ? 0 : 1, GetSize(y_sig));
+				Const y_value(cell->type.in(TW($eq), TW($eqx)) ? 0 : 1, GetSize(y_sig));
 
 				log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
 					cell, module, log_signal(y_value));
@@ -2166,7 +2168,7 @@ skip_alu_split:
 			if (redundant_bits)
 			{
 				log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
-						redundant_bits, cell->type.unescape(), cell, module);
+						redundant_bits, cell->type.unescaped(), cell, module);
 
 				cell->setPort(TW::A, sig_a);
 				cell->setPort(TW::B, sig_b);
@@ -2179,7 +2181,7 @@ skip_alu_split:
 		}
 
 		// simplify comparisons
-		if (do_fine && cell->type.in(ID($lt), ID($ge), ID($gt), ID($le)))
+		if (do_fine && cell->type.in(TW($lt), TW($ge), TW($gt), TW($le)))
 		{
 			IdString cmp_type = cell->type;
 			SigSpec var_sig = cell->getPort(TW::A);
@@ -2192,14 +2194,14 @@ skip_alu_split:
 			{
 				std::swap(var_sig, const_sig);
 				std::swap(var_width, const_width);
-				if (cmp_type == ID($gt))
-					cmp_type = ID($lt);
-				else if (cmp_type == ID($lt))
-					cmp_type = ID($gt);
-				else if (cmp_type == ID($ge))
-					cmp_type = ID($le);
-				else if (cmp_type == ID($le))
-					cmp_type = ID($ge);
+				if (cmp_type == TW($gt))
+					cmp_type = TW($lt);
+				else if (cmp_type == TW($lt))
+					cmp_type = TW($gt);
+				else if (cmp_type == TW($ge))
+					cmp_type = TW($le);
+				else if (cmp_type == TW($le))
+					cmp_type = TW($ge);
 			}
 
 			if (const_sig.is_fully_def() && const_sig.is_fully_const())
@@ -2211,25 +2213,25 @@ skip_alu_split:
 
 				if (!is_signed)
 				{ /* unsigned */
-					if (const_sig.is_fully_zero() && cmp_type == ID($lt)) {
+					if (const_sig.is_fully_zero() && cmp_type == TW($lt)) {
 						condition   = "unsigned X<0";
 						replacement = "constant 0";
 						replace_sig[0] = State::S0;
 						replace = true;
 					}
-					if (const_sig.is_fully_zero() && cmp_type == ID($ge)) {
+					if (const_sig.is_fully_zero() && cmp_type == TW($ge)) {
 						condition   = "unsigned X>=0";
 						replacement = "constant 1";
 						replace_sig[0] = State::S1;
 						replace = true;
 					}
-					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == ID($gt)) {
+					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == TW($gt)) {
 						condition   = "unsigned X>~0";
 						replacement = "constant 0";
 						replace_sig[0] = State::S0;
 						replace = true;
 					}
-					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == ID($le)) {
+					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == TW($le)) {
 						condition   = "unsigned X<=~0";
 						replacement = "constant 1";
 						replace_sig[0] = State::S1;
@@ -2244,14 +2246,14 @@ skip_alu_split:
 							var_high_sig[i - const_bit_hot] = var_sig[i];
 						}
 
-						if (cmp_type == ID($lt))
+						if (cmp_type == TW($lt))
 						{
 							condition   = stringf("unsigned X<%s", log_signal(const_sig));
 							replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
 							replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_high_sig).as_bit();
 							replace = true;
 						}
-						if (cmp_type == ID($ge))
+						if (cmp_type == TW($ge))
 						{
 							condition   = stringf("unsigned X>=%s", log_signal(const_sig));
 							replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
@@ -2264,19 +2266,19 @@ skip_alu_split:
 					if (const_bit_set >= var_width)
 					{
 						string cmp_name;
-						if (cmp_type == ID($lt) || cmp_type == ID($le))
+						if (cmp_type == TW($lt) || cmp_type == TW($le))
 						{
-							if (cmp_type == ID($lt)) cmp_name = "<";
-							if (cmp_type == ID($le)) cmp_name = "<=";
+							if (cmp_type == TW($lt)) cmp_name = "<";
+							if (cmp_type == TW($le)) cmp_name = "<=";
 							condition   = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig));
 							replacement = "constant 1";
 							replace_sig[0] = State::S1;
 							replace = true;
 						}
-						if (cmp_type == ID($gt) || cmp_type == ID($ge))
+						if (cmp_type == TW($gt) || cmp_type == TW($ge))
 						{
-							if (cmp_type == ID($gt)) cmp_name = ">";
-							if (cmp_type == ID($ge)) cmp_name = ">=";
+							if (cmp_type == TW($gt)) cmp_name = ">";
+							if (cmp_type == TW($ge)) cmp_name = ">=";
 							condition   = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig));
 							replacement = "constant 0";
 							replace_sig[0] = State::S0;
@@ -2286,14 +2288,14 @@ skip_alu_split:
 				}
 				else
 				{ /* signed */
-					if (const_sig.is_fully_zero() && cmp_type == ID($lt))
+					if (const_sig.is_fully_zero() && cmp_type == TW($lt))
 					{
 						condition   = "signed X<0";
 						replacement = stringf("X[%d]", var_width - 1);
 						replace_sig[0] = var_sig[var_width - 1];
 						replace = true;
 					}
-					if (const_sig.is_fully_zero() && cmp_type == ID($ge))
+					if (const_sig.is_fully_zero() && cmp_type == TW($ge))
 					{
 						condition   = "signed X>=0";
 						replacement = stringf("X[%d]", var_width - 1);
diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc
index c74ad2a72..b98c874fa 100644
--- a/passes/opt/opt_ffinv.cc
+++ b/passes/opt/opt_ffinv.cc
@@ -52,9 +52,9 @@ struct OptFfInvWorker
 				continue;
 			if (port.port != TW::Y)
 				return false;
-			if (port.cell->type.in(ID($not), ID($_NOT_))) {
+			if (port.cell->type.in(TW($not), TW($_NOT_))) {
 				// OK
-			} else if (port.cell->type.in(ID($lut))) {
+			} else if (port.cell->type.in(TW($lut))) {
 				if (port.cell->getParam(ID::WIDTH) != 1)
 					return false;
 				if (port.cell->getParam(ID::LUT).as_int() != 1)
@@ -78,7 +78,7 @@ struct OptFfInvWorker
 				return false;
 			if (port.port != TW::A)
 				return false;
-			if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut)))
+			if (!port.cell->type.in(TW($not), TW($_NOT_), TW($lut)))
 				return false;
 			q_luts.insert(port.cell);
 		}
@@ -87,7 +87,7 @@ struct OptFfInvWorker
 		ff.sig_d = d_inv->getPort(TW::A);
 
 		for (Cell *lut: q_luts) {
-			if (lut->type == ID($lut)) {
+			if (lut->type == TW($lut)) {
 				int flip_mask = 0;
 				SigSpec sig_a = lut->getPort(TW::A);
 				for (int i = 0; i < GetSize(sig_a); i++) {
@@ -137,7 +137,7 @@ struct OptFfInvWorker
 				continue;
 			if (port.port != TW::Y)
 				return false;
-			if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut)))
+			if (!port.cell->type.in(TW($not), TW($_NOT_), TW($lut)))
 				return false;
 			log_assert(d_lut == nullptr);
 			d_lut = port.cell;
@@ -157,9 +157,9 @@ struct OptFfInvWorker
 				return false;
 			if (port.port != TW::A)
 				return false;
-			if (port.cell->type.in(ID($not), ID($_NOT_))) {
+			if (port.cell->type.in(TW($not), TW($_NOT_))) {
 				// OK
-			} else if (port.cell->type.in(ID($lut))) {
+			} else if (port.cell->type.in(TW($lut))) {
 				if (port.cell->getParam(ID::WIDTH) != 1)
 					return false;
 				if (port.cell->getParam(ID::LUT).as_int() != 1)
@@ -176,7 +176,7 @@ struct OptFfInvWorker
 		ff.sig_q = q_inv->getPort(TW::Y);
 		module->remove(q_inv);
 
-		if (d_lut->type == ID($lut)) {
+		if (d_lut->type == TW($lut)) {
 			Const mask = d_lut->getParam(ID::LUT);
 			Const::Builder new_mask_builder(GetSize(mask));
 			for (int i = 0; i < GetSize(mask); i++) {
diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc
index b53673695..011b93bf6 100644
--- a/passes/opt/opt_hier.cc
+++ b/passes/opt/opt_hier.cc
@@ -101,7 +101,7 @@ struct ModuleIndex {
 			if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
 				log_error("Port %s connected on instance %s not found in module %s"
 						  " or width is not matching\n",
-						  port_name.unescape(), instantiation, module);
+						  design->twines.unescaped_str(port_name), instantiation, module);
 			}
 
 			if (port->port_input && port->port_output) {
@@ -145,12 +145,12 @@ struct ModuleIndex {
 
 			if (nunused > 0) {
 				log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n",
-					nunused, instantiation, instantiation->type.unescape(), parent.module);
+					nunused, instantiation, design->twines.unescaped_str(instantiation->type), parent.module);
 				changed = true;
 			}
 			if (nconstants > 0) {
 				log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n",
-					nconstants, instantiation, instantiation->type.unescape(), parent.module);
+					nconstants, instantiation, design->twines.unescaped_str(instantiation->type), parent.module);
 				changed = true;
 			}
 		}
@@ -163,8 +163,8 @@ struct ModuleIndex {
 			SigSpec new_tie;
 
 			for (auto port_bit : class_) {
-				if (instantiation->connections_.count(port_bit.wire->name)) {
-					SigBit bit = instantiation->connections_.at(port_bit.wire->name)[port_bit.offset];
+				if (instantiation->connections_.count(port_bit.wire->meta_->name)) {
+					SigBit bit = instantiation->connections_.at(port_bit.wire->meta_->name)[port_bit.offset];
 					if (parent.used.check(bit)) {
 						if (!new_tie.empty()) {
 							severed_port_bits.append(port_bit);
@@ -181,7 +181,7 @@ struct ModuleIndex {
 
 		severed_port_bits.sort_and_unify();
 		for (auto chunk : severed_port_bits.chunks()) {
-			SigSpec &value = instantiation->connections_.at(chunk.wire->name);
+			SigSpec &value = instantiation->connections_.at(chunk.wire->meta_->name);
 			SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("tie_together"), chunk.width);
 			for (int i = 0; i < chunk.width; i++)
 				value[chunk.offset + i] = dummy[i];
@@ -189,7 +189,7 @@ struct ModuleIndex {
 
 		if (ntie_togethers > 0) {
 			log("Replacing %d output bits with tie-togethers on instance '%s' of '%s' in '%s'\n",
-				ntie_togethers, instantiation, instantiation->type.unescape(), parent.module);
+				ntie_togethers, instantiation, design->twines.unescaped_str(instantiation->type), parent.module);
 			changed = true;
 		}
 
@@ -290,7 +290,7 @@ struct UsageData {
 			if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
 				log_error("Port %s connected on instance %s not found in module %s"
 						  " or width is not matching\n",
-						  port_name.unescape(), instance, module);
+						module->design->twines.unescaped_str(port_name), instance, module);
 			}
 
 			if (port->port_input && port->port_output) {
@@ -338,7 +338,7 @@ struct UsageData {
 
 		dict<SigBit, SigBit> replacement_map;
 		for (auto chunk : disconnect_outputs.chunks()) {
-			Wire *repl_wire = module->addWire(module->uniquify(std::string("$") + chunk.wire->name.str()), chunk.size());
+			Wire *repl_wire = module->addWire(module->uniquify(Twine{std::string("$") + chunk.wire->name.str()}), chunk.size());
 			for (int i = 0; i < repl_wire->width; i++)
 				replacement_map[SigSpec(chunk)[i]] = SigBit(repl_wire, i);
 		}
@@ -454,7 +454,7 @@ struct OptHierPass : Pass {
 		for (auto module : d->modules()) {
 			for (auto cell : module->cells()) {
 				if (usage_datas.count(cell->type)) {
-					log_debug("Account for instance %s of %s in %s\n", cell, cell->type.unescape(), module);
+					log_debug("Account for instance %s of %s in %s\n", cell, cell->type.unescaped(), module);
 					usage_datas.at(cell->type).refine(cell, indices.at(module->name));
 				}
 			}
@@ -471,7 +471,7 @@ struct OptHierPass : Pass {
 
 			for (auto cell : module->cells()) {
 				if (indices.count(cell->type)) {
-					log_debug("Applying changes to instance %s of %s in %s\n", cell, cell->type.unescape(), module);
+					log_debug("Applying changes to instance %s of %s in %s\n", cell, cell->type.unescaped(), module);
 					did_something |= indices.at(cell->type).apply_changes(parent_index, cell);
 				}
 			}
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 27180a1d2..cb7f5ea66 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -109,7 +109,7 @@ struct OptLutWorker
 		log("Discovering LUTs.\n");
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type == ID($lut))
+			if (cell->type == TW($lut))
 			{
 				if (cell->has_keep_attr())
 					continue;
diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc
index 792c421bb..f5dbd1c6c 100644
--- a/passes/opt/opt_lut_ins.cc
+++ b/passes/opt/opt_lut_ins.cc
@@ -77,7 +77,7 @@ struct OptLutInsPass : public Pass {
 				std::vector<SigBit> output;
 				bool ignore_const = false;
 				if (techname == "") {
-					if (cell->type != ID($lut))
+					if (cell->type != TW($lut))
 						continue;
 					inputs = cell->getPort(TW::A);
 					output = cell->getPort(TW::Y);
diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc
index 0bd97f5f9..45b3adc7d 100644
--- a/passes/opt/opt_mem.cc
+++ b/passes/opt/opt_mem.cc
@@ -108,13 +108,13 @@ struct OptMemPass : public Pass {
 					}
 					State bit;
 					if (!always_0[i]) {
-						log("%s.%s: removing const-1 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
+						log("%s.%s: removing const-1 lane %d\n", design->twines.unescaped_str(module->name), design->twines.unescaped_str(mem.memid), i);
 						bit = State::S1;
 					} else if (!always_1[i]) {
-						log("%s.%s: removing const-0 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
+						log("%s.%s: removing const-0 lane %d\n", design->twines.unescaped_str(module->name), design->twines.unescaped_str(mem.memid), i);
 						bit = State::S0;
 					} else {
-						log("%s.%s: removing const-x lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
+						log("%s.%s: removing const-x lane %d\n", design->twines.unescaped_str(module->name), design->twines.unescaped_str(mem.memid), i);
 						bit = State::Sx;
 					}
 					// Reconnect read port data.
diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc
index a41f7e2e5..88e752ba1 100644
--- a/passes/opt/opt_mem_feedback.cc
+++ b/passes/opt/opt_mem_feedback.cc
@@ -163,7 +163,7 @@ struct OptMemFeedbackWorker
 		{
 			auto &port = mem.wr_ports[i];
 
-			log("  Analyzing %s.%s write port %d.\n", module, mem.memid.unescape(), i);
+			log("  Analyzing %s.%s write port %d.\n", module, design->twines.unescaped_str(mem.memid), i);
 
 			for (int sub = 0; sub < (1 << port.wide_log2); sub++)
 			{
@@ -232,7 +232,7 @@ struct OptMemFeedbackWorker
 
 		// Okay, let's do it.
 
-		log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, mem.memid.unescape());
+		log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, design->twines.unescaped_str(mem.memid));
 
 		// If a write port has a feedback path that we're about to bypass,
 		// but also has priority over some other write port, the feedback
@@ -293,7 +293,7 @@ struct OptMemFeedbackWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 			{
 				RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
 				RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
@@ -304,7 +304,7 @@ struct OptMemFeedbackWorker
 					sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
 			}
 
-			if (cell->type.in(ID($mux), ID($pmux)))
+			if (cell->type.in(TW($mux), TW($pmux)))
 			{
 				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(TW::Y));
 				for (int i = 0; i < int(sig_y.size()); i++)
diff --git a/passes/opt/opt_mem_widen.cc b/passes/opt/opt_mem_widen.cc
index b7bc748c4..ff9158ae5 100644
--- a/passes/opt/opt_mem_widen.cc
+++ b/passes/opt/opt_mem_widen.cc
@@ -65,7 +65,7 @@ struct OptMemWidenPass : public Pass {
 						factor_log2 = port.wide_log2;
 				if (factor_log2 == 0)
 					continue;
-				log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), design->twines.str(module->meta_->name).c_str(), 1 << factor_log2);
+				log("Widening base width of memory %s in module %s by factor %d.\n", design->twines.unescaped_str(mem.memid), design->twines.str(module->meta_->name).c_str(), 1 << factor_log2);
 				total_count++;
 				// The inits are too messy to expand one-by-one, for they may
 				// collide with one another after expansion.  Just hit it with
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index da123d5ca..2d51312ae 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -121,18 +121,18 @@ struct OptMergeThreadWorker : public CellHasher
 			const RTLIL::Cell *cell = module->cell_at(cell_index);
 			if (!module->selected(cell))
 				continue;
-			if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
+			if (cell->type.in(TW($meminit), TW($meminit_v2), TW($mem), TW($mem_v2))) {
 				// Ignore those for performance: meminit can have an excessively large port,
 				// mem can have an excessively large parameter holding the init data
 				continue;
 			}
-			if (cell->type == ID($scopeinfo))
+			if (cell->type == TW($scopeinfo))
 				continue;
 			if (mode_keepdc && has_dont_care_initval(cell))
 				continue;
 			if (!cell->known())
 				continue;
-			if (!mode_share_all && !ct.cell_known(cell->type))
+			if (!mode_share_all && !ct.cell_known(cell->type_impl))
 				continue;
 
 			Hasher::hash_t h = hash_cell_function(cell, Hasher()).yield();
@@ -397,20 +397,20 @@ struct OptMergePass : public Pass {
 		ct.setup_stdcells();
 		ct.setup_stdcells_mem();
 		if (mode_nomux) {
-			ct.cell_types.erase(ID($mux));
-			ct.cell_types.erase(ID($pmux));
+			ct.cell_types.erase(TW($mux));
+			ct.cell_types.erase(TW($pmux));
 		}
-		ct.cell_types.erase(ID($tribuf));
-		ct.cell_types.erase(ID($_TBUF_));
-		ct.cell_types.erase(ID($anyseq));
-		ct.cell_types.erase(ID($anyconst));
-		ct.cell_types.erase(ID($allseq));
-		ct.cell_types.erase(ID($allconst));
+		ct.cell_types.erase(TW($tribuf));
+		ct.cell_types.erase(TW($_TBUF_));
+		ct.cell_types.erase(TW($anyseq));
+		ct.cell_types.erase(TW($anyconst));
+		ct.cell_types.erase(TW($allseq));
+		ct.cell_types.erase(TW($allconst));
 		// Synthetic driver cells signorm creates for module ports — must
 		// never be folded into one another, otherwise distinct ports collapse.
-		ct.cell_types.erase(ID($input_port));
-		ct.cell_types.erase(ID($output_port));
-		ct.cell_types.erase(ID($public));
+		ct.cell_types.erase(TW($input_port));
+		ct.cell_types.erase(TW($output_port));
+		ct.cell_types.erase(TW($public));
 
 		// patcher.patch uses connect_incremental + fanout queries.
 		design->sigNormalize(true);
diff --git a/passes/opt/opt_merge_common.h b/passes/opt/opt_merge_common.h
index 3e6975994..d7903f943 100644
--- a/passes/opt/opt_merge_common.h
+++ b/passes/opt/opt_merge_common.h
@@ -91,21 +91,21 @@ struct CellHasher
 	{
 		// TODO: when implemented, use celltypes to match:
 		// (builtin || stdcell) && (unary || binary) && symmetrical
-		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
-				ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
+		if (cell->type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($add), TW($mul),
+				TW($logic_and), TW($logic_or), TW($_AND_), TW($_OR_), TW($_XOR_))) {
 			hashlib::commutative_hash comm;
 			comm.eat(map_sig(cell->getPort(TW::A)));
 			comm.eat(map_sig(cell->getPort(TW::B)));
 			h = comm.hash_into(h);
-		} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+		} else if (cell->type.in(TW($reduce_xor), TW($reduce_xnor))) {
 			SigSpec a = map_sig(cell->getPort(TW::A));
 			a.sort();
 			h = a.hash_into(h);
-		} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
+		} else if (cell->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool))) {
 			SigSpec a = map_sig(cell->getPort(TW::A));
 			a.sort_and_unify();
 			h = a.hash_into(h);
-		} else if (cell->type == ID($pmux)) {
+		} else if (cell->type == TW($pmux)) {
 			SigSpec sig_s = map_sig(cell->getPort(TW::S));
 			SigSpec sig_b = map_sig(cell->getPort(TW::B));
 			h = hash_pmux_in(sig_s, sig_b, h);
@@ -177,8 +177,8 @@ struct CellHasher
 			}
 		}
 
-		if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
-				ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
+		if (cell1->type.in(TW($and), TW($or), TW($xor), TW($xnor), TW($add), TW($mul),
+				TW($logic_and), TW($logic_or), TW($_AND_), TW($_OR_), TW($_XOR_))) {
 			if (conn1.at(TW::A) < conn1.at(TW::B)) {
 				std::swap(conn1[TW::A], conn1[TW::B]);
 			}
@@ -186,15 +186,15 @@ struct CellHasher
 				std::swap(conn2[TW::A], conn2[TW::B]);
 			}
 		} else
-		if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+		if (cell1->type.in(TW($reduce_xor), TW($reduce_xnor))) {
 			conn1[TW::A].sort();
 			conn2[TW::A].sort();
 		} else
-		if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
+		if (cell1->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_bool))) {
 			conn1[TW::A].sort_and_unify();
 			conn2[TW::A].sort_and_unify();
 		} else
-		if (cell1->type == ID($pmux)) {
+		if (cell1->type == TW($pmux)) {
 			sort_pmux_conn(conn1);
 			sort_pmux_conn(conn2);
 		}
diff --git a/passes/opt/opt_merge_inc.cc b/passes/opt/opt_merge_inc.cc
index 932b88dc9..6ec0f47d5 100644
--- a/passes/opt/opt_merge_inc.cc
+++ b/passes/opt/opt_merge_inc.cc
@@ -44,20 +44,20 @@ using MergeableTypes = StaticCellTypes::Categories::Category;
 // is intentionally not included, so $anyinit stays excluded
 static constexpr MergeableTypes build_mergeable_types(bool nomux) {
 	auto c = StaticCellTypes::categories.is_known;
-	c.set_id(ID($anyinit), false);
-	c.set_id(ID($tribuf), false);
-	c.set_id(ID($_TBUF_), false);
-	c.set_id(ID($anyseq), false);
-	c.set_id(ID($anyconst), false);
-	c.set_id(ID($allseq), false);
-	c.set_id(ID($allconst), false);
-	c.set_id(ID($connect), false);
-	c.set_id(ID($input_port), false);
-	c.set_id(ID($output_port), false);
-	c.set_id(ID($public), false);
+	c.set_id(TW($anyinit), false);
+	c.set_id(TW($tribuf), false);
+	c.set_id(TW($_TBUF_), false);
+	c.set_id(TW($anyseq), false);
+	c.set_id(TW($anyconst), false);
+	c.set_id(TW($allseq), false);
+	c.set_id(TW($allconst), false);
+	c.set_id(TW($connect), false);
+	c.set_id(TW($input_port), false);
+	c.set_id(TW($output_port), false);
+	c.set_id(TW($public), false);
 	if (nomux) {
-		c.set_id(ID($mux), false);
-		c.set_id(ID($pmux), false);
+		c.set_id(TW($mux), false);
+		c.set_id(TW($pmux), false);
 	}
 	return c;
 }
@@ -161,18 +161,18 @@ struct OptMergeIncWorker
 				for (auto cell : module->cells()) {
 					if (!design->selected(module, cell))
 						continue;
-					if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
+					if (cell->type.in(TW($meminit), TW($meminit_v2), TW($mem), TW($mem_v2))) {
 						// Ignore those for performance: meminit can have an excessively large port,
 						// mem can have an excessively large parameter holding the init data
 						continue;
 					}
-					if (cell->type == ID($scopeinfo))
+					if (cell->type == TW($scopeinfo))
 						continue;
 					if (mode_keepdc && hasher.has_dont_care_initval(cell))
 						continue;
 					if (!cell->known())
 						continue;
-					if (!mode_share_all && !ct(cell->type))
+					if (!mode_share_all && !ct(cell->type_impl))
 						continue;
 
 					cells.push_back(cell);
@@ -190,18 +190,18 @@ struct OptMergeIncWorker
 				for (auto cell : module->dirty_cells(timestamp)) {
 					if (!design->selected(module, cell))
 						continue;
-					if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
+					if (cell->type.in(TW($meminit), TW($meminit_v2), TW($mem), TW($mem_v2))) {
 						// Ignore those for performance: meminit can have an excessively large port,
 						// mem can have an excessively large parameter holding the init data
 						continue;
 					}
-					if (cell->type == ID($scopeinfo))
+					if (cell->type == TW($scopeinfo))
 						continue;
 					if (mode_keepdc && hasher.has_dont_care_initval(cell))
 						continue;
 					if (!cell->known())
 						continue;
-					if (!mode_share_all && !ct(cell->type))
+					if (!mode_share_all && !ct(cell->type_impl))
 						continue;
 
 
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index e4f1c547d..96bbfabf8 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -232,7 +232,7 @@ struct OptMuxtreeWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($mux), ID($pmux)))
+			if (cell->type.in(TW($mux), TW($pmux)))
 				track_mux(cell);
 			else
 				see_non_mux_cell(cell);
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 5a4a4e671..2b17a6c46 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -50,7 +50,7 @@ struct OptReduceWorker
 		for (auto &bit : sig_a)
 		{
 			if (bit == RTLIL::State::S0) {
-				if (cell->type == ID($reduce_and)) {
+				if (cell->type == TW($reduce_and)) {
 					new_sig_a_bits.clear();
 					new_sig_a_bits.insert(RTLIL::State::S0);
 					break;
@@ -58,7 +58,7 @@ struct OptReduceWorker
 				continue;
 			}
 			if (bit == RTLIL::State::S1) {
-				if (cell->type == ID($reduce_or)) {
+				if (cell->type == TW($reduce_or)) {
 					new_sig_a_bits.clear();
 					new_sig_a_bits.insert(RTLIL::State::S1);
 					break;
@@ -90,7 +90,7 @@ struct OptReduceWorker
 		new_sig_a.sort_and_unify();
 
 		if (GetSize(new_sig_a) == 0)
-			new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
+			new_sig_a = (cell->type == TW($reduce_or)) ? State::S0 : State::S1;
 
 		if (new_sig_a != sig_a || sig_a.size() != cell->getPort(TW::A).size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
@@ -126,7 +126,7 @@ struct OptReduceWorker
 			RTLIL::SigSpec this_s{this_s_bit};
 			if (this_s.size() > 1)
 			{
-				RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
+				RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
 				reduce_or_cell->setPort(TW::A, this_s);
 				reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
 				reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
@@ -151,7 +151,7 @@ struct OptReduceWorker
 			return;
 		}
 
-		if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {
+		if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == TW($pmux))) {
 			log("    New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
 			did_something = true;
 			total_count++;
@@ -338,7 +338,7 @@ struct OptReduceWorker
 		SigSpec sig_y = assign_map(cell->getPort(TW::Y));
 		int width = GetSize(sig_y);
 
-		if (cell->type != ID($bmux))
+		if (cell->type != TW($bmux))
 			sig_b = assign_map(cell->getPort(TW::B));
 
 		RTLIL::SigSig old_sig_conn;
@@ -386,7 +386,7 @@ struct OptReduceWorker
 		if (GetSize(swizzle) != width)
 		{
 			log("    Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
-			if (cell->type != ID($bmux)) {
+			if (cell->type != TW($bmux)) {
 				log("      Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
 						log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
 			} else {
@@ -403,7 +403,7 @@ struct OptReduceWorker
 						new_sig_a.append(sig_a[i+j]);
 				cell->setPort(TW::A, new_sig_a);
 
-				if (cell->type != ID($bmux)) {
+				if (cell->type != TW($bmux)) {
 					SigSpec new_sig_b;
 					for (int i = 0; i < GetSize(sig_b); i += width)
 						for (int j: swizzle)
@@ -418,7 +418,7 @@ struct OptReduceWorker
 
 				cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
 
-				if (cell->type != ID($bmux)) {
+				if (cell->type != TW($bmux)) {
 					log("      New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
 							log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
 				} else {
@@ -520,14 +520,14 @@ struct OptReduceWorker
 		SigPool mem_wren_sigs;
 		for (auto &cell_it : module->cells_) {
 			RTLIL::Cell *cell = cell_it.second;
-			if (cell->type.in(ID($mem), ID($mem_v2)))
+			if (cell->type.in(TW($mem), TW($mem_v2)))
 				mem_wren_sigs.add(assign_map(cell->getPort(TW::WR_EN)));
-			if (cell->type.in(ID($memwr), ID($memwr_v2)))
+			if (cell->type.in(TW($memwr), TW($memwr_v2)))
 				mem_wren_sigs.add(assign_map(cell->getPort(TW::EN)));
 		}
 		for (auto &cell_it : module->cells_) {
 			RTLIL::Cell *cell = cell_it.second;
-			if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
+			if (cell->type == TW($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
 				mem_wren_sigs.add(assign_map(cell->getPort(TW::D)));
 		}
 
@@ -536,7 +536,7 @@ struct OptReduceWorker
 			keep_expanding_mem_wren_sigs = false;
 			for (auto &cell_it : module->cells_) {
 				RTLIL::Cell *cell = cell_it.second;
-				if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
+				if (cell->type == TW($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
 					if (!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::A))) ||
 							!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::B))))
 						keep_expanding_mem_wren_sigs = true;
@@ -553,7 +553,7 @@ struct OptReduceWorker
 			// merge trees of reduce_* cells to one single cell and unify input vectors
 			// (only handle reduce_and and reduce_or for various reasons)
 
-			const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
+			const IdString type_list[] = { TW($reduce_or), TW($reduce_and) };
 			for (auto type : type_list)
 			{
 				SigSet<RTLIL::Cell*> drivers;
@@ -577,13 +577,13 @@ struct OptReduceWorker
 
 			for (auto cell : module->selected_cells())
 			{
-				if (!cell->type.in(ID($mux), ID($pmux), ID($bmux), ID($demux)))
+				if (!cell->type.in(TW($mux), TW($pmux), TW($bmux), TW($demux)))
 					continue;
 
 				// this optimization is to aggressive for most coarse-grain applications.
 				// but we always want it for multiplexers driving write enable ports.
 				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
-					if (cell->type == ID($demux)) {
+					if (cell->type == TW($demux)) {
 						if (opt_demux_bits(cell))
 							continue;
 					} else {
@@ -592,11 +592,11 @@ struct OptReduceWorker
 					}
 				}
 
-				if (cell->type.in(ID($mux), ID($pmux)))
+				if (cell->type.in(TW($mux), TW($pmux)))
 					opt_pmux(cell);
-				else if (cell->type == ID($bmux))
+				else if (cell->type == TW($bmux))
 					opt_bmux(cell);
-				else if (cell->type == ID($demux))
+				else if (cell->type == TW($demux))
 					opt_demux(cell);
 			}
 		}
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index af5eb9844..a8cfc9040 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -81,27 +81,27 @@ struct ExtSigSpec {
 	bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; }
 };
 
-#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)
+#define FINE_BITWISE_OPS TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)
 
-#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor)
+#define BITWISE_OPS FINE_BITWISE_OPS, TW($and), TW($or), TW($xor), TW($xnor)
 
-#define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand)
+#define REDUCTION_OPS TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($reduce_nand)
 
-#define LOGICAL_OPS ID($logic_and), ID($logic_or)
+#define LOGICAL_OPS TW($logic_and), TW($logic_or)
 
-#define SHIFT_OPS ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)
+#define SHIFT_OPS TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)
 
-#define RELATIONAL_OPS ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)
+#define RELATIONAL_OPS TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt)
 
 bool cell_supported(RTLIL::Cell *cell)
 {
-	if (cell->type.in(ID($alu))) {
+	if (cell->type.in(TW($alu))) {
 		RTLIL::SigSpec sig_bi = cell->getPort(TW::BI);
 		RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
 
 		if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
 			return true;
-	} else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat))) {
+	} else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($concat))) {
 		return true;
 	}
 
@@ -113,7 +113,7 @@ std::map<IdString, IdString> mergeable_type_map;
 bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
 {
 	if (mergeable_type_map.empty()) {
-		mergeable_type_map.insert({ID($sub), ID($add)});
+		mergeable_type_map.insert({TW($sub), TW($add)});
 	}
 	auto a_type = a->type;
 	if (mergeable_type_map.count(a_type))
@@ -128,10 +128,10 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
 
 TwineRef decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name)
 {
-	if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == TW::B)
+	if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($concat), SHIFT_OPS) && port_name == TW::B)
 		return port_name;
 
-	if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+	if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
 		return port_name;
 
 	return Twine::Null;
@@ -139,9 +139,9 @@ TwineRef decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name)
 
 RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, TwineRef port_name) {
 
-	if (cell->type == ID($alu) && port_name == TW::B)
+	if (cell->type == TW($alu) && port_name == TW::B)
 		return cell->getPort(TW::BI);
-	else if (cell->type == ID($sub) && port_name == TW::B)
+	else if (cell->type == TW($sub) && port_name == TW::B)
 		return RTLIL::Const(1, 1);
 
 	return RTLIL::Const(0, 1);
@@ -247,7 +247,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 		mux_to_oper = module->Pmux(NEW_TWINE, shared_pmux_a, shared_pmux_b, shared_pmux_s);
 	}
 
-	if (shared_op->type.in(ID($alu))) {
+	if (shared_op->type.in(TW($alu))) {
 		shared_op->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(new_out)));
 		shared_op->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(new_out)));
 	}
@@ -365,7 +365,7 @@ struct OptSharePass : public Pass {
 			dict<RTLIL::SigBit, int> bit_users;
 
 			for (auto cell : module->cells()) {
-				if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+				if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 					continue;
 				for (auto conn : cell->connections())
 					for (auto bit : conn.second)
@@ -386,7 +386,7 @@ struct OptSharePass : public Pass {
 					continue;
 
 				bool skip = false;
-				if (cell->type == ID($alu)) {
+				if (cell->type == TW($alu)) {
 					for (TwineRef port_name : {TW::X, TW::CO}) {
 						for (auto outbit : sigmap(cell->getPort(port_name)))
 							if (bit_users[outbit] > 1)
@@ -417,7 +417,7 @@ struct OptSharePass : public Pass {
 			std::vector<merged_op_t> merged_ops;
 
 			for (auto mux : module->selected_cells()) {
-				if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux)))
+				if (!mux->type.in(TW($mux), TW($_MUX_), TW($pmux)))
 					continue;
 
 				int mux_port_size = GetSize(mux->getPort(TW::A));
@@ -564,7 +564,7 @@ struct OptSharePass : public Pass {
 				log("    Found cells that share an operand and can be merged by moving the %s %s in front "
 				    "of "
 				    "them:\n",
-				    shared.mux->type.unescape(), shared.mux);
+				    design->twines.unescaped_str(shared.mux->type), shared.mux);
 				for (const auto& op : shared.ports)
 					log("        %s\n", op.op);
 				log("\n");
diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index b4b1724ae..5f308b21d 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -54,17 +54,17 @@ struct OnehotDatabase
 			vector<SigSpec> inputs;
 			SigSpec output;
 
-			if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
+			if (cell->type.in(TW($adff), TW($adffe), TW($dff), TW($dffe), TW($sdff), TW($sdffe), TW($sdffce), TW($dlatch), TW($adlatch), TW($ff)))
 			{
 				output = cell->getPort(TW::Q);
-				if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
+				if (cell->type.in(TW($adff), TW($adffe), TW($adlatch)))
 					inputs.push_back(cell->getParam(ID::ARST_VALUE));
-				if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+				if (cell->type.in(TW($sdff), TW($sdffe), TW($sdffce)))
 					inputs.push_back(cell->getParam(ID::SRST_VALUE));
 				inputs.push_back(cell->getPort(TW::D));
 			}
 
-			if (cell->type.in(ID($mux), ID($pmux)))
+			if (cell->type.in(TW($mux), TW($pmux)))
 			{
 				output = cell->getPort(TW::Y);
 				inputs.push_back(cell->getPort(TW::A));
@@ -285,7 +285,7 @@ struct Pmux2ShiftxPass : public Pass {
 
 			for (auto cell : module->cells())
 			{
-				if (cell->type == ID($eq))
+				if (cell->type == TW($eq))
 				{
 					dict<SigBit, State> bits;
 
@@ -333,7 +333,7 @@ struct Pmux2ShiftxPass : public Pass {
 					goto next_cell;
 				}
 
-				if (cell->type == ID($logic_not))
+				if (cell->type == TW($logic_not))
 				{
 					dict<SigBit, State> bits;
 
@@ -359,10 +359,10 @@ struct Pmux2ShiftxPass : public Pass {
 
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type != ID($pmux))
+				if (cell->type != TW($pmux))
 					continue;
 
-				string src = cell->get_src_attribute();
+				TwineRef src = cell->meta_->src;
 				int width = cell->getParam(ID::WIDTH).as_int();
 				int width_bits = ceil_log2(width);
 				int extwidth = width;
@@ -777,7 +777,7 @@ struct OnehotPass : public Pass {
 
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type != ID($eq))
+				if (cell->type != TW($eq))
 					continue;
 
 				SigSpec A = sigmap(cell->getPort(TW::A));
@@ -851,7 +851,7 @@ struct OnehotPass : public Pass {
 				}
 
 				RTLIL::Patch patcher(module, &sigmap);
-				patcher.patch(cell, ID::Y, replacement);
+				patcher.patch(cell, TW::Y, replacement);
 			}
 		}
 	}
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index fc39ea6d8..580c181a6 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -74,7 +74,7 @@ struct ShareWorker
 		queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
 
 		for (auto &it : module->cells_)
-			if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type)) {
+			if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type_impl)) {
 				pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
 				queue_bits.insert(bits.begin(), bits.end());
 			}
@@ -88,13 +88,13 @@ struct ShareWorker
 			queue_bits.clear();
 
 			for (auto &pbit : portbits) {
-				if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && visited_cells.count(pbit.cell) == 0) {
+				if ((pbit.cell->type == TW($mux) || pbit.cell->type == TW($pmux)) && visited_cells.count(pbit.cell) == 0) {
 					pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(TW::S)).to_sigbit_pool();
 					terminal_bits.insert(bits.begin(), bits.end());
 					queue_bits.insert(bits.begin(), bits.end());
 					visited_cells.insert(pbit.cell);
 				}
-				if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
+				if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type_impl) && visited_cells.count(pbit.cell) == 0) {
 					pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
 					terminal_bits.insert(bits.begin(), bits.end());
 					queue_bits.insert(bits.begin(), bits.end());
@@ -351,7 +351,7 @@ struct ShareWorker
 	{
 		for (auto cell : module->cells())
 		{
-			if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type))
+			if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type_impl))
 				continue;
 
 			for (auto &bit : modwalker.cell_outputs[cell])
@@ -362,7 +362,7 @@ struct ShareWorker
 		not_a_muxed_cell:
 				continue;
 
-			if (cell->type.in(ID($memrd), ID($memrd_v2))) {
+			if (cell->type.in(TW($memrd), TW($memrd_v2))) {
 				if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
 					continue;
 				if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(TW::ADDR)).is_fully_const())
@@ -370,19 +370,19 @@ struct ShareWorker
 				continue;
 			}
 
-			if (cell->type.in(ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+			if (cell->type.in(TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 				if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4)
 					shareable_cells.insert(cell);
 				continue;
 			}
 
-			if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
+			if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr))) {
 				if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 8)
 					shareable_cells.insert(cell);
 				continue;
 			}
 
-			if (generic_ops(cell->type)) {
+			if (generic_ops(cell->type_impl)) {
 				if (config.opt_aggressive)
 					shareable_cells.insert(cell);
 				continue;
@@ -395,7 +395,7 @@ struct ShareWorker
 		if (c1->type != c2->type)
 			return false;
 
-		if (c1->type.in(ID($memrd), ID($memrd_v2)))
+		if (c1->type.in(TW($memrd), TW($memrd_v2)))
 		{
 			if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string())
 				return false;
@@ -406,7 +406,7 @@ struct ShareWorker
 			return true;
 		}
 
-		if (config.generic_uni_ops(c1->type))
+		if (config.generic_uni_ops(c1->type_impl))
 		{
 			if (!config.opt_aggressive)
 			{
@@ -423,7 +423,7 @@ struct ShareWorker
 			return true;
 		}
 
-		if (config.generic_bin_ops(c1->type) || c1->type == ID($alu))
+		if (config.generic_bin_ops(c1->type_impl) || c1->type == TW($alu))
 		{
 			if (!config.opt_aggressive)
 			{
@@ -443,7 +443,7 @@ struct ShareWorker
 			return true;
 		}
 
-		if (config.generic_cbin_ops(c1->type))
+		if (config.generic_cbin_ops(c1->type_impl))
 		{
 			if (!config.opt_aggressive)
 			{
@@ -469,7 +469,7 @@ struct ShareWorker
 			return true;
 		}
 
-		if (c1->type == ID($macc))
+		if (c1->type == TW($macc))
 		{
 			if (!config.opt_aggressive)
 				if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false;
@@ -505,7 +505,7 @@ struct ShareWorker
 	{
 		log_assert(c1->type == c2->type);
 
-		if (config.generic_uni_ops(c1->type))
+		if (config.generic_uni_ops(c1->type_impl))
 		{
 			if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
 			{
@@ -540,7 +540,7 @@ struct ShareWorker
 
 			RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
 
-			RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
+			RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
 			supercell->parameters[ID::A_SIGNED] = a_signed;
 			supercell->parameters[ID::A_WIDTH] = a_width;
 			supercell->parameters[ID::Y_WIDTH] = y_width;
@@ -554,11 +554,11 @@ struct ShareWorker
 			return supercell;
 		}
 
-		if (config.generic_bin_ops(c1->type) || config.generic_cbin_ops(c1->type) || c1->type == ID($alu))
+		if (config.generic_bin_ops(c1->type_impl) || config.generic_cbin_ops(c1->type_impl) || c1->type_impl == TW($alu))
 		{
 			bool modified_src_cells = false;
 
-			if (config.generic_cbin_ops(c1->type))
+			if (config.generic_cbin_ops(c1->type_impl))
 			{
 				int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
 						max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
@@ -616,7 +616,7 @@ struct ShareWorker
 			log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
 			log_assert(b_signed == c2->parameters.at(ID::B_SIGNED).as_bool());
 
-			if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
+			if (c1->type == TW($shl) || c1->type == TW($shr) || c1->type == TW($sshl) || c1->type == TW($sshr))
 				b_signed = false;
 
 			RTLIL::SigSpec a1 = c1->getPort(TW::A);
@@ -631,7 +631,7 @@ struct ShareWorker
 			int b_width = max(b1.size(), b2.size());
 			int y_width = max(y1.size(), y2.size());
 
-			if (c1->type == ID($shr) && a_signed)
+			if (c1->type == TW($shr) && a_signed)
 			{
 				a_width = max(y_width, a_width);
 
@@ -657,10 +657,10 @@ struct ShareWorker
 			supercell_aux.insert(module->addMux(NEW_TWINE, b2, b1, act, b));
 
 			RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
-			RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
-			RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
+			RTLIL::Wire *x = c1->type == TW($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
+			RTLIL::Wire *co = c1->type == TW($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
 
-			RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
+			RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
 			supercell->parameters[ID::A_SIGNED] = a_signed;
 			supercell->parameters[ID::B_SIGNED] = b_signed;
 			supercell->parameters[ID::A_WIDTH] = a_width;
@@ -669,7 +669,7 @@ struct ShareWorker
 			supercell->setPort(TW::A, a);
 			supercell->setPort(TW::B, b);
 			supercell->setPort(TW::Y, y);
-			if (c1->type == ID($alu)) {
+			if (c1->type == TW($alu)) {
 				RTLIL::Wire *ci = module->addWire(NEW_TWINE), *bi = module->addWire(NEW_TWINE);
 				supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci));
 				supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi));
@@ -682,7 +682,7 @@ struct ShareWorker
 
 			supercell_aux.insert(module->addPos(NEW_TWINE, y, y1));
 			supercell_aux.insert(module->addPos(NEW_TWINE, y, y2));
-			if (c1->type == ID($alu)) {
+			if (c1->type == TW($alu)) {
 				supercell_aux.insert(module->addPos(NEW_TWINE, co, c1->getPort(TW::CO)));
 				supercell_aux.insert(module->addPos(NEW_TWINE, co, c2->getPort(TW::CO)));
 				supercell_aux.insert(module->addPos(NEW_TWINE, x, c1->getPort(TW::X)));
@@ -693,16 +693,16 @@ struct ShareWorker
 			return supercell;
 		}
 
-		if (c1->type == ID($macc))
+		if (c1->type == TW($macc))
 		{
-			RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
+			RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
 			supercell_aux.insert(supercell);
 			share_macc(c1, c2, act, supercell, &supercell_aux);
 			supercell->check();
 			return supercell;
 		}
 
-		if (c1->type.in(ID($memrd), ID($memrd_v2)))
+		if (c1->type.in(TW($memrd), TW($memrd_v2)))
 		{
 			RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1);
 			RTLIL::SigSpec addr1 = c1->getPort(TW::ADDR);
@@ -744,7 +744,7 @@ struct ShareWorker
 		modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
 
 		for (auto &bit : pbits) {
-			if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == TW::S)
+			if ((bit.cell->type == TW($mux) || bit.cell->type == TW($pmux)) && bit.port == TW::S)
 				forbidden_controls_cache[cell].insert(bit.cell->getPort(TW::S).extract(bit.offset, 1));
 			consumer_cells.insert(bit.cell);
 		}
@@ -752,7 +752,7 @@ struct ShareWorker
 		recursion_state.insert(cell);
 
 		for (auto c : consumer_cells)
-			if (StaticCellTypes::Compat::internals_nomem_noff(c->type)) {
+			if (StaticCellTypes::Compat::internals_nomem_noff(c->type_impl)) {
 				const pool<RTLIL::SigBit> &bits = find_forbidden_controls(c);
 				forbidden_controls_cache[cell].insert(bits.begin(), bits.end());
 			}
@@ -891,8 +891,8 @@ struct ShareWorker
 				return activation_patterns_cache.at(cell);
 			}
 			for (auto &pbit : modwalker.signal_consumers[bit]) {
-				log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type));
-				if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == TW::A || pbit.port == TW::B))
+				log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type_impl));
+				if ((pbit.cell->type == TW($mux) || pbit.cell->type == TW($pmux)) && (pbit.port == TW::A || pbit.port == TW::B))
 					driven_data_muxes.insert(pbit.cell);
 				else
 					driven_cells.insert(pbit.cell);
@@ -1095,9 +1095,9 @@ struct ShareWorker
 		dict<RTLIL::SigBit, pool<RTLIL::Cell*>> bit_to_cells;
 
 		for (auto cell : module->cells())
-			if (ct.cell_known(cell->type))
+			if (ct.cell_known(cell->type_impl))
 				for (auto &conn : cell->connections()) {
-					if (ct.cell_output(cell->type, conn.first))
+					if (ct.cell_output(cell->type_impl, conn.first))
 						for (auto bit : topo_sigmap(conn.second)) {
 							cell_to_bits[cell].insert(bit);
 							topo_bit_drivers[bit].insert(cell);
@@ -1123,7 +1123,7 @@ struct ShareWorker
 			for (auto &loop : toposort.loops) {
 				log("### loop ###\n");
 				for (auto &c : loop)
-					log("%s (%s)\n", c, c->type.unescape());
+					log("%s (%s)\n", c, design->twines.unescaped_str(c->type));
 			}
 
 		return found_scc;
@@ -1167,13 +1167,13 @@ struct ShareWorker
 			pool<RTLIL::Cell*> new_queue;
 
 			for (auto c : queue) {
-				if (!ct.cell_known(c->type))
+				if (!ct.cell_known(c->type_impl))
 					continue;
 				for (auto &conn : c->connections())
-					if (ct.cell_input(c->type, conn.first))
+					if (ct.cell_input(c->type_impl, conn.first))
 						for (auto bit : conn.second)
 							for (auto &pi : mi.query_ports(bit))
-								if (ct.cell_known(pi.cell->type) && ct.cell_output(pi.cell->type, pi.port))
+								if (ct.cell_known(pi.cell->type_impl) && ct.cell_output(pi.cell->type_impl, pi.port))
 									new_queue.insert(pi.cell);
 				covered.insert(c);
 			}
@@ -1247,7 +1247,7 @@ struct ShareWorker
 			RTLIL::Cell *cell = *shareable_cells.begin();
 			shareable_cells.erase(cell);
 
-			log("  Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescape());
+			log("  Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescaped());
 
 			const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, "    ");
 			RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
@@ -1280,7 +1280,7 @@ struct ShareWorker
 
 			for (auto other_cell : candidates)
 			{
-				log("    Analyzing resource sharing with %s (%s):\n", other_cell, other_cell->type.unescape());
+				log("    Analyzing resource sharing with %s (%s):\n", other_cell, design->twines.unescaped_str(other_cell->type));
 
 				const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, "      ");
 				RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
@@ -1431,7 +1431,7 @@ struct ShareWorker
 					log("      Activation signal for %s: %s\n", other_cell, log_signal(act));
 				}
 
-				log("      New cell: %s (%s)\n", supercell, supercell->type.unescape());
+				log("      New cell: %s (%s)\n", supercell, design->twines.unescaped_str(supercell->type));
 
 				cells_to_remove.insert(cell);
 				cells_to_remove.insert(other_cell);
@@ -1478,7 +1478,7 @@ struct ShareWorker
 		if (!cells_to_remove.empty()) {
 			log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), module);
 			for (auto c : cells_to_remove) {
-				log("  Removing cell %s (%s).\n", c, c->type.unescape());
+				log("  Removing cell %s (%s).\n", c, design->twines.unescaped_str(c->type));
 				remove_cell(c);
 			}
 		}
@@ -1532,45 +1532,45 @@ struct SharePass : public Pass {
 		config.opt_aggressive = false;
 		config.opt_fast = false;
 
-		config.generic_uni_ops.set_id(ID($not));
-		// config.generic_uni_ops.set_id(ID($pos));
-		config.generic_uni_ops.set_id(ID($neg));
+		config.generic_uni_ops.set_id(TW($not));
+		// config.generic_uni_ops.set_id(TW($pos));
+		config.generic_uni_ops.set_id(TW($neg));
 
-		config.generic_cbin_ops.set_id(ID($and));
-		config.generic_cbin_ops.set_id(ID($or));
-		config.generic_cbin_ops.set_id(ID($xor));
-		config.generic_cbin_ops.set_id(ID($xnor));
+		config.generic_cbin_ops.set_id(TW($and));
+		config.generic_cbin_ops.set_id(TW($or));
+		config.generic_cbin_ops.set_id(TW($xor));
+		config.generic_cbin_ops.set_id(TW($xnor));
 
-		config.generic_bin_ops.set_id(ID($shl));
-		config.generic_bin_ops.set_id(ID($shr));
-		config.generic_bin_ops.set_id(ID($sshl));
-		config.generic_bin_ops.set_id(ID($sshr));
+		config.generic_bin_ops.set_id(TW($shl));
+		config.generic_bin_ops.set_id(TW($shr));
+		config.generic_bin_ops.set_id(TW($sshl));
+		config.generic_bin_ops.set_id(TW($sshr));
 
-		config.generic_bin_ops.set_id(ID($lt));
-		config.generic_bin_ops.set_id(ID($le));
-		config.generic_bin_ops.set_id(ID($eq));
-		config.generic_bin_ops.set_id(ID($ne));
-		config.generic_bin_ops.set_id(ID($eqx));
-		config.generic_bin_ops.set_id(ID($nex));
-		config.generic_bin_ops.set_id(ID($ge));
-		config.generic_bin_ops.set_id(ID($gt));
+		config.generic_bin_ops.set_id(TW($lt));
+		config.generic_bin_ops.set_id(TW($le));
+		config.generic_bin_ops.set_id(TW($eq));
+		config.generic_bin_ops.set_id(TW($ne));
+		config.generic_bin_ops.set_id(TW($eqx));
+		config.generic_bin_ops.set_id(TW($nex));
+		config.generic_bin_ops.set_id(TW($ge));
+		config.generic_bin_ops.set_id(TW($gt));
 
-		config.generic_cbin_ops.set_id(ID($add));
-		config.generic_cbin_ops.set_id(ID($mul));
+		config.generic_cbin_ops.set_id(TW($add));
+		config.generic_cbin_ops.set_id(TW($mul));
 
-		config.generic_bin_ops.set_id(ID($sub));
-		config.generic_bin_ops.set_id(ID($div));
-		config.generic_bin_ops.set_id(ID($mod));
-		config.generic_bin_ops.set_id(ID($divfloor));
-		config.generic_bin_ops.set_id(ID($modfloor));
-		// config.generic_bin_ops.set_id(ID($pow));
+		config.generic_bin_ops.set_id(TW($sub));
+		config.generic_bin_ops.set_id(TW($div));
+		config.generic_bin_ops.set_id(TW($mod));
+		config.generic_bin_ops.set_id(TW($divfloor));
+		config.generic_bin_ops.set_id(TW($modfloor));
+		// config.generic_bin_ops.set_id(TW($pow));
 
-		config.generic_uni_ops.set_id(ID($logic_not));
-		config.generic_cbin_ops.set_id(ID($logic_and));
-		config.generic_cbin_ops.set_id(ID($logic_or));
+		config.generic_uni_ops.set_id(TW($logic_not));
+		config.generic_cbin_ops.set_id(TW($logic_and));
+		config.generic_cbin_ops.set_id(TW($logic_or));
 
-		config.generic_other_ops.set_id(ID($alu));
-		config.generic_other_ops.set_id(ID($macc));
+		config.generic_other_ops.set_id(TW($alu));
+		config.generic_other_ops.set_id(TW($macc));
 
 		log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
 
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index e820dbc8d..ca7f2a914 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -29,21 +29,21 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct WreduceConfig
 {
-	pool<IdString> supported_cell_types;
+	pool<TwineRef> supported_cell_types;
 	bool keepdc = false;
 	bool mux_undef = false;
 
 	WreduceConfig()
 	{
-		supported_cell_types = pool<IdString>({
-			ID($not), ID($pos), ID($neg),
-			ID($and), ID($or), ID($xor), ID($xnor),
-			ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
-			ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
-			ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
-			ID($mux), ID($pmux),
-			ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
-			ID($dlatch), ID($adlatch),
+		supported_cell_types = pool<TwineRef>({
+			TW($not), TW($pos), TW($neg),
+			TW($and), TW($or), TW($xor), TW($xnor),
+			TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx),
+			TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt),
+			TW($add), TW($sub), TW($mul), // TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow),
+			TW($mux), TW($pmux),
+			TW($dff), TW($dffe), TW($adff), TW($adffe), TW($sdff), TW($sdffe), TW($sdffce),
+			TW($dlatch), TW($adlatch),
 		});
 	}
 };
@@ -104,14 +104,14 @@ struct WreduceWorker
 			sig_removed.append(bits_removed[i]);
 
 		if (GetSize(bits_removed) == GetSize(sig_y)) {
-			log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
+			log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
 			module->connect(sig_y, sig_removed);
 			module->remove(cell);
 			return;
 		}
 
 		log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
-				GetSize(sig_removed), GetSize(sig_y), module, cell, cell->type.unescape());
+				GetSize(sig_removed), GetSize(sig_y), module, cell, cell->type.unescaped());
 
 		int n_removed = GetSize(sig_removed);
 		int n_kept = GetSize(sig_y) - GetSize(sig_removed);
@@ -211,13 +211,13 @@ struct WreduceWorker
 			return;
 
 		if (GetSize(sig_q) == 0) {
-			log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
+			log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
 			module->remove(cell);
 			return;
 		}
 
 		log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
-				module, cell, cell->type.unescape());
+				module, cell, cell->type.unescaped());
 
 		for (auto bit : sig_d)
 			work_queue_bits.insert(bit);
@@ -246,7 +246,7 @@ struct WreduceWorker
 		auto &twines = cell->module->design->twines;
 		SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
 
-		if (port == 'B' && cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr)))
+		if (port == 'B' && cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr)))
 			port_signed = false;
 
 		int bits_removed = 0;
@@ -267,7 +267,7 @@ struct WreduceWorker
 
 		if (bits_removed) {
 			log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
-					bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescape());
+					bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescaped());
 			// SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
 			cell->setPort(twines.add(Twine{stringf("\\%c", port)}), sig);
 			did_something = true;
@@ -291,13 +291,13 @@ struct WreduceWorker
 	{
 		bool did_something = false;
 
-		if (!config->supported_cell_types.count(cell->type))
+		if (!config->supported_cell_types.count(cell->type_impl))
 			return;
 
-		if (cell->type.in(ID($mux), ID($pmux)))
+		if (cell->type.in(TW($mux), TW($pmux)))
 			return run_cell_mux(cell);
 
-		if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
+		if (cell->type.in(TW($dff), TW($dffe), TW($adff), TW($adffe), TW($sdff), TW($sdffe), TW($sdffce), TW($dlatch), TW($adlatch)))
 			return run_cell_dff(cell);
 
 		SigSpec sig = mi.sigmap(cell->getPort(TW::Y));
@@ -311,7 +311,7 @@ struct WreduceWorker
 		int max_port_a_size = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : -1;
 		int max_port_b_size = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : -1;
 
-		if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) {
+		if (cell->type.in(TW($not), TW($pos), TW($neg), TW($and), TW($or), TW($xor), TW($add), TW($sub))) {
 			max_port_a_size = min(max_port_a_size, GetSize(sig));
 			max_port_b_size = min(max_port_b_size, GetSize(sig));
 		}
@@ -321,7 +321,7 @@ struct WreduceWorker
 
 		// For some operations if the output is no wider than either of the inputs
 		// we are free to choose the signedness of the operands
-		if (cell->type.in(ID($mul), ID($add), ID($sub)) &&
+		if (cell->type.in(TW($mul), TW($add), TW($sub)) &&
 				max_port_a_size == GetSize(sig) &&
 				max_port_b_size == GetSize(sig)) {
 			SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B));
@@ -331,7 +331,7 @@ struct WreduceWorker
 			sig_b.extend_u0(max_port_b_size);
 
 			int signed_cost, unsigned_cost;
-			if (cell->type == ID($mul)) {
+			if (cell->type == TW($mul)) {
 				signed_cost = reduced_opsize(sig_a, true) * reduced_opsize(sig_b, true);
 				unsigned_cost = reduced_opsize(sig_a, false) * reduced_opsize(sig_b, false);
 			} else {
@@ -341,7 +341,7 @@ struct WreduceWorker
 
 			if (!port_a_signed && !port_b_signed && signed_cost < unsigned_cost) {
 				log("Converting cell %s.%s (%s) from unsigned to signed.\n",
-						module, cell, cell->type.unescape());
+						module, cell, cell->type.unescaped());
 				cell->setParam(ID::A_SIGNED, 1);
 				cell->setParam(ID::B_SIGNED, 1);
 				port_a_signed = true;
@@ -349,7 +349,7 @@ struct WreduceWorker
 				did_something = true;
 			} else if (port_a_signed && port_b_signed && unsigned_cost < signed_cost) {
 				log("Converting cell %s.%s (%s) from signed to unsigned.\n",
-						module, cell, cell->type.unescape());
+						module, cell, cell->type.unescaped());
 				cell->setParam(ID::A_SIGNED, 0);
 				cell->setParam(ID::B_SIGNED, 0);
 				port_a_signed = false;
@@ -358,7 +358,7 @@ struct WreduceWorker
 			}
 		}
 
-		if (max_port_a_size >= 0 && cell->type != ID($shiftx))
+		if (max_port_a_size >= 0 && cell->type != TW($shiftx))
 			run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something);
 
 		if (max_port_b_size >= 0)
@@ -369,7 +369,7 @@ struct WreduceWorker
 			if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
 					GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
 				log("Converting cell %s.%s (%s) from signed to unsigned.\n",
-						module, cell, cell->type.unescape());
+						module, cell, cell->type.unescaped());
 				cell->setParam(ID::A_SIGNED, 0);
 				cell->setParam(ID::B_SIGNED, 0);
 				port_a_signed = false;
@@ -382,7 +382,7 @@ struct WreduceWorker
 			SigSpec sig_a = mi.sigmap(cell->getPort(TW::A));
 			if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
 				log("Converting cell %s.%s (%s) from signed to unsigned.\n",
-						module, cell, cell->type.unescape());
+						module, cell, cell->type.unescaped());
 				cell->setParam(ID::A_SIGNED, 0);
 				port_a_signed = false;
 				did_something = true;
@@ -393,7 +393,7 @@ struct WreduceWorker
 		// Reduce size of port Y based on sizes for A and B and unused bits in Y
 
 		int bits_removed = 0;
-		if (port_a_signed && cell->type == ID($shr)) {
+		if (port_a_signed && cell->type == TW($shr)) {
 			// do not reduce size of output on $shr cells with signed A inputs
 		} else {
 			while (GetSize(sig) > 0)
@@ -411,9 +411,9 @@ struct WreduceWorker
 			}
 		}
 
-		if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
+		if (cell->type.in(TW($pos), TW($add), TW($mul), TW($and), TW($or), TW($xor), TW($sub)))
 		{
-			bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
+			bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == TW($sub);
 
 			int a_size = 0, b_size = 0;
 			if (cell->hasPort(TW::A)) a_size = GetSize(cell->getPort(TW::A));
@@ -421,10 +421,10 @@ struct WreduceWorker
 
 			int max_y_size = max(a_size, b_size);
 
-			if (cell->type.in(ID($add), ID($sub)))
+			if (cell->type.in(TW($add), TW($sub)))
 				max_y_size++;
 
-			if (cell->type == ID($mul))
+			if (cell->type == TW($mul))
 				max_y_size = a_size + b_size;
 
 			max_y_size = std::max(max_y_size, 1);
@@ -441,14 +441,14 @@ struct WreduceWorker
 		}
 
 		if (GetSize(sig) == 0) {
-			log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
+			log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
 			module->remove(cell);
 			return;
 		}
 
 		if (bits_removed) {
 			log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
-					bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape());
+					bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescaped());
 			cell->setPort(TW::Y, sig);
 			did_something = true;
 		}
@@ -591,9 +591,9 @@ struct WreducePass : public Pass {
 
 			for (auto c : module->selected_cells())
 			{
-				if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
-						ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
-						ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(TW::Y)) > 1) {
+				if (c->type.in(TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool),
+						TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt),
+						TW($logic_not), TW($logic_and), TW($logic_or)) && GetSize(c->getPort(TW::Y)) > 1) {
 					SigSpec sig = c->getPort(TW::Y);
 					if (!sig.has_const()) {
 						c->setPort(TW::Y, sig[0]);
@@ -603,7 +603,7 @@ struct WreducePass : public Pass {
 					}
 				}
 
-				if (c->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
+				if (c->type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow)))
 				{
 					SigSpec A = c->getPort(TW::A);
 					int original_a_width = GetSize(A);
@@ -616,7 +616,7 @@ struct WreducePass : public Pass {
 					}
 					if (original_a_width != GetSize(A)) {
 						log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
-								original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape());
+								original_a_width-GetSize(A), original_a_width, module, c, design->twines.unescaped_str(c->type));
 						c->setPort(TW::A, A);
 						c->setParam(ID::A_WIDTH, GetSize(A));
 					}
@@ -632,13 +632,13 @@ struct WreducePass : public Pass {
 					}
 					if (original_b_width != GetSize(B)) {
 						log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
-								original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape());
+								original_b_width-GetSize(B), original_b_width, module, c, design->twines.unescaped_str(c->type));
 						c->setPort(TW::B, B);
 						c->setParam(ID::B_WIDTH, GetSize(B));
 					}
 				}
 
-				if (!opt_memx && c->type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) {
+				if (!opt_memx && c->type.in(TW($memrd), TW($memrd_v2), TW($memwr), TW($memwr_v2), TW($meminit), TW($meminit_v2))) {
 					std::string memid_s = c->getParam(ID::MEMID).decode_string();
 					TwineRef memid = design->twines.add(Twine{memid_s});
 					RTLIL::Memory *mem = module->memories.at(memid);
@@ -648,7 +648,7 @@ struct WreducePass : public Pass {
 						if (cur_addrbits > max_addrbits) {
 							log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
 									cur_addrbits-max_addrbits, cur_addrbits,
-									c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
+									c->type == TW($memrd) ? "read" : c->type == TW($memwr) ? "write" : "init",
 									module, c, memid_s);
 							c->setParam(ID::ABITS, max_addrbits);
 							c->setPort(TW::ADDR, c->getPort(TW::ADDR).extract(0, max_addrbits));
diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc
index 8d24a874a..7fc439faf 100644
--- a/passes/pmgen/test_pmgen.cc
+++ b/passes/pmgen/test_pmgen.cc
@@ -37,7 +37,7 @@ void reduce_chain(test_pmgen_pm &pm)
 	if (ud.longest_chain.empty())
 		return;
 
-	log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
+	log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), design->twines.unescaped_str(st.first->type));
 
 	SigSpec A;
 	SigSpec Y = ud.longest_chain.front().first->getPort(TW::Y);
@@ -57,16 +57,16 @@ void reduce_chain(test_pmgen_pm &pm)
 
 	Cell *c;
 
-	if (last_cell->type == ID($_AND_))
+	if (last_cell->type == TW($_AND_))
 		c = pm.module->addReduceAnd(NEW_TWINE, A, Y);
-	else if (last_cell->type == ID($_OR_))
+	else if (last_cell->type == TW($_OR_))
 		c = pm.module->addReduceOr(NEW_TWINE, A, Y);
-	else if (last_cell->type == ID($_XOR_))
+	else if (last_cell->type == TW($_XOR_))
 		c = pm.module->addReduceXor(NEW_TWINE, A, Y);
 	else
 		log_abort();
 
-	log("    -> %s (%s)\n", c, c->type.unescape());
+	log("    -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
 }
 
 void reduce_tree(test_pmgen_pm &pm)
@@ -81,21 +81,21 @@ void reduce_tree(test_pmgen_pm &pm)
 	SigSpec Y = st.first->getPort(TW::Y);
 	pm.autoremove(st.first);
 
-	log("Found %s tree with %d leaves for %s (%s).\n", st.first->type.unescape(),
+	log("Found %s tree with %d leaves for %s (%s).\n", design->twines.unescaped_str(st.first->type),
 			GetSize(A), log_signal(Y), st.first);
 
 	Cell *c;
 
-	if (st.first->type == ID($_AND_))
+	if (st.first->type == TW($_AND_))
 		c = pm.module->addReduceAnd(NEW_TWINE, A, Y);
-	else if (st.first->type == ID($_OR_))
+	else if (st.first->type == TW($_OR_))
 		c = pm.module->addReduceOr(NEW_TWINE, A, Y);
-	else if (st.first->type == ID($_XOR_))
+	else if (st.first->type == TW($_XOR_))
 		c = pm.module->addReduceXor(NEW_TWINE, A, Y);
 	else
 		log_abort();
 
-	log("    -> %s (%s)\n", c, c->type.unescape());
+	log("    -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
 }
 
 void opt_eqpmux(test_pmgen_pm &pm)
@@ -113,7 +113,7 @@ void opt_eqpmux(test_pmgen_pm &pm)
 
 	pm.autoremove(st.pmux);
 	Cell *c = pm.module->addMux(NEW_TWINE, NE, EQ, st.eq->getPort(TW::Y), Y);
-	log("    -> %s (%s)\n", c, c->type.unescape());
+	log("    -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
 }
 
 struct TestPmgenPass : public Pass {
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 15e79e583..1361cc50d 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -39,23 +39,23 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
 
 	for (auto cell : mod->cells())
 	{
-		if (cell->type == ID($reduce_or) && cell->getPort(TW::Y) == signal)
+		if (cell->type == TW($reduce_or) && cell->getPort(TW::Y) == signal)
 			return check_signal(mod, cell->getPort(TW::A), ref, polarity);
 
-		if (cell->type == ID($reduce_bool) && cell->getPort(TW::Y) == signal)
+		if (cell->type == TW($reduce_bool) && cell->getPort(TW::Y) == signal)
 			return check_signal(mod, cell->getPort(TW::A), ref, polarity);
 
-		if (cell->type == ID($logic_not) && cell->getPort(TW::Y) == signal) {
+		if (cell->type == TW($logic_not) && cell->getPort(TW::Y) == signal) {
 			polarity = !polarity;
 			return check_signal(mod, cell->getPort(TW::A), ref, polarity);
 		}
 
-		if (cell->type == ID($not) && cell->getPort(TW::Y) == signal) {
+		if (cell->type == TW($not) && cell->getPort(TW::Y) == signal) {
 			polarity = !polarity;
 			return check_signal(mod, cell->getPort(TW::A), ref, polarity);
 		}
 
-		if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(TW::Y) == signal) {
+		if (cell->type.in(TW($eq), TW($eqx)) && cell->getPort(TW::Y) == signal) {
 			if (cell->getPort(TW::A).is_fully_const()) {
 				if (!cell->getPort(TW::A).as_bool())
 					polarity = !polarity;
@@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
 			}
 		}
 
-		if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(TW::Y) == signal) {
+		if (cell->type.in(TW($ne), TW($nex)) && cell->getPort(TW::Y) == signal) {
 			if (cell->getPort(TW::A).is_fully_const()) {
 				if (cell->getPort(TW::A).as_bool())
 					polarity = !polarity;
@@ -215,7 +215,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
 						RTLIL::SigSpec en = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.enable, memwr.enable);
 						if (!en.is_fully_zero()) {
 							log_error("Async reset %s causes memory write to %s.\n",
-									log_signal(sync->signal), memwr.memid.unescape());
+									log_signal(sync->signal), design->twines.unescaped_str(memwr.memid));
 						}
 						apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.address, memwr.address);
 						apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.data, memwr.data);
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index e2ca54544..aa92840c3 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -94,7 +94,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
 	std::stringstream sstr;
 	sstr << "$procdff$" << (autoidx++);
 
-	RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, ID($aldff));
+	RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, TW($aldff));
 	cell->attributes = proc->attributes;
 
 	cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
@@ -116,7 +116,7 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
 	std::stringstream sstr;
 	sstr << "$procdff$" << (autoidx++);
 
-	RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
+	RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? TW($ff) : arst ? TW($adff) : TW($dff));
 	cell->attributes = proc->attributes;
 
 	cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc
index a5d0cee59..663e5a312 100644
--- a/passes/proc/proc_dlatch.cc
+++ b/passes/proc/proc_dlatch.cc
@@ -46,7 +46,7 @@ struct proc_dlatch_db_t
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($mux), ID($pmux), ID($bwmux)))
+			if (cell->type.in(TW($mux), TW($pmux), TW($bwmux)))
 			{
 				auto sig_y = sigmap(cell->getPort(TW::Y));
 				for (int i = 0; i < GetSize(sig_y); i++)
@@ -185,8 +185,8 @@ struct proc_dlatch_db_t
 		Cell *cell = it->second.first;
 		int index = it->second.second;
 
-		log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux)));
-		bool is_bwmux = (cell->type == ID($bwmux));
+		log_assert(cell->type.in(TW($mux), TW($pmux), TW($bwmux)));
+		bool is_bwmux = (cell->type == TW($bwmux));
 		SigSpec sig_a = sigmap(cell->getPort(TW::A));
 		SigSpec sig_b = sigmap(cell->getPort(TW::B));
 		SigSpec sig_s = sigmap(cell->getPort(TW::S));
@@ -328,7 +328,7 @@ struct proc_dlatch_db_t
 			pool<Cell*> next_queue;
 
 			for (auto cell : queue) {
-				if (cell->type.in(ID($mux), ID($pmux)))
+				if (cell->type.in(TW($mux), TW($pmux)))
 					fixup_mux(cell);
 				for (auto bit : upstream_cell2net[cell])
 					for (auto cell : upstream_net2cell[bit])
@@ -338,7 +338,7 @@ struct proc_dlatch_db_t
 
 			queue.clear();
 			for (auto cell : next_queue) {
-				if (!visited.count(cell) && ct.cell_known(cell->type))
+				if (!visited.count(cell) && ct.cell_known(cell->type_impl))
 					queue.insert(cell);
 			}
 		}
diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc
index aab451606..e55e21ba1 100644
--- a/passes/proc/proc_memwr.cc
+++ b/passes/proc/proc_memwr.cc
@@ -42,7 +42,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
 					priority_mask.set(prev_port_ids[i], State::S1);
 			prev_port_ids.push_back(port_id);
 
-			RTLIL::Cell *cell = mod->addCell(NEW_TWINE, ID($memwr_v2));
+			RTLIL::Cell *cell = mod->addCell(NEW_TWINE, TW($memwr_v2));
 			cell->attributes = memwr.attributes;
 			cell->setParam(ID::MEMID, Const(memwr.memid.str()));
 			cell->setParam(ID::ABITS, GetSize(memwr.address));
@@ -102,8 +102,8 @@ struct ProcMemWrPass : public Pass {
 		for (auto mod : design->all_selected_modules()) {
 			dict<IdString, int> next_port_id;
 			for (auto cell : mod->cells()) {
-				if (cell->type.in(ID($memwr), ID($memwr_v2))) {
-					bool is_compat = cell->type == ID($memwr);
+				if (cell->type.in(TW($memwr), TW($memwr_v2))) {
+					bool is_compat = cell->type == TW($memwr);
 					IdString memid = cell->parameters.at(ID::MEMID).decode_string();
 					int port_id = cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int();
 					if (port_id >= next_port_id[memid])
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index e457a85de..007124182 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 		else
 		{
 			// create compare cell
-			RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? ID($eqx) : ID($eq));
+			RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? TW($eqx) : TW($eq));
 			apply_attrs(eq_cell, sw, cs);
 
 			eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
@@ -204,7 +204,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 		ctrl_wire = mod->addWire(Twine{sstr.str() + "_CTRL"});
 
 		// reduce cmp vector to one logic signal
-		RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, ID($reduce_or));
+		RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, TW($reduce_or));
 		apply_attrs(any_cell, sw, cs);
 
 		any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
@@ -239,7 +239,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 	RTLIL::Wire *result_wire = mod->addWire(Twine{sstr.str() + "_Y"}, when_signal.size());
 
 	// create the multiplexer itself
-	RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, ID($mux));
+	RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, TW($mux));
 	apply_attrs(mux_cell, sw, cs);
 
 	mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index 0325c9508..0213b381c 100644
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -54,10 +54,10 @@ struct AssertpmuxWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($mux), ID($pmux)))
+			if (cell->type.in(TW($mux), TW($pmux)))
 			{
 				int width = cell->getParam(ID::WIDTH).as_int();
-				int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
+				int numports = cell->type == TW($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
 
 				SigSpec sig_a = sigmap(cell->getPort(TW::A));
 				SigSpec sig_b = sigmap(cell->getPort(TW::B));
@@ -234,7 +234,7 @@ struct AssertpmuxPass : public Pass {
 			vector<Cell*> pmux_cells;
 
 			for (auto cell : module->selected_cells())
-				if (cell->type == ID($pmux))
+				if (cell->type == TW($pmux))
 					pmux_cells.push_back(cell);
 
 			for (auto cell : pmux_cells)
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index 828d630ac..b602b57f9 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -79,9 +79,9 @@ struct Async2syncPass : public Pass {
 
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				if (cell->type.in(ID($print), ID($check)))
+				if (cell->type.in(TW($print), TW($check)))
 				{
-					if (cell->type == ID($check))
+					if (cell->type == TW($check))
 						have_check_cells = true;
 
 					bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
@@ -111,7 +111,7 @@ struct Async2syncPass : public Pass {
 						module->addDff(NEW_TWINE, sig_trg, sig_args, sig_args_q, trg_polarity, cell->src_ref());
 						cell->setPort(TW::EN, sig_en_q);
 						cell->setPort(TW::ARGS, sig_args_q);
-						if (cell->type == ID($check)) {
+						if (cell->type == TW($check)) {
 							SigBit sig_a = cell->getPort(TW::A);
 							Wire *sig_a_q = module->addWire(NEW_TWINE);
 							sig_a_q->attributes.emplace(ID::init, State::S1);
@@ -147,7 +147,7 @@ struct Async2syncPass : public Pass {
 						ff.unmap_ce_srst();
 
 						log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
-								module, cell, cell->type.unescape(),
+								module, cell, cell->type.unescaped(),
 								log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_d), log_signal(ff.sig_q));
 
 						initvals.remove_init(ff.sig_q);
@@ -245,7 +245,7 @@ struct Async2syncPass : public Pass {
 						ff.unmap_srst();
 
 						log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
-								module, cell, cell->type.unescape(),
+								module, cell, cell->type.unescaped(),
 								log_signal(ff.sig_arst), log_signal(ff.sig_d), log_signal(ff.sig_q));
 
 						initvals.remove_init(ff.sig_q);
@@ -279,7 +279,7 @@ struct Async2syncPass : public Pass {
 				{
 					// Latch.
 					log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
-							module, cell, cell->type.unescape(),
+							module, cell, cell->type.unescaped(),
 							log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
 
 					initvals.remove_init(ff.sig_q);
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index c6d68894b..81fd12840 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -173,7 +173,7 @@ struct Clk2fflogicPass : public Pass {
 					auto &port = mem.rd_ports[i];
 					if (port.clk_enable)
 						log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
-								"Call \"memory\" with -nordff to avoid this error.\n", i, mem.memid.unescape(), module);
+								"Call \"memory\" with -nordff to avoid this error.\n", i, design->twines.unescaped_str(mem.memid), module);
 				}
 
 				for (int i = 0; i < GetSize(mem.wr_ports); i++)
@@ -184,10 +184,10 @@ struct Clk2fflogicPass : public Pass {
 						continue;
 
 					log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
-							i, module, mem.memid.unescape(), log_signal(port.clk),
+							i, module, design->twines.unescaped_str(mem.memid), log_signal(port.clk),
 							log_signal(port.addr), log_signal(port.data));
 
-					Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk))));
+					Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", design->twines.unescaped_str(mem.memid), i, log_signal(port.clk))));
 					past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
 					module->addFf(NEW_TWINE, port.clk, past_clk);
 
@@ -203,13 +203,13 @@ struct Clk2fflogicPass : public Pass {
 
 					SigSpec clock_edge = module->Eqx(NEW_TWINE, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
 
-					SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en));
+					SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.en));
 					module->addFf(NEW_TWINE, port.en, en_q);
 
-					SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr));
+					SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.addr));
 					module->addFf(NEW_TWINE, port.addr, addr_q);
 
-					SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data));
+					SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.data));
 					module->addFf(NEW_TWINE, port.data, data_q);
 
 					port.clk = State::S0;
@@ -228,9 +228,9 @@ struct Clk2fflogicPass : public Pass {
 
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				if (cell->type.in(ID($print), ID($check)))
+				if (cell->type.in(TW($print), TW($check)))
 				{
-					if (cell->type == ID($check))
+					if (cell->type == TW($check))
 						have_check_cells = true;
 
 					bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
@@ -262,7 +262,7 @@ struct Clk2fflogicPass : public Pass {
 
 						cell->setPort(TW::EN, module->And(NEW_TWINE, sig_en_sampled, sig_trg_combined));
 						cell->setPort(TW::ARGS, sig_args_sampled);
-						if (cell->type == ID($check)) {
+						if (cell->type == TW($check)) {
 							SigBit sig_a = cell->getPort(TW::A);
 							SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled;
 							cell->setPort(TW::A, sig_a_sampled);
@@ -291,16 +291,16 @@ struct Clk2fflogicPass : public Pass {
 
 				if (ff.has_clk) {
 					log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
-							module, cell, cell->type.unescape(),
+							module, cell, cell->type.unescaped(),
 							log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
 				} else if (ff.has_aload) {
 					log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
-							module, cell, cell->type.unescape(),
+							module, cell, cell->type.unescaped(),
 							log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
 				} else {
 					// $sr.
 					log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
-							module, cell, cell->type.unescape(),
+							module, cell, cell->type.unescaped(),
 							log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
 				}
 
diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index 38989ee12..8c0fdafd0 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -126,7 +126,7 @@ struct CutpointPass : public Pass {
 						wire_drivers.insert(bit);
 
 			for (auto cell : module->selected_cells()) {
-				if (cell->type == ID($anyseq))
+				if (cell->type == TW($anyseq))
 					continue;
 				log("Removing cell %s.%s, making all cell outputs cutpoints.\n", module, cell);
 				for (auto &conn : cell->connections()) {
@@ -135,7 +135,7 @@ struct CutpointPass : public Pass {
 						if (cell->input(conn.first))
 							for (auto bit : sigmap(conn.second))
 								if (wire_drivers.count(bit)) {
-									log_debug("  Treating inout port '%s' as input.\n", conn.first.unescape());
+									log_debug("  Treating inout port '%s' as input.\n", design->twines.unescaped_str(conn.first));
 									do_cut = false;
 									break;
 								}
@@ -143,7 +143,7 @@ struct CutpointPass : public Pass {
 						if (do_cut) {
 							module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_TWINE, GetSize(conn.second)));
 							if (cell->input(conn.first)) {
-								log_debug("  Treating inout port '%s' as output.\n", conn.first.unescape());
+								log_debug("  Treating inout port '%s' as output.\n", design->twines.unescaped_str(conn.first));
 								for (auto bit : sigmap(conn.second))
 									wire_drivers.insert(bit);
 							}
@@ -154,7 +154,7 @@ struct CutpointPass : public Pass {
 				RTLIL::Cell *scopeinfo = nullptr;
 				RTLIL::IdString cell_name(cell->name);
 				if (flag_scopeinfo && cell_name.isPublic()) {
-					auto scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo));
+					auto scopeinfo = module->addCell(NEW_TWINE, TW($scopeinfo));
 					scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
 
 					for (auto const &attr : cell->attributes)
@@ -162,7 +162,7 @@ struct CutpointPass : public Pass {
 						if (attr.first == ID::hdlname)
 							scopeinfo->attributes.insert(attr);
 						else
-							scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second);
+							scopeinfo->attributes.emplace(stringf("\\cell_%s", design->twines.unescaped_str(attr.first)), attr.second);
 					}
 				}
 
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index a192fba9b..2432bdedc 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -149,7 +149,7 @@ struct VlogHammerReporter
 
 		for (auto c : module->cells())
 			if (!satgen.importCell(c))
-				log_error("Failed to import cell %s (type %s) to SAT database.\n", c->name.unescape(), c->type.unescape());
+				log_error("Failed to import cell %s (type %s) to SAT database.\n", design->twines.unescaped_str(c->name), design->twines.unescaped_str(c->type));
 
 		ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
 
@@ -262,21 +262,21 @@ struct VlogHammerReporter
 					if (module == modules.front()) {
 						RTLIL::SigSpec sig(wire);
 						if (!ce.eval(sig))
-							log_error("Can't read back value for port %s!\n", inputs[i].unescape());
+							log_error("Can't read back value for port %s!\n", design->twines.unescaped_str(inputs[i]));
 						input_pattern_list += stringf(" %s", sig.as_const().as_string());
-						log("++PAT++ %d %s %s #\n", idx, inputs[i].unescape(), sig.as_const().as_string());
+						log("++PAT++ %d %s %s #\n", idx, design->twines.unescaped_str(inputs[i]), sig.as_const().as_string());
 					}
 				}
 
 				if (module->wire(ID(y)) == nullptr)
-					log_error("No output wire (y) found in module %s!\n", module->name.unescape());
+					log_error("No output wire (y) found in module %s!\n", design->twines.unescaped_str(module->name));
 
 				RTLIL::SigSpec sig(module->wire(ID(y)));
 				RTLIL::SigSpec undef;
 
 				while (!ce.eval(sig, undef)) {
 					// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", module, log_signal(sig), log_signal(undef));
-					log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), module->name.unescape());
+					log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), design->twines.unescaped_str(module->name));
 					ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
 				}
 
@@ -288,7 +288,7 @@ struct VlogHammerReporter
 					sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
 				} else if (rtl_sig.size() > 0) {
 					if (rtl_sig.size() != sig.size())
-						log_error("Output (y) has a different width in module %s compared to rtl!\n", module->name.unescape());
+						log_error("Output (y) has a different width in module %s compared to rtl!\n", design->twines.unescaped_str(module->name));
 					for (int i = 0; i < GetSize(sig); i++)
 						if (rtl_sig[i] == RTLIL::State::Sx)
 							sig[i] = RTLIL::State::Sx;
@@ -319,10 +319,10 @@ struct VlogHammerReporter
 			RTLIL::IdString esc_name = RTLIL::escape_id(name);
 			for (auto mod : modules) {
 				if (mod->wire(esc_name) == nullptr)
-					log_error("Can't find input %s in module %s!\n", name, mod->name.unescape());
+					log_error("Can't find input %s in module %s!\n", name, design->twines.unescaped_str(mod->name));
 				RTLIL::Wire *port = mod->wire(esc_name);
 				if (!port->port_input || port->port_output)
-					log_error("Wire %s in module %s is not an input!\n", name, mod->name.unescape());
+					log_error("Wire %s in module %s is not an input!\n", name, design->twines.unescaped_str(mod->name));
 				if (width >= 0 && width != port->width)
 					log_error("Port %s has different sizes in the different modules!\n", name);
 				width = port->width;
@@ -443,7 +443,7 @@ struct EvalPass : public Pass {
 		for (auto mod : design->selected_modules()) {
 			if (module)
 				log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
-						module->name.unescape(), mod->name.unescape());
+						module->name.unescape(), design->twines.unescaped_str(mod->name));
 			module = mod;
 		}
 		if (module == NULL)
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index bff31ed0b..88aa5e9f9 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -85,7 +85,7 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
 	SigPool dffsignals;
 
 	for (auto cell : module->cells()) {
-		if (ct.cell_known(cell->type) && cell->hasPort(TW::Q))
+		if (ct.cell_known(cell->type_impl) && cell->hasPort(TW::Q))
 			dffsignals.add(sigmap(cell->getPort(TW::Q)));
 	}
 
@@ -111,7 +111,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
 		info.arst_value = RTLIL::State::Sm;
 		info.cell = cell;
 
-		if (info.cell->type == ID($dff)) {
+		if (info.cell->type == TW($dff)) {
 			info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit();
 			info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
 			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(TW::D)).to_sigbit_vector();
@@ -123,7 +123,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
 			continue;
 		}
 
-		if (info.cell->type == ID($adff)) {
+		if (info.cell->type == TW($adff)) {
 			info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit();
 			info.bit_arst = sigmap(info.cell->getPort(TW::ARST)).as_bit();
 			info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
@@ -139,9 +139,9 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
 			continue;
 		}
 
-		if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
+		if (info.cell->type.in(TW($_DFF_N_), TW($_DFF_P_))) {
 			info.bit_clk = sigmap(info.cell->getPort(TW::C)).as_bit();
-			info.clk_polarity = info.cell->type == ID($_DFF_P_);
+			info.clk_polarity = info.cell->type == TW($_DFF_P_);
 			info.bit_d = sigmap(info.cell->getPort(TW::D)).as_bit();
 			bit_info[sigmap(info.cell->getPort(TW::Q)).as_bit()] = info;
 			continue;
@@ -210,7 +210,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
 RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
 {
 	if (module->count_id(name))
-		log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", name.unescape());
+		log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", design->twines.unescaped_str(name));
 	return module->addWire(name, width);
 }
 
@@ -497,10 +497,10 @@ struct ExposePass : public Pass {
 				}
 
 				for (auto cell : module->cells()) {
-					if (!ct.cell_known(cell->type))
+					if (!ct.cell_known(cell->type_impl))
 						continue;
 					for (auto &conn : cell->connections_)
-						if (ct.cell_output(cell->type, conn.first))
+						if (ct.cell_output(cell->type_impl, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}
 
@@ -518,10 +518,10 @@ struct ExposePass : public Pass {
 				}
 
 				for (auto cell : module->cells()) {
-					if (!ct.cell_known(cell->type))
+					if (!ct.cell_known(cell->type_impl))
 						continue;
 					for (auto &conn : cell->connections_)
-						if (ct.cell_input(cell->type, conn.first))
+						if (ct.cell_input(cell->type_impl, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}
 
@@ -578,7 +578,7 @@ struct ExposePass : public Pass {
 				if (info.clk_polarity) {
 					module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
 				} else {
-					RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not));
+					RTLIL::Cell *c = module->addCell(NEW_TWINE, TW($not));
 					c->parameters[ID::A_SIGNED] = 0;
 					c->parameters[ID::A_WIDTH] = 1;
 					c->parameters[ID::Y_WIDTH] = 1;
@@ -594,7 +594,7 @@ struct ExposePass : public Pass {
 					if (info.arst_polarity) {
 						module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
 					} else {
-						RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not));
+						RTLIL::Cell *c = module->addCell(NEW_TWINE, TW($not));
 						c->parameters[ID::A_SIGNED] = 0;
 						c->parameters[ID::A_WIDTH] = 1;
 						c->parameters[ID::Y_WIDTH] = 1;
@@ -632,13 +632,13 @@ struct ExposePass : public Pass {
 							if (!p->port_input && !p->port_output)
 								continue;
 
-							RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + p->name.unescape(), p->width);
+							RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + design->twines.unescaped_str(p->name), p->width);
 							if (p->port_input)
 								w->port_output = true;
 							if (p->port_output)
 								w->port_input = true;
 
-							log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape());
+							log("New module port: %s/%s (%s)\n", module, w, cell->type.unescaped());
 
 							RTLIL::SigSpec sig;
 							if (cell->hasPort(p->name))
@@ -654,13 +654,13 @@ struct ExposePass : public Pass {
 					{
 						for (auto &it : cell->connections())
 						{
-							RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + it.first.unescape(), it.second.size());
-							if (ct.cell_input(cell->type, it.first))
+							RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + design->twines.unescaped_str(it.first), it.second.size());
+							if (ct.cell_input(cell->type_impl, it.first))
 								w->port_output = true;
-							if (ct.cell_output(cell->type, it.first))
+							if (ct.cell_output(cell->type_impl, it.first))
 								w->port_input = true;
 
-							log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape());
+							log("New module port: %s/%s (%s)\n", module, w, cell->type.unescaped());
 
 							if (w->port_input)
 								module->connect(RTLIL::SigSig(it.second, w));
@@ -673,7 +673,7 @@ struct ExposePass : public Pass {
 				}
 
 				for (auto cell : delete_cells) {
-					log("Removing cell: %s/%s (%s)\n", module, cell, cell->type.unescape());
+					log("Removing cell: %s/%s (%s)\n", module, cell, cell->type.unescaped());
 					module->remove(cell);
 				}
 			}
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index c40803f08..e13be0650 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -95,11 +95,11 @@ struct FmcombineWorker
 	void generate()
 	{
 		if (design->module(combined_type)) {
-			// log("Combined module %s already exists.\n", combined_type.unescape());
+			// log("Combined module %s already exists.\n", design->twines.unescaped_str(combined_type));
 			return;
 		}
 
-		log("Generating combined module %s from module %s.\n", combined_type.unescape(), orig_type.unescape());
+		log("Generating combined module %s from module %s.\n", design->twines.unescaped_str(combined_type), design->twines.unescaped_str(orig_type));
 		module = design->addModule(combined_type);
 
 		for (auto wire : original->wires()) {
@@ -110,7 +110,7 @@ struct FmcombineWorker
 
 		for (auto cell : original->cells()) {
 			if (design->module(cell->type) == nullptr) {
-				if (opts.anyeq && cell->type.in(ID($anyseq), ID($anyconst))) {
+				if (opts.anyeq && cell->type.in(TW($anyseq), TW($anyconst))) {
 					Cell *gold = import_prim_cell(cell, "_gold");
 					for (auto &conn : cell->connections())
 						module->connect(import_sig(conn.second, "_gate"), gold->getPort(conn.first));
@@ -153,7 +153,7 @@ struct FmcombineWorker
 
 		for (auto cell : original->cells())
 		{
-			if (!ct.cell_known(cell->type))
+			if (!ct.cell_known(cell->type_impl))
 				continue;
 
 			for (auto &conn : cell->connections())
@@ -174,7 +174,7 @@ struct FmcombineWorker
 
 		for (auto cell : original->cells())
 		{
-			if (!ct.cell_known(cell->type))
+			if (!ct.cell_known(cell->type_impl))
 				continue;
 
 			bool skip_cell = !cell_to_eq_nets.count(cell);
@@ -332,15 +332,15 @@ struct FmcombinePass : public Pass {
 
 			module = design->module(module_name);
 			if (module == nullptr)
-				log_cmd_error("Module %s not found.\n", module_name.unescape());
+				log_cmd_error("Module %s not found.\n", design->twines.unescaped_str(module_name));
 
 			gold_cell = module->cell(gold_name);
 			if (gold_cell == nullptr)
-				log_cmd_error("Gold cell %s not found in module %s.\n", gold_name.unescape(), module);
+				log_cmd_error("Gold cell %s not found in module %s.\n", design->twines.unescaped_str(gold_name), module);
 
 			gate_cell = module->cell(gate_name);
 			if (gate_cell == nullptr)
-				log_cmd_error("Gate cell %s not found in module %s.\n", gate_name.unescape(), module);
+				log_cmd_error("Gate cell %s not found in module %s.\n", design->twines.unescaped_str(gate_name), module);
 		}
 		else
 		{
diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc
index 2165c7243..d0655b20b 100644
--- a/passes/sat/formalff.cc
+++ b/passes/sat/formalff.cc
@@ -110,9 +110,9 @@ struct InitValWorker
 			return ff.val_init[portbit.offset];
 		}
 
-		if (cell->type.in(ID($mux), ID($and), ID($or), ID($eq), ID($eqx), ID($initstate)))
+		if (cell->type.in(TW($mux), TW($and), TW($or), TW($eq), TW($eqx), TW($initstate)))
 		{
-			if (cell->type == ID($mux))
+			if (cell->type == TW($mux))
 			{
 				SigBit sig_s = sigmap(cell->getPort(TW::S));
 				State init_s = initconst(sig_s);
@@ -131,16 +131,16 @@ struct InitValWorker
 				return init_y;
 			}
 
-			if (cell->type.in(ID($and), ID($or)))
+			if (cell->type.in(TW($and), TW($or)))
 			{
 				State init_a = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, portbit.offset));
 				State init_b = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, portbit.offset));
 				State init_y;
 				if (init_a == init_b)
 					init_y = init_a;
-				else if (cell->type == ID($and) && (init_a == State::S0 || init_b == State::S0))
+				else if (cell->type == TW($and) && (init_a == State::S0 || init_b == State::S0))
 					init_y = State::S0;
-				else if (cell->type == ID($or) && (init_a == State::S1 || init_b == State::S1))
+				else if (cell->type == TW($or) && (init_a == State::S1 || init_b == State::S1))
 					init_y = State::S1;
 				else
 					init_y = State::Sx;
@@ -149,7 +149,7 @@ struct InitValWorker
 				return init_y;
 			}
 
-			if (cell->type.in(ID($eq), ID($eqx))) // Treats $eqx as $eq
+			if (cell->type.in(TW($eq), TW($eqx))) // Treats $eqx as $eq
 			{
 				if (portbit.offset > 0) {
 					initconst_bits[bit] = State::S0;
@@ -178,7 +178,7 @@ struct InitValWorker
 				return init_y;
 			}
 
-			if (cell->type == ID($initstate))
+			if (cell->type == TW($initstate))
 			{
 				initconst_bits[bit] = State::S1;
 				return State::S1;
@@ -224,7 +224,7 @@ struct InitValWorker
 
 		for (auto portbit : portbits) {
 			RTLIL::Cell *cell = portbit.cell;
-			if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !cell->is_builtin_ff()) {
+			if (!cell->type.in(TW($mux), TW($and), TW($or), TW($mem_v2)) && !cell->is_builtin_ff()) {
 				return true;
 			}
 		}
@@ -244,7 +244,7 @@ struct InitValWorker
 
 				return true;
 			}
-			else if (cell->type == ID($mux))
+			else if (cell->type == TW($mux))
 			{
 				State init_s = initconst(cell->getPort(TW::S).as_bit());
 				if (init_s == State::S0 && portbit.port == ID::B)
@@ -256,14 +256,14 @@ struct InitValWorker
 				if (is_initval_used(sig_y[portbit.offset]))
 					return true;
 			}
-			else if (cell->type.in(ID($and), ID($or)))
+			else if (cell->type.in(TW($and), TW($or)))
 			{
 				auto sig_a = cell->getPort(TW::A);
 				auto sig_b = cell->getPort(TW::B);
 				auto sig_y = cell->getPort(TW::Y);
 				if (GetSize(sig_y) != GetSize(sig_a) || GetSize(sig_y) != GetSize(sig_b))
 					return true; // TODO handle more of this
-				State absorbing = cell->type == ID($and) ? State::S0 : State::S1;
+				State absorbing = cell->type == TW($and) ? State::S0 : State::S1;
 				if (portbit.port == ID::A && initconst(sig_b[portbit.offset]) == absorbing)
 					continue;
 				if (portbit.port == ID::B && initconst(sig_a[portbit.offset]) == absorbing)
@@ -272,7 +272,7 @@ struct InitValWorker
 				if (is_initval_used(sig_y[portbit.offset]))
 					return true;
 			}
-			else if (cell->type == ID($mem_v2))
+			else if (cell->type == TW($mem_v2))
 			{
 				// TODO Use mem.h instead to uniformily cover all cases, most
 				// likely requires processing all memories when initializing
@@ -368,7 +368,7 @@ struct PropagateWorker
 				replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].at(0) == State::S1, false);
 
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($not), ID($_NOT_))) {
+			if (cell->type.in(TW($not), TW($_NOT_))) {
 				auto sig_a = cell->getPort(TW::A);
 				auto &sig_y = cell->getPort(TW::Y);
 				sig_a.extend_u0(GetSize(sig_y), cell->hasParam(ID::A_SIGNED) && cell->parameters.at(ID::A_SIGNED).as_bool());
@@ -393,7 +393,7 @@ struct PropagateWorker
 		}
 
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($not), ID($_NOT_)))
+			if (cell->type.in(TW($not), TW($_NOT_)))
 				continue;
 			for (auto &conn : cell->connections()) {
 				if (!cell->output(conn.first))
@@ -402,7 +402,7 @@ struct PropagateWorker
 					sigmap.apply(bit);
 					if (replaced_clk_bits.count(bit))
 						log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n",
-								log_signal(bit), cell->module->design->twines.str(cell->meta_->name), cell->type.unescape(), module);
+								log_signal(bit), cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped(), module);
 				}
 			}
 		}
@@ -647,7 +647,7 @@ struct FormalFfPass : public Pass {
 							continue;
 						SigBit clk = sigmap(ff.sig_clk);
 						clk_bits[{clk, ff.pol_clk}].push_back(cell);
-					} else if (cell->type == ID($mem_v2)) {
+					} else if (cell->type == TW($mem_v2)) {
 						auto const &mem = memories.at(cell->name);
 						for (auto &rd_port : mem.rd_ports)
 							if (rd_port.clk_enable)
@@ -708,11 +708,11 @@ struct FormalFfPass : public Pass {
 					auto driver = *found->second.begin();
 
 					bool is_gate =
-					  pol_clk ? driver.cell->type.in(ID($and), ID($_AND_)) : driver.cell->type.in(ID($or), ID($_OR_));
+					  pol_clk ? driver.cell->type.in(TW($and), TW($_AND_)) : driver.cell->type.in(TW($or), TW($_OR_));
 
 					if (!is_gate) {
 						log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", module,
-							  driver.cell, driver.cell->type.unescape(), pol_clk ? "posedge" : "negedge",
+							  driver.cell, design->twines.unescaped_str(driver.cell->type), pol_clk ? "posedge" : "negedge",
 							  module, log_signal(SigSpec(clk)));
 
 						continue;
@@ -754,7 +754,7 @@ struct FormalFfPass : public Pass {
 							log_debug(
 							  "FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible type: %s\n",
 							  module, log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)),
-							  gate_driver.cell->type.unescape());
+							  design->twines.unescaped_str(gate_driver.cell->type));
 							continue;
 						}
 
@@ -782,7 +782,7 @@ struct FormalFfPass : public Pass {
 
 						for (auto clocked_cell : clocked_cells) {
 							log_debug("rewriting cell %s.%s (%s)\n", module, clocked_cell,
-								  clocked_cell->type.unescape());
+								  design->twines.unescaped_str(clocked_cell->type));
 
 							if (clocked_cell->is_builtin_ff()) {
 
@@ -794,7 +794,7 @@ struct FormalFfPass : public Pass {
 								ff.has_ce = true;
 								ff.sig_clk = gate_clock;
 								ff.emit();
-							} else if (clocked_cell->type == ID($mem_v2)) {
+							} else if (clocked_cell->type == TW($mem_v2)) {
 								auto &mem = memories.at(clocked_cell->name);
 								bool changed = false;
 								for (auto &rd_port : mem.rd_ports) {
@@ -855,7 +855,7 @@ struct FormalFfPass : public Pass {
 
 						if (ff.val_init != before) {
 							log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
-									module, cell, cell->type.unescape(),
+									module, cell, cell->type.unescaped(),
 									log_const(before), log_const(ff.val_init));
 							worker.initvals.set_init(ff.sig_q, ff.val_init);
 						}
@@ -868,7 +868,7 @@ struct FormalFfPass : public Pass {
 
 			for (auto cell : module->selected_cells())
 			{
-				if (flag_anyinit2ff && cell->type == ID($anyinit))
+				if (flag_anyinit2ff && cell->type == TW($anyinit))
 				{
 					FfData ff(&initvals, cell);
 					ff.remove();
@@ -895,7 +895,7 @@ struct FormalFfPass : public Pass {
 								cell, cell->type, module);
 					if (ff.has_aload || ff.has_arst || ff.has_sr)
 						log_error("Async inputs on %s (%s) from module %s, run async2sync first.\n",
-								cell, cell->type.unescape(), module);
+								cell, cell->type.unescaped(), module);
 
 					auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr;
 
@@ -912,7 +912,7 @@ struct FormalFfPass : public Pass {
 
 					if (!attr.empty() && attr != clk_polarity)
 						log_error("CLK %s on %s (%s) from module %s also used with opposite polarity, run clk2fflogic instead.\n",
-								clk_wire, cell, cell->type.unescape(), module);
+								clk_wire, cell, cell->type.unescaped(), module);
 
 					attr = clk_polarity;
 					clk_wire->set_bool_attribute(ID::keep);
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index a5c11e9c5..25063d844 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -139,7 +139,7 @@ struct FindReducedInputs
 			if (ez_cells.count(drv.first) == 0) {
 				satgen.setContext(&sigmap, "A");
 				if (!satgen.importCell(drv.first))
-					log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape());
+					log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, design->twines.unescaped_str(drv.first->type));
 				satgen.setContext(&sigmap, "B");
 				if (!satgen.importCell(drv.first))
 					log_abort();
@@ -256,7 +256,7 @@ struct PerformReduction
 			std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
 			if (celldone.count(drv.first) == 0) {
 				if (!satgen.importCell(drv.first))
-					log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape());
+					log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, design->twines.unescaped_str(drv.first->type));
 				celldone.insert(drv.first);
 			}
 			int max_child_depth = 0;
@@ -616,11 +616,11 @@ struct FreduceWorker
 				bits_full_total += w->width;
 			}
 		for (auto cell : module->cells()) {
-			if (ct.cell_known(cell->type)) {
+			if (ct.cell_known(cell->type_impl)) {
 				std::set<RTLIL::SigBit> inputs, outputs;
 				for (auto &port : cell->connections()) {
 					std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
-					if (ct.cell_output(cell->type, port.first))
+					if (ct.cell_output(cell->type_impl, port.first))
 						outputs.insert(bits.begin(), bits.end());
 					else
 						inputs.insert(bits.begin(), bits.end());
@@ -631,7 +631,7 @@ struct FreduceWorker
 				batches.push_back(outputs);
 				bits_full_total += outputs.size();
 			}
-			if (inv_mode && cell->type == ID($_NOT_))
+			if (inv_mode && cell->type == TW($_NOT_))
 				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(TW::A)), sigmap(cell->getPort(TW::Y))));
 		}
 
@@ -718,7 +718,7 @@ struct FreduceWorker
 				RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
 				RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE);
 				for (auto &port : drv->connections_)
-					if (ct.cell_output(drv->type, port.first))
+					if (ct.cell_output(drv->type_impl, port.first))
 						sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
 
 				if (grp[i].inverted)
@@ -727,7 +727,7 @@ struct FreduceWorker
 					{
 						inv_sig = module->addWire(NEW_TWINE);
 
-						RTLIL::Cell *inv_cell = module->addCell(NEW_TWINE, ID($_NOT_));
+						RTLIL::Cell *inv_cell = module->addCell(NEW_TWINE, TW($_NOT_));
 						inv_cell->setPort(TW::A, grp[0].bit);
 						inv_cell->setPort(TW::Y, inv_sig);
 					}
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 43ab0d34c..941c2e14d 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -128,7 +128,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 		log_cmd_error("No matching port in gold module was found for %s!\n", design->twines.str(gate_wire->meta_->name).c_str());
 	}
 
-	log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", miter_name.unescape(), gold_name.unescape(), gate_name.unescape());
+	log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", design->twines.unescaped_str(miter_name), design->twines.unescaped_str(gold_name), design->twines.unescaped_str(gate_name));
 
 	RTLIL::Module *miter_module = new RTLIL::Module;
 	miter_module->design = design;
@@ -184,7 +184,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 			{
 				RTLIL::SigSpec gold_x = miter_module->addWire(NEW_TWINE, GetSize(w_gold));
 				for (int i = 0; i < GetSize(w_gold); i++) {
-					RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
+					RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_TWINE, TW($eqx));
 					eqx_cell->parameters[ID::A_WIDTH] = 1;
 					eqx_cell->parameters[ID::B_WIDTH] = 1;
 					eqx_cell->parameters[ID::Y_WIDTH] = 1;
@@ -198,7 +198,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_TWINE, w_gold->width);
 				RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_TWINE, w_gate->width);
 
-				RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_TWINE, ID($or));
+				RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_TWINE, TW($or));
 				or_gold_cell->parameters[ID::A_WIDTH] = GetSize(w_gold);
 				or_gold_cell->parameters[ID::B_WIDTH] = GetSize(w_gold);
 				or_gold_cell->parameters[ID::Y_WIDTH] = GetSize(w_gold);
@@ -208,7 +208,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				or_gold_cell->setPort(TW::B, gold_x);
 				or_gold_cell->setPort(TW::Y, gold_masked);
 
-				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_TWINE, ID($or));
+				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_TWINE, TW($or));
 				or_gate_cell->parameters[ID::A_WIDTH] = GetSize(w_gate);
 				or_gate_cell->parameters[ID::B_WIDTH] = GetSize(w_gate);
 				or_gate_cell->parameters[ID::Y_WIDTH] = GetSize(w_gate);
@@ -218,7 +218,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				or_gate_cell->setPort(TW::B, gold_x);
 				or_gate_cell->setPort(TW::Y, gate_masked);
 
-				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
+				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, TW($eqx));
 				eq_cell->parameters[ID::A_WIDTH] = GetSize(w_gold);
 				eq_cell->parameters[ID::B_WIDTH] = GetSize(w_gate);
 				eq_cell->parameters[ID::Y_WIDTH] = 1;
@@ -231,7 +231,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 			}
 			else
 			{
-				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
+				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, TW($eqx));
 				eq_cell->parameters[ID::A_WIDTH] = GetSize(w_gold);
 				eq_cell->parameters[ID::B_WIDTH] = GetSize(w_gate);
 				eq_cell->parameters[ID::Y_WIDTH] = 1;
@@ -261,7 +261,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	}
 
 	if (all_conditions.size() != 1) {
-		RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_TWINE, ID($reduce_and));
+		RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_TWINE, TW($reduce_and));
 		reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size();
 		reduce_cell->parameters[ID::Y_WIDTH] = 1;
 		reduce_cell->parameters[ID::A_SIGNED] = 0;
@@ -271,7 +271,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	}
 
 	if (flag_make_assert) {
-		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_TWINE, ID($assert));
+		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_TWINE, TW($assert));
 		assert_cell->setPort(TW::A, all_conditions);
 		assert_cell->setPort(TW::EN, State::S1);
 	}
@@ -279,7 +279,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	RTLIL::Wire *w_trigger = miter_module->addWire(TW::trigger);
 	w_trigger->port_output = true;
 
-	RTLIL::Cell *not_cell = miter_module->addCell(NEW_TWINE, ID($not));
+	RTLIL::Cell *not_cell = miter_module->addCell(NEW_TWINE, TW($not));
 	not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
 	not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
 	not_cell->parameters[ID::Y_WIDTH] = w_trigger->width;
@@ -353,13 +353,13 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
 	vector<Cell*> cell_list = module->cells();
 	for (auto cell : cell_list)
 	{
-		if (!cell->type.in(ID($assert), ID($assume)))
+		if (!cell->type.in(TW($assert), TW($assume)))
 			continue;
 
 		SigBit is_active = module->Nex(NEW_TWINE, cell->getPort(TW::A), State::S1);
 		SigBit is_enabled = module->Eqx(NEW_TWINE, cell->getPort(TW::EN), State::S1);
 
-		if (cell->type == ID($assert)) {
+		if (cell->type == TW($assert)) {
 			assert_signals.append(module->And(NEW_TWINE, is_active, is_enabled));
 		} else {
 			assume_signals.append(module->And(NEW_TWINE, is_active, is_enabled));
diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index e1cf0b4a1..8c00973cc 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -558,7 +558,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 	if (opts.none) {
 		string str = "mutate";
 		if (!opts.ctrl_name.empty())
-			str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
+			str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
 		str += " -mode none";
 		if (filename.empty())
 			log("%s\n", str);
@@ -569,20 +569,20 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 	for (auto &entry : database) {
 		string str = "mutate";
 		if (!opts.ctrl_name.empty())
-			str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
+			str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
 		str += stringf(" -mode %s", entry.mode);
 		if (!entry.module.empty())
-			str += stringf(" -module %s", entry.module.unescape());
+			str += stringf(" -module %s", design->twines.unescaped_str(entry.module));
 		if (!entry.cell.empty())
-			str += stringf(" -cell %s", entry.cell.unescape());
+			str += stringf(" -cell %s", design->twines.unescaped_str(entry.cell));
 		if (!entry.port.empty())
-			str += stringf(" -port %s", entry.port.unescape());
+			str += stringf(" -port %s", design->twines.unescaped_str(entry.port));
 		if (entry.portbit >= 0)
 			str += stringf(" -portbit %d", entry.portbit);
 		if (entry.ctrlbit >= 0)
 			str += stringf(" -ctrlbit %d", entry.ctrlbit);
 		if (!entry.wire.empty())
-			str += stringf(" -wire %s", entry.wire.unescape());
+			str += stringf(" -wire %s", design->twines.unescaped_str(entry.wire));
 		if (entry.wirebit >= 0)
 			str += stringf(" -wirebit %d", entry.wirebit);
 		for (auto &s : entry.src)
@@ -600,7 +600,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
 
 	if (ctrl_wire == nullptr)
 	{
-		log("Adding ctrl port %s to module %s.\n", name.unescape(), module);
+		log("Adding ctrl port %s to module %s.\n", design->twines.unescaped_str(name), module);
 
 		ctrl_wire = module->addWire(name, width);
 		ctrl_wire->port_input = true;
@@ -652,13 +652,13 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
 
 	if (cell->input(opts.port))
 	{
-		log("Add input inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
+		log("Add input inverter at %s.%s.%s[%d].\n", module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
 		SigBit outbit = module->Not(NEW_TWINE, bit);
 		bit = mutate_ctrl_mux(module, opts, bit, outbit);
 	}
 	else
 	{
-		log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
+		log("Add output inverter at %s.%s.%s[%d].\n", module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
 		SigBit inbit = module->addWire(NEW_TWINE);
 		SigBit outbit = module->Not(NEW_TWINE, inbit);
 		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@@ -680,13 +680,13 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
 
 	if (cell->input(opts.port))
 	{
-		log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
+		log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
 		SigBit outbit = one ? State::S1 : State::S0;
 		bit = mutate_ctrl_mux(module, opts, bit, outbit);
 	}
 	else
 	{
-		log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
+		log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
 		SigBit inbit = module->addWire(NEW_TWINE);
 		SigBit outbit = one ? State::S1 : State::S0;
 		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@@ -709,13 +709,13 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
 
 	if (cell->input(opts.port))
 	{
-		log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
+		log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit, opts.ctrlbit);
 		SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_TWINE, bit, ctrl);
 		bit = mutate_ctrl_mux(module, opts, bit, outbit);
 	}
 	else
 	{
-		log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
+		log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit, opts.ctrlbit);
 		SigBit inbit = module->addWire(NEW_TWINE);
 		SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_TWINE, inbit, ctrl);
 		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@@ -947,26 +947,26 @@ struct MutatePass : public Pass {
 
 		Module *module = design->module(opts.module);
 		if (module == nullptr)
-			log_cmd_error("Module %s not found.\n", opts.module.unescape());
+			log_cmd_error("Module %s not found.\n", design->twines.unescaped_str(opts.module));
 
 		if (opts.cell.empty())
 			log_cmd_error("Missing -cell argument.\n");
 
 		Cell *cell = module->cell(opts.cell);
 		if (cell == nullptr)
-			log_cmd_error("Cell %s not found in module %s.\n", opts.cell.unescape(), opts.module.unescape());
+			log_cmd_error("Cell %s not found in module %s.\n", design->twines.unescaped_str(opts.cell), design->twines.unescaped_str(opts.module));
 
 		if (opts.port.empty())
 			log_cmd_error("Missing -port argument.\n");
 
 		if (!cell->hasPort(opts.port))
-			log_cmd_error("Port %s not found on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
+			log_cmd_error("Port %s not found on cell %s.%s.\n", design->twines.unescaped_str(opts.port), design->twines.unescaped_str(opts.module), design->twines.unescaped_str(opts.cell));
 
 		if (opts.portbit < 0)
 			log_cmd_error("Missing -portbit argument.\n");
 
 		if (GetSize(cell->getPort(opts.port)) <= opts.portbit)
-			log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
+			log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", design->twines.unescaped_str(opts.port), design->twines.unescaped_str(opts.module), design->twines.unescaped_str(opts.cell));
 
 		if (opts.mode == "inv") {
 			mutate_inv(design, opts);
@@ -982,7 +982,7 @@ struct MutatePass : public Pass {
 			log_cmd_error("Missing -ctrlbit argument.\n");
 
 		if (GetSize(cell->getPort(opts.port)) <= opts.ctrlbit)
-			log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
+			log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", design->twines.unescaped_str(opts.port), design->twines.unescaped_str(opts.module), design->twines.unescaped_str(opts.cell));
 
 		if (opts.mode == "cnot0" || opts.mode == "cnot1") {
 			mutate_cnot(design, opts, opts.mode == "cnot1");
diff --git a/passes/sat/recover_names.cc b/passes/sat/recover_names.cc
index e2c93df65..bba605579 100644
--- a/passes/sat/recover_names.cc
+++ b/passes/sat/recover_names.cc
@@ -641,8 +641,8 @@ struct RecoverNamesWorker {
                 for (auto gate_bit : gate_bits) {
                     if (solved_gate.count(gate_bit.bit))
                         continue;
-                    log_debug("   attempting to prove %s[%d] == %s%s[%d]\n", gold_bit.name.unescape(), gold_bit.bit,
-                        gate_bit.inverted ? "" : "!", gate_bit.bit.name.unescape(), gate_bit.bit.bit);
+                    log_debug("   attempting to prove %s[%d] == %s%s[%d]\n", design->twines.unescaped_str(gold_bit.name), gold_bit.bit,
+                        gate_bit.inverted ? "" : "!", design->twines.unescaped_str(gate_bit.bit.name), gate_bit.bit.bit);
                     if (!prove_equiv(gold_worker, gate_worker, gold_anchors, gate_anchors, gold_bit, gate_bit.bit, gate_bit.inverted))
                         continue;
                     log_debug("       success!\n");
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index b662f4974..29a9ae6f1 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -245,7 +245,7 @@ struct SatHelper
 			if (design->selected(module, cell)) {
 				if (satgen.importCell(cell, timestep)) {
 					for (auto &p : cell->connections())
-						if (ct.cell_output(cell->type, p.first))
+						if (ct.cell_output(cell->type_impl, p.first))
 							show_drivers.insert(sigmap(p.second), cell);
 					import_cell_counter++;
 				} else report_missing_model(ignore_unknown_cells, cell);
@@ -267,7 +267,7 @@ struct SatHelper
 			// Check for $anyinit cells that are forced to be defined
 			if (set_init_undef && satgen.def_formal)
 				for (auto cell : module->cells())
-					if (cell->type == ID($anyinit))
+					if (cell->type == TW($anyinit))
 						forced_def.append(sigmap(cell->getPort(TW::Q)));
 
 			for (auto wire : module->wires())
@@ -533,7 +533,7 @@ struct SatHelper
 				} else {
 					for (auto &d : drivers)
 					for (auto &p : d->connections()) {
-						if (d->type == ID($dff) && p.first == TW::CLK)
+						if (d->type == TW($dff) && p.first == TW::CLK)
 							continue;
 						if (d->type.begins_with("$_DFF_") && p.first == TW::C)
 							continue;
@@ -1408,7 +1408,7 @@ struct SatPass : public Pass {
 		if (show_regs) {
 			pool<Wire*> reg_wires;
 			for (auto cell : module->cells()) {
-				if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_"))
+				if (cell->type == TW($dff) || cell->type.begins_with("$_DFF_"))
 					for (auto bit : cell->getPort(TW::Q))
 						if (bit.wire)
 							reg_wires.insert(bit.wire);
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 59f20ff70..a241ce176 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -250,7 +250,7 @@ struct SimInstance
 
 		if (module->get_blackbox_attribute(true))
 			log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
-					  module->name.unescape(), hiername().c_str());
+					  design->twines.unescaped_str(module->name), hiername().c_str());
 
 		if (module->has_processes())
 			log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
@@ -275,9 +275,9 @@ struct SimInstance
 			}
 
 			if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
-				fstHandle id = shared->fst->getHandle(scope + "." + wire->name.unescape());
+				fstHandle id = shared->fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
 				if (id==0 && wire->name.isPublic())
-					log_warning("Unable to find wire %s in input file.\n", (scope + "." + wire->name.unescape()));
+					log_warning("Unable to find wire %s in input file.\n", (scope + "." + design->twines.unescaped_str(wire->name)));
 				fst_handles[wire] = id;
 			}
 
@@ -329,7 +329,7 @@ struct SimInstance
 					}
 			}
 
-			if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
+			if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
 				FfData ff_data(nullptr, cell);
 				ff_state_t ff;
 				ff.past_d = Const(State::Sx, ff_data.width);
@@ -354,13 +354,13 @@ struct SimInstance
 					fst_memories[name] = shared->fst->getMemoryHandles(scope + "." + RTLIL::unescape_id(name));
 			}
 
-			if (cell->type.in(ID($assert), ID($cover), ID($assume)))
+			if (cell->type.in(TW($assert), TW($cover), TW($assume)))
 				formal_database.insert(cell);
 
-			if (cell->type == ID($initstate))
+			if (cell->type == TW($initstate))
 				initstate_database.insert(cell);
 
-			if (cell->type == ID($print)) {
+			if (cell->type == TW($print)) {
 				print_database.emplace_back();
 				auto &print = print_database.back();
 				print.cell = cell;
@@ -413,7 +413,7 @@ struct SimInstance
 	std::string hiername() const
 	{
 		if (instance != nullptr)
-			return parent->hiername() + "." + instance->name.unescape();
+			return parent->hiername() + "." + design->twines.unescaped_str(instance->name);
 
 		return module->design->twines.str(module->meta_->name);
 	}
@@ -520,7 +520,7 @@ struct SimInstance
 	{
 		auto &state = mem_database[memid];
 		if (offset >= state.mem->size * state.mem->width)
-			log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, memid.unescape());
+			log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, design->twines.unescaped_str(memid));
 		if (state.data[offset] != data) {
 			state.data.set(offset, data);
 			dirty_memories.insert(memid);
@@ -573,7 +573,7 @@ struct SimInstance
 			if (has_y) sig_y = cell->getPort(TW::Y);
 
 			if (shared->debug)
-				log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescape());
+				log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescaped());
 
 			bool err = false;
 			RTLIL::Const eval_state;
@@ -593,19 +593,19 @@ struct SimInstance
 				err = true;
 
 			if (err)
-				log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
+				log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
 			else
 				set_state(sig_y, eval_state);
 			return;
 		}
 
-		if (cell->type == ID($print))
+		if (cell->type == TW($print))
 			return;
 
-		if (cell->type.in(ID($input_port), ID($output_port), ID($public), ID($connect)))
+		if (cell->type.in(TW($input_port), TW($output_port), TW($public), TW($connect)))
 			return;
 
-		log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
+		log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
 	}
 
 	void update_memory(IdString id) {
@@ -619,7 +619,7 @@ struct SimInstance
 			Const data = Const(State::Sx, mem.width << port.wide_log2);
 
 			if (port.clk_enable)
-				log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, mem.memid.unescape());
+				log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, design->twines.unescaped_str(mem.memid));
 
 			if (addr.is_fully_def()) {
 				int addr_int = addr.as_int();
@@ -937,17 +937,17 @@ struct SimInstance
 				State a = get_state(cell->getPort(TW::A))[0];
 				State en = get_state(cell->getPort(TW::EN))[0];
 
-				if (en == State::S1 && (cell->type == ID($cover) ? a == State::S1 : a != State::S1)) {
+				if (en == State::S1 && (cell->type == TW($cover) ? a == State::S1 : a != State::S1)) {
 					shared->triggered_assertions.emplace_back(shared->step, this, cell);
 				}
 
-				if (cell->type == ID($cover) && en == State::S1 && a == State::S1)
+				if (cell->type == TW($cover) && en == State::S1 && a == State::S1)
 					log("Cover %s.%s (%s) reached.\n", hiername(), cell, label);
 
-				if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
+				if (cell->type == TW($assume) && en == State::S1 && a != State::S1)
 					log("Assumption %s.%s (%s) failed.\n", hiername(), cell, label);
 
-				if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
+				if (cell->type == TW($assert) && en == State::S1 && a != State::S1) {
 					log_cell_w_hierarchy("Failed assertion", cell);
 					if (shared->serious_asserts)
 						log_error("Assertion %s.%s (%s) failed.\n", hiername(), cell, label);
@@ -1085,7 +1085,7 @@ struct SimInstance
 				for (auto name : hdlname)
 					enter_scope("\\" + name);
 			} else {
-				signal_name = memid.unescape();
+				signal_name = design->twines.unescaped_str(memid);
 			}
 
 			for (auto &trace_index : trace_mem.second) {
@@ -1199,7 +1199,7 @@ struct SimInstance
 	{
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($anyseq))) {
+			if (cell->type.in(TW($anyseq))) {
 				SigSpec sig_y = sigmap(cell->getPort(TW::Y));
 				if (sig_y.is_wire()) {
 					bool found = false;
@@ -1212,7 +1212,7 @@ struct SimInstance
 						}
 					}
 					if (!found)
-						log_error("Unable to find required '%s' signal in file\n",(scope + "." + sig_y.as_wire()->name.unescape()));
+						log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(sig_y.as_wire()->name)));
 				}
 			}
 		}
@@ -1412,7 +1412,7 @@ struct SimWorker : SimShared
 			Wire *w = top->module->wire(portname);
 
 			if (w == nullptr)
-				log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
+				log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
 
 			top->set_state(w, value);
 		}
@@ -1495,24 +1495,24 @@ struct SimWorker : SimShared
 		{
 			Wire *w = topmod->wire(portname);
 			if (!w)
-				log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
+				log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
 			if (!w->port_input)
-				log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
-			fstHandle id = fst->getHandle(scope + "." + portname.unescape());
+				log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
+			fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
 			if (id==0)
-				log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
+				log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
 			fst_clock.push_back(id);
 		}
 		for (auto portname : clockn)
 		{
 			Wire *w = topmod->wire(portname);
 			if (!w)
-				log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
+				log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
 			if (!w->port_input)
-				log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
-			fstHandle id = fst->getHandle(scope + "." + portname.unescape());
+				log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
+			fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
 			if (id==0)
-				log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
+				log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
 			fst_clock.push_back(id);
 		}
 
@@ -1520,9 +1520,9 @@ struct SimWorker : SimShared
 
 		for (auto wire : topmod->wires()) {
 			if (wire->port_input) {
-				fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
+				fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
 				if (id==0)
-					log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
+					log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
 				top->fst_inputs[wire] = id;
 			}
 		}
@@ -1837,7 +1837,7 @@ struct SimWorker : SimShared
 							Cell *c = topmod->cell(found);
 							if (!c)
 								log_warning("Wire/cell %s not present in module %s\n", unescaped_s, topmod);
-							else if (c->type.in(ID($anyconst), ID($anyseq))) {
+							else if (c->type.in(TW($anyconst), TW($anyseq))) {
 								SigSpec sig_y= c->getPort(TW::Y);
 								if ((int)parts[1].size() != GetSize(sig_y))
 									log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y));
@@ -2084,13 +2084,13 @@ struct SimWorker : SimShared
 		json.entry("version", "Yosys sim summary");
 		json.entry("generator", yosys_maybe_version());
 		json.entry("steps", step);
-		json.entry("top", top->module->name.unescape());
+		json.entry("top", design->twines.unescaped_str(top->module->name));
 		json.name("assertions");
 		json.begin_array();
 		for (auto &assertion : triggered_assertions) {
 			json.begin_object();
 			json.entry("step", assertion.step);
-			json.entry("type", assertion.cell->type.unescape());
+			json.entry("type", design->twines.unescaped_str(assertion.cell->type));
 			json.entry("path", assertion.instance->witness_full_path(assertion.cell));
 			auto src = assertion.cell->get_src_attribute();
 			if (!src.empty()) {
@@ -2155,12 +2155,12 @@ struct SimWorker : SimShared
 		{
 			Wire *w = topmod->wire(portname);
 			if (!w)
-				log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
+				log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
 			if (!w->port_input)
-				log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
-			fstHandle id = fst->getHandle(scope + "." + portname.unescape());
+				log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
+			fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
 			if (id==0)
-				log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
+				log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
 			fst_clock.push_back(id);
 			clocks[w] = id;
 		}
@@ -2168,12 +2168,12 @@ struct SimWorker : SimShared
 		{
 			Wire *w = topmod->wire(portname);
 			if (!w)
-				log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
+				log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
 			if (!w->port_input)
-				log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
-			fstHandle id = fst->getHandle(scope + "." + portname.unescape());
+				log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
+			fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
 			if (id==0)
-				log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
+				log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
 			fst_clock.push_back(id);
 			clocks[w] = id;
 		}
@@ -2183,9 +2183,9 @@ struct SimWorker : SimShared
 		std::map<Wire*,fstHandle> outputs;
 
 		for (auto wire : topmod->wires()) {
-			fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
+			fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
 			if (id==0 && (wire->port_input || wire->port_output))
-				log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
+				log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
 			if (wire->port_input)
 				if (clocks.find(wire)==clocks.end())
 					inputs[wire] = id;
@@ -2366,7 +2366,7 @@ struct VCDWriter : public OutputWriter
 			vcdfile << stringf("$timescale %s $end\n", worker->timescale);
 
 		worker->top->write_output_header(
-			[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", name.unescape()); },
+			[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", design->twines.unescaped_str(name)); },
 			[this]() { vcdfile << stringf("$upscope $end\n");},
 			[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
 				if (!use_signal.at(id)) return;
@@ -2432,7 +2432,7 @@ struct FSTWriter : public OutputWriter
 		fstWriterSetRepackOnClose(fstfile, 1);
 	   
 	   	worker->top->write_output_header(
-			[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); },
+			[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, design->twines.unescaped_str(stringf("%s",name)).c_str(), nullptr); },
 			[this]() { fstWriterSetUpscope(fstfile); },
 			[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
 				if (!use_signal.at(id)) return;
@@ -2495,7 +2495,7 @@ struct AIWWriter : public OutputWriter
 			RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
 			Wire *w = worker->top->module->wire(escaped_s);
 			if (!w)
-				log_error("Wire %s not present in module %s\n",escaped_s.unescape(),worker->top->module);
+				log_error("Wire %s not present in module design->twines.unescaped_str(%s\n",escaped_s),worker->top->module);
 			if (index < w->start_offset || index > w->start_offset + w->width)
 				log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
 			if (type == "input") {
diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc
index 744a63673..f387aabc2 100644
--- a/passes/sat/synthprop.cc
+++ b/passes/sat/synthprop.cc
@@ -64,7 +64,7 @@ void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &traci
 	tracing_data[mod] = TrackingItem();
 	int cnt = 0;
 	for (auto cell : mod->cells()) {
-		if (cell->type == ID($assert)) {
+		if (cell->type == TW($assert)) {
 			log("%*sFound assert %s..\n", 2*(depth+1), "", cell);
 			tracing_data[mod].assertion_cells.emplace(cell);
 			if (!or_outputs) {
@@ -93,7 +93,7 @@ void SynthPropWorker::run()
 		log_error("Module is not TOP module\n");
 
 	TrackingData tracing_data;
-	tracing(module, 0, tracing_data, module->name.unescape());
+	tracing(module, 0, tracing_data, design->twines.unescaped_str(module->name));
 
 	for (auto &data : tracing_data) {
 		if (data.second.names.size() == 0) continue;
@@ -112,7 +112,7 @@ void SynthPropWorker::run()
 		}
 		pool<Wire*> connected;
 		for (auto cell : data.second.assertion_cells) {
-			if (cell->type == ID($assert)) {
+			if (cell->type == TW($assert)) {
 				RTLIL::Wire *neg_wire = data.first->addWire(NEW_TWINE);
 				RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE);
 				data.first->addNot(NEW_ID, cell->getPort(TW::A), neg_wire);
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index b4085f17e..5982a6a34 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -474,7 +474,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
 		return true;
 	}
 
-	if (cell->type.in(ID($_BUF_), ID($_NOT_)))
+	if (cell->type.in(TW($_BUF_), TW($_NOT_)))
 	{
 		RTLIL::SigSpec sig_a = cell->getPort(TW::A);
 		RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
@@ -482,13 +482,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_y);
 
-		map_signal(assign_map, sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(assign_map, sig_a));
+		map_signal(assign_map, sig_y, cell->type == TW($_BUF_) ? G(BUF) : G(NOT), map_signal(assign_map, sig_a));
 
 		module->remove(cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
+	if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
 	{
 		RTLIL::SigSpec sig_a = cell->getPort(TW::A);
 		RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@@ -501,21 +501,21 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
 		int mapped_a = map_signal(assign_map, sig_a);
 		int mapped_b = map_signal(assign_map, sig_b);
 
-		if (cell->type == ID($_AND_))
+		if (cell->type == TW($_AND_))
 			map_signal(assign_map, sig_y, G(AND), mapped_a, mapped_b);
-		else if (cell->type == ID($_NAND_))
+		else if (cell->type == TW($_NAND_))
 			map_signal(assign_map, sig_y, G(NAND), mapped_a, mapped_b);
-		else if (cell->type == ID($_OR_))
+		else if (cell->type == TW($_OR_))
 			map_signal(assign_map, sig_y, G(OR), mapped_a, mapped_b);
-		else if (cell->type == ID($_NOR_))
+		else if (cell->type == TW($_NOR_))
 			map_signal(assign_map, sig_y, G(NOR), mapped_a, mapped_b);
-		else if (cell->type == ID($_XOR_))
+		else if (cell->type == TW($_XOR_))
 			map_signal(assign_map, sig_y, G(XOR), mapped_a, mapped_b);
-		else if (cell->type == ID($_XNOR_))
+		else if (cell->type == TW($_XNOR_))
 			map_signal(assign_map, sig_y, G(XNOR), mapped_a, mapped_b);
-		else if (cell->type == ID($_ANDNOT_))
+		else if (cell->type == TW($_ANDNOT_))
 			map_signal(assign_map, sig_y, G(ANDNOT), mapped_a, mapped_b);
-		else if (cell->type == ID($_ORNOT_))
+		else if (cell->type == TW($_ORNOT_))
 			map_signal(assign_map, sig_y, G(ORNOT), mapped_a, mapped_b);
 		else
 			log_abort();
@@ -524,7 +524,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
 		return true;
 	}
 
-	if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
+	if (cell->type.in(TW($_MUX_), TW($_NMUX_)))
 	{
 		RTLIL::SigSpec sig_a = cell->getPort(TW::A);
 		RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@@ -540,13 +540,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
 		int mapped_b = map_signal(assign_map, sig_b);
 		int mapped_s = map_signal(assign_map, sig_s);
 
-		map_signal(assign_map, sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
+		map_signal(assign_map, sig_y, cell->type == TW($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
 
 		module->remove(cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
+	if (cell->type.in(TW($_AOI3_), TW($_OAI3_)))
 	{
 		RTLIL::SigSpec sig_a = cell->getPort(TW::A);
 		RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@@ -562,13 +562,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
 		int mapped_b = map_signal(assign_map, sig_b);
 		int mapped_c = map_signal(assign_map, sig_c);
 
-		map_signal(assign_map, sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
+		map_signal(assign_map, sig_y, cell->type == TW($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
 
 		module->remove(cell);
 		return true;
 	}
 
-	if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
+	if (cell->type.in(TW($_AOI4_), TW($_OAI4_)))
 	{
 		RTLIL::SigSpec sig_a = cell->getPort(TW::A);
 		RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@@ -587,7 +587,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
 		int mapped_c = map_signal(assign_map, sig_c);
 		int mapped_d = map_signal(assign_map, sig_d);
 
-		map_signal(assign_map, sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
+		map_signal(assign_map, sig_y, cell->type == TW($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
 
 		module->remove(cell);
 		return true;
@@ -1481,42 +1481,42 @@ void emit_global_input_files(const AbcConfig &config)
 			log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
 		fprintf(f, "GATE ZERO    1 Y=CONST0;\n");
 		fprintf(f, "GATE ONE     1 Y=CONST1;\n");
-		fprintf(f, "GATE BUF    %d Y=A;                  PIN * NONINV  1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
-		fprintf(f, "GATE NOT    %d Y=!A;                 PIN * INV     1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
+		fprintf(f, "GATE BUF    %d Y=A;                  PIN * NONINV  1 999 1 0 1 0\n", cell_cost.at(TW($_BUF_)));
+		fprintf(f, "GATE NOT    %d Y=!A;                 PIN * INV     1 999 1 0 1 0\n", cell_cost.at(TW($_NOT_)));
 		if (config.enabled_gates.count("AND"))
-			fprintf(f, "GATE AND    %d Y=A*B;                PIN * NONINV  1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
+			fprintf(f, "GATE AND    %d Y=A*B;                PIN * NONINV  1 999 1 0 1 0\n", cell_cost.at(TW($_AND_)));
 		if (config.enabled_gates.count("NAND"))
-			fprintf(f, "GATE NAND   %d Y=!(A*B);             PIN * INV     1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
+			fprintf(f, "GATE NAND   %d Y=!(A*B);             PIN * INV     1 999 1 0 1 0\n", cell_cost.at(TW($_NAND_)));
 		if (config.enabled_gates.count("OR"))
-			fprintf(f, "GATE OR     %d Y=A+B;                PIN * NONINV  1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
+			fprintf(f, "GATE OR     %d Y=A+B;                PIN * NONINV  1 999 1 0 1 0\n", cell_cost.at(TW($_OR_)));
 		if (config.enabled_gates.count("NOR"))
-			fprintf(f, "GATE NOR    %d Y=!(A+B);             PIN * INV     1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
+			fprintf(f, "GATE NOR    %d Y=!(A+B);             PIN * INV     1 999 1 0 1 0\n", cell_cost.at(TW($_NOR_)));
 		if (config.enabled_gates.count("XOR"))
-			fprintf(f, "GATE XOR    %d Y=(A*!B)+(!A*B);      PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
+			fprintf(f, "GATE XOR    %d Y=(A*!B)+(!A*B);      PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_XOR_)));
 		if (config.enabled_gates.count("XNOR"))
-			fprintf(f, "GATE XNOR   %d Y=(A*B)+(!A*!B);      PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
+			fprintf(f, "GATE XNOR   %d Y=(A*B)+(!A*!B);      PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_XNOR_)));
 		if (config.enabled_gates.count("ANDNOT"))
-			fprintf(f, "GATE ANDNOT %d Y=A*!B;               PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
+			fprintf(f, "GATE ANDNOT %d Y=A*!B;               PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_ANDNOT_)));
 		if (config.enabled_gates.count("ORNOT"))
-			fprintf(f, "GATE ORNOT  %d Y=A+!B;               PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
+			fprintf(f, "GATE ORNOT  %d Y=A+!B;               PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_ORNOT_)));
 		if (config.enabled_gates.count("AOI3"))
-			fprintf(f, "GATE AOI3   %d Y=!((A*B)+C);         PIN * INV     1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
+			fprintf(f, "GATE AOI3   %d Y=!((A*B)+C);         PIN * INV     1 999 1 0 1 0\n", cell_cost.at(TW($_AOI3_)));
 		if (config.enabled_gates.count("OAI3"))
-			fprintf(f, "GATE OAI3   %d Y=!((A+B)*C);         PIN * INV     1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
+			fprintf(f, "GATE OAI3   %d Y=!((A+B)*C);         PIN * INV     1 999 1 0 1 0\n", cell_cost.at(TW($_OAI3_)));
 		if (config.enabled_gates.count("AOI4"))
-			fprintf(f, "GATE AOI4   %d Y=!((A*B)+(C*D));     PIN * INV     1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
+			fprintf(f, "GATE AOI4   %d Y=!((A*B)+(C*D));     PIN * INV     1 999 1 0 1 0\n", cell_cost.at(TW($_AOI4_)));
 		if (config.enabled_gates.count("OAI4"))
-			fprintf(f, "GATE OAI4   %d Y=!((A+B)*(C+D));     PIN * INV     1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
+			fprintf(f, "GATE OAI4   %d Y=!((A+B)*(C+D));     PIN * INV     1 999 1 0 1 0\n", cell_cost.at(TW($_OAI4_)));
 		if (config.enabled_gates.count("MUX"))
-			fprintf(f, "GATE MUX    %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
+			fprintf(f, "GATE MUX    %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_MUX_)));
 		if (config.enabled_gates.count("NMUX"))
-			fprintf(f, "GATE NMUX   %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
+			fprintf(f, "GATE NMUX   %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_NMUX_)));
 		if (config.map_mux4)
-			fprintf(f, "GATE MUX4   %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
+			fprintf(f, "GATE MUX4   %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(TW($_MUX_)));
 		if (config.map_mux8)
-			fprintf(f, "GATE MUX8   %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
+			fprintf(f, "GATE MUX8   %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(TW($_MUX_)));
 		if (config.map_mux16)
-			fprintf(f, "GATE MUX16  %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
+			fprintf(f, "GATE MUX16  %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(TW($_MUX_)));
 		fclose(f);
 	}
 }
@@ -1584,7 +1584,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 				continue;
 			}
 			if (c->type == ID(NOT)) {
-				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_NOT_));
 				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
 				for (auto name : {ID::A, ID::Y}) {
 					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@@ -1614,7 +1614,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 				continue;
 			}
 			if (c->type == ID(MUX4)) {
-				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX4_));
 				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
 				for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
 					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@@ -1624,7 +1624,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 				continue;
 			}
 			if (c->type == ID(MUX8)) {
-				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX8_));
 				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
 				for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
 					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@@ -1634,7 +1634,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 				continue;
 			}
 			if (c->type == ID(MUX16)) {
-				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX16_));
 				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
 				for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
 						ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
@@ -1754,7 +1754,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 			continue;
 		}
 
-		if (c->type == ID($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
+		if (c->type == TW($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
 			SigSpec my_a = module->wire(remap_name(c->getPort(TW::A).as_wire()->name));
 			SigSpec my_y = module->wire(remap_name(c->getPort(TW::Y).as_wire()->name));
 			connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
@@ -2503,11 +2503,11 @@ struct AbcPass : public Pass {
 					if (bit.wire != nullptr) {
 						cell_to_bit[cell].insert(bit);
 						bit_to_cell[bit].insert(cell);
-						if (ct.cell_input(cell->type, conn.first)) {
+						if (ct.cell_input(cell->type_impl, conn.first)) {
 							cell_to_bit_up[cell].insert(bit);
 							bit_to_cell_down[bit].insert(cell);
 						}
-						if (ct.cell_output(cell->type, conn.first)) {
+						if (ct.cell_output(cell->type_impl, conn.first)) {
 							cell_to_bit_down[cell].insert(bit);
 							bit_to_cell_up[bit].insert(cell);
 						}
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 646811e54..9a3ad5bfd 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -48,7 +48,7 @@ void check(RTLIL::Design *design, bool dff_mode)
 			auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), RTLIL::IdString(m->name)));
 			if (!r.second)
 				log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
-						m, id, r.first->second.unescape());
+						m, id, design->twines.unescaped_str(r.first->second));
 		}
 
 		// Make carry in the last PI, and carry out the last PO
@@ -89,13 +89,13 @@ void check(RTLIL::Design *design, bool dff_mode)
 
 	if (dff_mode) {
 		static pool<IdString> unsupported{
-			ID($adff), ID($dlatch), ID($dlatchsr), ID($sr),
-			ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
-			ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
-			ID($_DLATCH_N_), ID($_DLATCH_P_),
-			ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
-			ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
-			ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
+			TW($adff), TW($dlatch), TW($dlatchsr), TW($sr),
+			TW($_DFF_NN0_), TW($_DFF_NN1_), TW($_DFF_NP0_), TW($_DFF_NP1_),
+			TW($_DFF_PN0_), TW($_DFF_PN1_), TW($_DFF_PP0_), TW($_DFF_PP1_),
+			TW($_DLATCH_N_), TW($_DLATCH_P_),
+			TW($_DLATCHSR_NNN_), TW($_DLATCHSR_NNP_), TW($_DLATCHSR_NPN_), TW($_DLATCHSR_NPP_),
+			TW($_DLATCHSR_PNN_), TW($_DLATCHSR_PNP_), TW($_DLATCHSR_PPN_), TW($_DLATCHSR_PPP_),
+			TW($_SR_NN_), TW($_SR_NP_), TW($_SR_PN_), TW($_SR_PP_)
 		};
 		for (auto module : design->selected_modules())
 			for (auto cell : module->cells()) {
@@ -120,14 +120,14 @@ void check(RTLIL::Design *design, bool dff_mode)
 				if (!derived_module->get_bool_attribute(ID::abc9_flop))
 					continue;
 				if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
-					log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", derived_type.unescape());
+					log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", design->twines.unescaped_str(derived_type));
 
 				if (derived_module->has_processes())
 					Pass::call_on_module(design, derived_module, "proc -noopt");
 
 				bool found = false;
 				for (auto derived_cell : derived_module->cells()) {
-					if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
+					if (derived_cell->type.in(TW($dff), TW($_DFF_N_), TW($_DFF_P_))) {
 						if (found)
 							log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", derived_module);
 						found = true;
@@ -136,13 +136,13 @@ void check(RTLIL::Design *design, bool dff_mode)
 						log_assert(GetSize(Q.wire) == 1);
 
 						if (!Q.wire->port_output)
-							log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", derived_module, derived_cell->type.unescape());
+							log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
 
 						Const init = Q.wire->attributes.at(ID::init, State::Sx);
 						log_assert(GetSize(init) == 1);
 					}
 					else if (unsupported.count(derived_cell->type))
-						log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", derived_module, derived_cell->type.unescape());
+						log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
 				}
 			}
 	}
@@ -182,7 +182,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 			else {
 				bool has_timing = false;
 				for (auto derived_cell : derived_module->cells()) {
-					if (derived_cell->type.in(ID($specify2), ID($specify3), ID($specrule))) {
+					if (derived_cell->type.in(TW($specify2), TW($specify3), TW($specrule))) {
 						// If the module contains timing; then we potentially care about deriving its content too,
 						// as timings (or associated port widths) could be dependent on parameters.
 						has_timing = true;
@@ -208,7 +208,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 
 				if (derived_module->get_bool_attribute(ID::abc9_flop)) {
 					for (auto derived_cell : derived_module->cells())
-						if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
+						if (derived_cell->type.in(TW($dff), TW($_DFF_N_), TW($_DFF_P_))) {
 							SigBit Q = derived_cell->getPort(TW::Q);
 							Const init = Q.wire->attributes.at(ID::init, State::Sx);
 							log_assert(GetSize(init) == 1);
@@ -216,7 +216,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 							// Block sequential synthesis on cells with (* init *) != 1'b0
 							//   because ABC9 doesn't support them
 							if (init != State::S0) {
-								log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", derived_module, derived_cell->type.unescape());
+								log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
 								derived_module->set_bool_attribute(ID::abc9_flop, false);
 							}
 							break;
@@ -344,7 +344,7 @@ void prep_bypass(RTLIL::Design *design)
 				// For these new input ports driven by the replaced
 				//   cell, then create a new simple-path specify entry:
 				//     (input => output) = 0
-				auto specify = bypass_module->addCell(NEW_TWINE, ID($specify2));
+				auto specify = bypass_module->addCell(NEW_TWINE, TW($specify2));
 				specify->setPort(TW::EN, State::S1);
 				specify->setPort(TW::SRC, src);
 				specify->setPort(TW::DST, dst);
@@ -369,7 +369,7 @@ void prep_bypass(RTLIL::Design *design)
 			//   module ports; create new input port if one doesn't
 			//   already exist
 			for (auto cell : inst_module->cells()) {
-				if (cell->type != ID($specify2))
+				if (cell->type != TW($specify2))
 					continue;
 				auto EN = cell->getPort(TW::EN).as_bit();
 				SigBit newEN;
@@ -454,7 +454,7 @@ void prep_bypass(RTLIL::Design *design)
 
 void prep_dff(RTLIL::Design *design)
 {
-	auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection::EmptySelection(design)));
+	auto r = design->selection_vars.insert(std::make_pair(TW($abc9_flops), RTLIL::Selection::EmptySelection(design)));
 	auto &modules_sel = r.first->second;
 
 	for (auto module : design->selected_modules())
@@ -473,7 +473,7 @@ void prep_dff(RTLIL::Design *design)
 				// be instantiating the derived module which will have had any parameters constant-propagated.
 				// This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
 				// Please file a bug report!
-				log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
+				log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
 			}
 			modules_sel.select(inst_module);
 		}
@@ -490,13 +490,13 @@ void prep_dff_submod(RTLIL::Design *design)
 			continue;
 
 		for (auto cell : module->cells())
-			if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
+			if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_))) {
 				log_assert(!dff_cell);
 				dff_cell = cell;
 				Q = cell->getPort(TW::Q);
 				log_assert(GetSize(Q.wire) == 1);
 			}
-			else if (cell->type.in(ID($specify3), ID($specrule)))
+			else if (cell->type.in(TW($specify3), TW($specrule)))
 				specify_cells.emplace_back(cell);
 		log_assert(dff_cell);
 
@@ -603,7 +603,7 @@ void break_scc(RTLIL::Module *module)
 
 	if (!I.empty())
 	{
-		auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
+		auto cell = module->addCell(NEW_TWINE, TW($__ABC9_SCC_BREAKER));
 		log_assert(GetSize(I) == GetSize(O));
 		cell->setParam(ID::WIDTH, GetSize(I));
 		cell->setPort(TW::I, std::move(I));
@@ -625,7 +625,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 		}
 
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($_AND_), ID($_NOT_), ID($_DFF_N_), ID($_DFF_P_)))
+			if (cell->type.in(TW($_AND_), TW($_NOT_), TW($_DFF_N_), TW($_DFF_P_)))
 				continue;
 			log_assert(!cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
 
@@ -657,7 +657,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 	// Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
 	//   (or bypassed white-boxes with required times)
 	dict<int, IdString> box_cache;
-	Module *delay_module = design->module(ID($__ABC9_DELAY));
+	Module *delay_module = design->module(TW($__ABC9_DELAY));
 	log_assert(delay_module);
 	for (auto cell : cells) {
 		auto module = cell->module;
@@ -668,7 +668,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 			auto port_wire = inst_module->wire(i.first.name);
 			if (!port_wire)
 				log_error("Port %s in cell %s (type %s) from module %s does not actually exist",
-						i.first.name.unescape(), cell, cell->type.unescape(), module);
+						i.first.name.unescape(), cell, cell->type.unescaped(), module);
 			log_assert(port_wire->port_input);
 
 			auto d = i.second.first;
@@ -687,7 +687,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 			if (ys_debug(1)) {
 				static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
 				if (seen.emplace(cell->type, i.first).second) log("%s.%s[%d] abc9_required = %d\n",
-						cell->type.unescape(), i.first.name.unescape(), offset, d);
+						cell->type.unescape(), design->twines.unescaped_str(i.first.name), offset, d);
 			}
 #endif
 			auto r = box_cache.insert(d);
@@ -714,7 +714,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	dict<IdString, std::vector<IdString>> box_ports;
 
 	for (auto cell : module->cells()) {
-		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+		if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
 			continue;
 		if (cell->has_keep_attr())
 			continue;
@@ -759,7 +759,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 		dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+			if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
 				continue;
 			if (cell->has_keep_attr())
 				continue;
@@ -768,7 +768,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 			bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
 			if (abc9_flop && !dff)
 				continue;
-			if (!(inst_module && inst_module->get_bool_attribute(ID::abc9_box)) && !yosys_celltypes.cell_known(cell->type))
+			if (!(inst_module && inst_module->get_bool_attribute(ID::abc9_box)) && !yosys_celltypes.cell_known(cell->type_impl))
 				continue;
 
 			// TODO: Speed up toposort -- we care about box ordering only
@@ -828,7 +828,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 			}
 
 		if (!I.empty()) {
-			auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
+			auto cell = module->addCell(NEW_TWINE, TW($__ABC9_SCC_BREAKER));
 			log_assert(GetSize(I) == GetSize(O));
 			cell->setParam(ID::WIDTH, GetSize(I));
 			cell->setPort(TW::I, std::move(I));
@@ -847,7 +847,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 			for (auto cell_name : it) {
 				auto cell = module->cell(cell_name);
 				log_assert(cell);
-				log("\t%s (%s @ %s)\n", cell, cell->type.unescape(), cell->get_src_attribute());
+				log("\t%s (%s @ %s)\n", cell, cell->type.unescaped(), cell->get_src_attribute());
 			}
 		}
 	}
@@ -881,7 +881,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 			// be instantiating the derived module which will have had any parameters constant-propagated.
 			// This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
 			// Please file a bug report!
-			log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", cell_name.unescape(), cell->type.unescape());
+			log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", design->twines.unescaped_str(cell_name), cell->type.unescaped());
 		}
 		log_assert(box_module->get_blackbox_attribute());
 
@@ -916,7 +916,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 						}
 					}
 					else if (w->port_output)
-						conn = holes_module->addWire(stringf("%s.%s", cell->type, port_name.unescape()), GetSize(w));
+						conn = holes_module->addWire(stringf("%s.%s", cell->type, design->twines.unescaped_str(port_name)), GetSize(w));
 				}
 			}
 			else // box_module is a blackbox
@@ -928,7 +928,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 			log_assert(w);
 			if (!w->port_output)
 				continue;
-			Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, port_name.unescape()), GetSize(w));
+			Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, design->twines.unescaped_str(port_name)), GetSize(w));
 			holes_wire->port_output = true;
 			holes_wire->port_id = port_id++;
 			holes_module->ports.push_back(holes_wire->name);
@@ -980,9 +980,9 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 		auto r = table.emplace(K, entry);
 		if (!r.second) {
 			if (r.first->second.area != entry.area)
-				log_error("Modules '%s' and '%s' have conflicting (* abc9_lut *) values.\n", module, r.first->second.name.unescape());
+				log_error("Modules '%s' and '%s' have conflicting (* abc9_lut *) values.\n", module, design->twines.unescaped_str(r.first->second.name));
 			if (r.first->second.delays != entry.delays)
-				log_error("Modules '%s' and '%s' have conflicting specify entries.\n", module, r.first->second.name.unescape());
+				log_error("Modules '%s' and '%s' have conflicting specify entries.\n", module, design->twines.unescaped_str(r.first->second.name));
 		}
 	}
 
@@ -1001,7 +1001,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 		ss << std::endl;
 	}
 	for (const auto &i : table) {
-		ss << "# " << i.second.name.unescape() << std::endl;
+		ss << "# " << design->twines.unescaped_str(i.second.name) << std::endl;
 		ss << i.first << " " << i.second.area;
 		for (const auto &j : i.second.delays)
 			ss << " " << j;
@@ -1045,7 +1045,7 @@ void prep_box(RTLIL::Design *design)
 			}
 			log_assert(num_outputs == 1);
 
-			ss << module->name.unescape() << " " << r.first->second.as_int();
+			ss << design->twines.unescaped_str(module->name) << " " << r.first->second.as_int();
 			log_assert(module->get_bool_attribute(ID::whitebox));
 			ss << " " << "1";
 			ss << " " << num_inputs << " " << num_outputs << std::endl;
@@ -1060,7 +1060,7 @@ void prep_box(RTLIL::Design *design)
 					first = false;
 				else
 					ss << " ";
-				ss << wire->name.unescape();
+				ss << design->twines.unescaped_str(wire->name);
 			}
 			ss << std::endl;
 
@@ -1134,7 +1134,7 @@ void prep_box(RTLIL::Design *design)
 						outputs.emplace_back(wire, i);
 			}
 
-			ss << module->name.unescape() << " " << module->attributes.at(ID::abc9_box_id).as_int();
+			ss << design->twines.unescaped_str(module->name) << " " << module->attributes.at(ID::abc9_box_id).as_int();
 			bool has_model = module->get_bool_attribute(ID::whitebox) || !module->get_bool_attribute(ID::blackbox);
 			ss << " " << (has_model ? "1" : "0");
 			ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
@@ -1147,9 +1147,9 @@ void prep_box(RTLIL::Design *design)
 				else
 					ss << " ";
 				if (GetSize(i.wire) == 1)
-					ss << i.wire->name.unescape();
+					ss << design->twines.unescaped_str(i.wire->name);
 				else
-					ss << i.wire->name.unescape() << "[" << i.offset << "]";
+					ss << design->twines.unescaped_str(i.wire->name) << "[" << i.offset << "]";
 			}
 			ss << std::endl;
 
@@ -1173,9 +1173,9 @@ void prep_box(RTLIL::Design *design)
 				}
 				ss << " # ";
 				if (GetSize(o.wire) == 1)
-					ss << o.wire->name.unescape();
+					ss << design->twines.unescaped_str(o.wire->name);
 				else
-					ss << o.wire->name.unescape() << "[" << o.offset << "]";
+					ss << design->twines.unescaped_str(o.wire->name) << "[" << o.offset << "]";
 				ss << std::endl;
 			}
 			ss << std::endl;
@@ -1269,7 +1269,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 		// Short out (so that existing name can be preserved) and remove
 		//   $_DFF_[NP]_ cells since flop box already has all the information
 		//   we need to reconstruct them
-		if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
+		if (dff_mode && cell->type.in(TW($_DFF_N_), TW($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
 			SigBit Q = cell->getPort(TW::Q);
 			module->connect(Q, cell->getPort(TW::D));
 			module->remove(cell);
@@ -1278,7 +1278,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 			if (it != Qi.wire->attributes.end())
 				it->second.set(Qi.offset, State::Sx);
 		}
-		else if (cell->type.in(ID($_AND_), ID($_NOT_)))
+		else if (cell->type.in(TW($_AND_), TW($_NOT_)))
 			module->remove(cell);
 		else if (cell->attributes.erase(ID::abc9_box_seq))
 			boxes.emplace_back(cell);
@@ -1294,7 +1294,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 	{
 		// Short out $_FF_ cells since the flop box already has
 		//   all the information we need to reconstruct cell
-		if (dff_mode && mapped_cell->type == ID($_FF_)) {
+		if (dff_mode && mapped_cell->type == TW($_FF_)) {
 			SigBit D = mapped_cell->getPort(TW::D);
 			SigBit Q = mapped_cell->getPort(TW::Q);
 			if (D.wire)
@@ -1307,7 +1307,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 		// TODO: Speed up toposort -- we care about NOT ordering only
 		toposort.node(mapped_cell->name);
 
-		if (mapped_cell->type == ID($_NOT_)) {
+		if (mapped_cell->type == TW($_NOT_)) {
 			RTLIL::SigBit a_bit = mapped_cell->getPort(TW::A);
 			RTLIL::SigBit y_bit = mapped_cell->getPort(TW::Y);
 			bit_users[a_bit].insert(mapped_cell->name);
@@ -1345,7 +1345,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 							RTLIL::SigBit(module->wire(remap_name(y_bit.wire->name)), y_bit.offset),
 							RTLIL::Const::from_string("01"));
 					bit2sinks[cell->getPort(TW::A)].push_back(cell);
-					cell_stats[ID($lut)]++;
+					cell_stats[TW($lut)]++;
 				}
 				else
 					not2drivers[mapped_cell] = driver_lut;
@@ -1353,7 +1353,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 			continue;
 		}
 
-		if (mapped_cell->type == ID($lut)) {
+		if (mapped_cell->type == TW($lut)) {
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 			cell->parameters = mapped_cell->parameters;
 			cell->attributes = mapped_cell->attributes;
@@ -1554,7 +1554,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 	for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
 		RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
 		log_assert(not_cell);
-		if (not_cell->type != ID($_NOT_))
+		if (not_cell->type != TW($_NOT_))
 			continue;
 		auto it = not2drivers.find(not_cell);
 		if (it == not2drivers.end())
@@ -1572,7 +1572,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 			goto clone_lut;
 
 		for (auto sink_cell : jt->second)
-			if (sink_cell->type != ID($lut))
+			if (sink_cell->type != TW($lut))
 				goto clone_lut;
 
 		// Push downstream LUTs past inverter
@@ -1634,7 +1634,7 @@ static void replace_zbufs(Design *design)
 	for (auto mod : design->modules()) {
 		zbufs.clear();
 		for (auto cell : mod->cells()) {
-			if (cell->type != ID($buf))
+			if (cell->type != TW($buf))
 				continue;
 			auto &sig = cell->getPort(TW::A);
 			for (int i = 0; i < GetSize(sig); ++i) {
@@ -1650,7 +1650,7 @@ static void replace_zbufs(Design *design)
 			for (int i = 0; i < GetSize(sig); ++i) {
 				if (sig[i] == State::Sz) {
 					Wire *w = mod->addWire(NEW_TWINE);
-					Cell *ud = mod->addCell(NEW_TWINE, ID($tribuf));
+					Cell *ud = mod->addCell(NEW_TWINE, TW($tribuf));
 					ud->set_bool_attribute(ID::aiger2_zbuf);
 					ud->setParam(ID::WIDTH, 1);
 					ud->setPort(TW::Y, w);
@@ -1676,7 +1676,7 @@ static void restore_zbufs(Design *design)
 	for (auto mod : design->modules()) {
 		to_remove.clear();
 		for (auto cell : mod->cells())
-			if (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf)))
+			if (cell->type == TW($tribuf) && cell->has_attribute(ID(aiger2_zbuf)))
 				to_remove.push_back(cell);
 
 		for (auto cell : to_remove) {
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc
index 51d79cff4..bff1aa0b1 100644
--- a/passes/techmap/aigmap.cc
+++ b/passes/techmap/aigmap.cc
@@ -77,10 +77,10 @@ struct AigmapPass : public Pass {
 			{
 				Aig aig(cell);
 
-				if (cell->type.in(ID($_AND_), ID($_NOT_)))
+				if (cell->type.in(TW($_AND_), TW($_NOT_)))
 					aig.name.clear();
 
-				if (nand_mode && cell->type == ID($_NAND_))
+				if (nand_mode && cell->type == TW($_NAND_))
 					aig.name.clear();
 
 				if (aig.name.empty()) {
@@ -157,14 +157,14 @@ struct AigmapPass : public Pass {
 				stat_replaced.sort();
 				log("  replaced %d cell types:\n", GetSize(stat_replaced));
 				for (auto &it : stat_replaced)
-					log("%8d %s\n", it.second, it.first.unescape());
+					log("%8d %s\n", it.second, design->twines.unescaped_str(it.first));
 			}
 
 			if (!stat_not_replaced.empty()) {
 				stat_not_replaced.sort();
 				log("  not replaced %d cell types:\n", GetSize(stat_not_replaced));
 				for (auto &it : stat_not_replaced)
-					log("%8d %s\n", it.second, it.first.unescape());
+					log("%8d %s\n", it.second, design->twines.unescaped_str(it.first));
 			}
 
 			for (auto cell : replaced_cells)
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 35221965e..aa1de79e2 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -153,10 +153,10 @@ struct AlumaccWorker
 	{
 		for (auto cell : module->selected_cells())
 		{
-			if (!cell->type.in(ID($pos), ID($neg), ID($add), ID($sub), ID($mul)))
+			if (!cell->type.in(TW($pos), TW($neg), TW($add), TW($sub), TW($mul)))
 				continue;
 
-			log("  creating $macc model for %s (%s).\n", cell, cell->type.unescape());
+			log("  creating $macc model for %s (%s).\n", cell, cell->type.unescaped());
 
 			maccnode_t *n = new maccnode_t;
 			Macc::term_t new_term;
@@ -168,15 +168,15 @@ struct AlumaccWorker
 			for (auto bit : n->y)
 				n->users = max(n->users, bit_users.at(bit) - 1);
 
-			if (cell->type.in(ID($pos), ID($neg)))
+			if (cell->type.in(TW($pos), TW($neg)))
 			{
 				new_term.in_a = sigmap(cell->getPort(TW::A));
 				new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
-				new_term.do_subtract = cell->type == ID($neg);
+				new_term.do_subtract = cell->type == TW($neg);
 				n->macc.terms.push_back(new_term);
 			}
 
-			if (cell->type.in(ID($add), ID($sub)))
+			if (cell->type.in(TW($add), TW($sub)))
 			{
 				new_term.in_a = sigmap(cell->getPort(TW::A));
 				new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
@@ -185,11 +185,11 @@ struct AlumaccWorker
 
 				new_term.in_a = sigmap(cell->getPort(TW::B));
 				new_term.is_signed = cell->getParam(ID::B_SIGNED).as_bool();
-				new_term.do_subtract = cell->type == ID($sub);
+				new_term.do_subtract = cell->type == TW($sub);
 				n->macc.terms.push_back(new_term);
 			}
 
-			if (cell->type.in(ID($mul)))
+			if (cell->type.in(TW($mul)))
 			{
 				new_term.in_a = sigmap(cell->getPort(TW::A));
 				new_term.in_b = sigmap(cell->getPort(TW::B));
@@ -379,7 +379,7 @@ struct AlumaccWorker
 		for (auto &it : sig_macc)
 		{
 			auto n = it.second;
-			auto cell = module->addCell(NEW_TWINE, ID($macc));
+			auto cell = module->addCell(NEW_TWINE, TW($macc));
 
 			macc_counter++;
 
@@ -404,18 +404,18 @@ struct AlumaccWorker
 
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt)))
+			if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt)))
 				lge_cells.push_back(cell);
-			if (cell->type.in(ID($eq), ID($eqx), ID($ne), ID($nex)))
+			if (cell->type.in(TW($eq), TW($eqx), TW($ne), TW($nex)))
 				eq_cells.push_back(cell);
 		}
 
 		for (auto cell : lge_cells)
 		{
-			log("  creating $alu model for %s (%s):", cell, cell->type.unescape());
+			log("  creating $alu model for %s (%s):", cell, cell->type.unescaped());
 
-			bool cmp_less = cell->type.in(ID($lt), ID($le));
-			bool cmp_equal = cell->type.in(ID($le), ID($ge));
+			bool cmp_less = cell->type.in(TW($lt), TW($le));
+			bool cmp_equal = cell->type.in(TW($le), TW($ge));
 			bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
 
 			RTLIL::SigSpec A = sigmap(cell->getPort(TW::A));
@@ -460,7 +460,7 @@ struct AlumaccWorker
 
 		for (auto cell : eq_cells)
 		{
-			bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
+			bool cmp_equal = cell->type.in(TW($eq), TW($eqx));
 			bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
 
 			RTLIL::SigSpec A = sigmap(cell->getPort(TW::A));
@@ -484,7 +484,7 @@ struct AlumaccWorker
 			}
 
 			if (n != nullptr) {
-				log("  creating $alu model for %s (%s): merged with %s.\n", cell, cell->type.unescape(), n->cells.front());
+				log("  creating $alu model for %s (%s): merged with %s.\n", cell, cell->type.unescaped(), n->cells.front());
 				n->cells.push_back(cell);
 				n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, false, Y));
 			}
@@ -509,7 +509,7 @@ struct AlumaccWorker
 				goto delete_node;
 			}
 
-			n->alu_cell = module->addCell(NEW_TWINE, ID($alu));
+			n->alu_cell = module->addCell(NEW_TWINE, TW($alu));
 			alu_counter++;
 
 			log("  creating $alu cell for ");
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index 5854aa16e..292a42a7e 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -30,7 +30,7 @@ struct Traversal {
 	Traversal(Module *module) : sigmap(module)
 	{
 		for (auto cell : module->cells()) {
-			if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
+			if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
 				continue;
 			for (auto &conn : cell->connections())
 				if (cell->input(conn.first))
@@ -53,11 +53,11 @@ struct Cells {
 	pool<Cell *> alu;
 	pool<Cell *> macc;
 
-	static bool is_addsub(Cell *cell) { return cell->type == ID($add) || cell->type == ID($sub); }
+	static bool is_addsub(Cell *cell) { return cell->type == TW($add) || cell->type == TW($sub); }
 
-	static bool is_alu(Cell *cell) { return cell->type == ID($alu); }
+	static bool is_alu(Cell *cell) { return cell->type == TW($alu); }
 
-	static bool is_macc(Cell *cell) { return cell->type == ID($macc) || cell->type == ID($macc_v2); }
+	static bool is_macc(Cell *cell) { return cell->type == TW($macc) || cell->type == TW($macc_v2); }
 
 	bool empty() { return addsub.empty() && alu.empty() && macc.empty(); }
 
@@ -196,7 +196,7 @@ struct Rewriter {
 	bool feeds_subtracted_port(Cell *child, Cell *parent)
 	{
 		bool parent_subtracts;
-		if (parent->type == ID($sub))
+		if (parent->type == TW($sub))
 			parent_subtracts = true;
 		else if (cells.is_alu(parent))
 			parent_subtracts = alu_info.is_subtract(parent);
@@ -251,7 +251,7 @@ struct Rewriter {
 			SigSpec b = traversal.sigmap(cell->getPort(TW::B));
 			bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
 			bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
-			bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
+			bool b_sub = (cell->type == TW($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
 
 			// Only add operands not produced by other chain cells
 			if (!overlaps(a, chain_bits)) {
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index 4c97f6ab1..7a33a3770 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -131,13 +131,13 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
 
 		if (new_attr != attr)
 			log("Changed attribute on %s: %s=%s -> %s=%s\n", objname,
-					attr.first.unescape(), log_const(attr.second), new_attr.first.unescape(), log_const(new_attr.second));
+					attr.first.unescape(), log_const(attr.second), design->twines.unescaped_str(new_attr.first), log_const(new_attr.second));
 
 		new_attributes[new_attr.first] = new_attr.second;
 
 		if (0)
 	delete_this_attr:
-			log("Removed attribute on %s: %s=%s\n", objname, attr.first.unescape(), log_const(attr.second));
+			log("Removed attribute on %s: %s=%s\n", objname, design->twines.unescaped_str(attr.first), log_const(attr.second));
 	}
 
 	attributes.swap(new_attributes);
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index cff7d8697..0f9cc1a6b 100644
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -121,7 +121,7 @@ struct AttrmvcpPass : public Pass {
 					for (auto bit : sigmap(wire))
 						if (net2cells.count(bit))
 							for (auto cell : net2cells.at(bit)) {
-								log("Moving attribute %s=%s from %s.%s to %s.%s.\n", attr.first.unescape(), log_const(attr.second),
+								log("Moving attribute %s=%s from %s.%s to %s.%s.\n", design->twines.unescaped_str(attr.first), log_const(attr.second),
 										module, wire, module, cell);
 								cell->attributes[attr.first] = attr.second;
 								did_something = true;
diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc
index 14488fedf..61cbc9625 100644
--- a/passes/techmap/bmuxmap.cc
+++ b/passes/techmap/bmuxmap.cc
@@ -56,7 +56,7 @@ struct BmuxmapPass : public Pass {
 		for (auto module : design->selected_modules())
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type != ID($bmux))
+			if (cell->type != TW($bmux))
 				continue;
 
 			SigSpec sel = cell->getPort(TW::S);
diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc
index 5a74390e1..527e5197a 100644
--- a/passes/techmap/booth.cc
+++ b/passes/techmap/booth.cc
@@ -212,14 +212,14 @@ struct BoothPassWorker {
 			SigSpec A, B, Y;
 			bool is_signed;
 
-			if (cell->type == ID($mul)) {
+			if (cell->type == TW($mul)) {
 				A = cell->getPort(TW::A);
 				B = cell->getPort(TW::B);
 				Y = cell->getPort(TW::Y);
 
 				log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
 				is_signed = cell->getParam(ID::A_SIGNED).as_bool();
-			} else if (cell->type.in(ID($macc), ID($macc_v2))) {
+			} else if (cell->type.in(TW($macc), TW($macc_v2))) {
 				Macc macc;
 				macc.from_cell(cell);
 
diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc
index bd6898e16..356d80057 100644
--- a/passes/techmap/bufnorm.cc
+++ b/passes/techmap/bufnorm.cc
@@ -277,7 +277,7 @@ struct BufnormPass : public Pass {
 				vector<Cell*> old_dup_buffers;
 				for (auto cell : module->cells())
 				{
-					if (!cell->type.in(ID($buf), ID($_BUF_)))
+					if (!cell->type.in(TW($buf), TW($_BUF_)))
 						continue;
 
 					SigSpec insig = cell->getPort(TW::A);
@@ -380,7 +380,7 @@ struct BufnormPass : public Pass {
 
 			for (auto cell : module->cells())
 			{
-				if (cell->type.in(ID($buf), ID($_BUF_)))
+				if (cell->type.in(TW($buf), TW($_BUF_)))
 					continue;
 
 				for (auto &conn : cell->connections())
@@ -409,7 +409,7 @@ struct BufnormPass : public Pass {
 
 					if (w->name.isPublic())
 						log("  directly driven by cell %s port %s: %s\n",
-								cell, conn.first.unescape(), w);
+								cell, design->twines.unescaped_str(conn.first), w);
 
 					for (auto bit : SigSpec(w))
 						mapped_bits[sigmap(bit)] = bit;
@@ -488,12 +488,12 @@ struct BufnormPass : public Pass {
 					}
 				} else {
 					if (bits_mode) {
-						IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) : ID($_BUF_);
+						IdString celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) : TW($_BUF_);
 						for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
 							make_buffer_f(celltype, insig[i], outsig[i]);
 					} else {
-						IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) :
-								GetSize(outsig) == 1 ? ID($_BUF_) : ID($buf);
+						IdString celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) :
+								GetSize(outsig) == 1 ? TW($_BUF_) : TW($buf);
 						make_buffer_f(celltype, insig, outsig);
 					}
 				}
@@ -519,7 +519,7 @@ struct BufnormPass : public Pass {
 
 					if (conn.second != newsig) {
 						log("  fixing input signal on cell %s port %s: %s\n",
-								cell, conn.first.unescape(), log_signal(newsig));
+								cell, design->twines.unescaped_str(conn.first), log_signal(newsig));
 						cell->setPort(conn.first, newsig);
 						count_updated_cellports++;
 					}
diff --git a/passes/techmap/bwmuxmap.cc b/passes/techmap/bwmuxmap.cc
index 53ea04e4f..d869f1795 100644
--- a/passes/techmap/bwmuxmap.cc
+++ b/passes/techmap/bwmuxmap.cc
@@ -50,7 +50,7 @@ struct BwmuxmapPass : public Pass {
 		for (auto module : design->selected_modules())
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type != ID($bwmux))
+			if (cell->type != TW($bwmux))
 				continue;
 			auto &sig_y = cell->getPort(TW::Y);
 			auto &sig_a = cell->getPort(TW::A);
diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
index a2e2393d0..261e4eac5 100644
--- a/passes/techmap/cellmatch.cc
+++ b/passes/techmap/cellmatch.cc
@@ -95,7 +95,7 @@ bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
 	CellTypes ff_types;
 	ff_types.setup_stdcells_mem();
 	for (auto cell : m->cells()) {
-		if (ff_types.cell_known(cell->type)) {
+		if (ff_types.cell_known(cell->type_impl)) {
 			log("Ignoring module '%s' which isn't purely combinational.\n", m);
 			return false;
 		}
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index 103fba103..f72457b8c 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -83,9 +83,9 @@ struct DeminoutPass : public Pass {
 						for (auto bit : sigmap(conn.second))
 							bits_used.insert(bit);
 
-					if (conn.first == ID::Y && cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_TBUF_), ID($tribuf)))
+					if (conn.first == ID::Y && cell->type.in(TW($mux), TW($pmux), TW($_MUX_), TW($_TBUF_), TW($tribuf)))
 					{
-						bool tribuf = cell->type.in(ID($_TBUF_), ID($tribuf));
+						bool tribuf = cell->type.in(TW($_TBUF_), TW($tribuf));
 
 						if (!tribuf) {
 							for (auto &c : cell->connections()) {
diff --git a/passes/techmap/demuxmap.cc b/passes/techmap/demuxmap.cc
index db62d1c8b..ff49b4c92 100644
--- a/passes/techmap/demuxmap.cc
+++ b/passes/techmap/demuxmap.cc
@@ -47,7 +47,7 @@ struct DemuxmapPass : public Pass {
 		for (auto module : design->selected_modules())
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type != ID($demux))
+			if (cell->type != TW($demux))
 				continue;
 
 			SigSpec sel = cell->getPort(TW::S);
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 912f7fb81..a79c45ceb 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -123,14 +123,14 @@ struct DffinitPass : public Pass {
 						if (noreinit && value[i] != State::Sx && value[i] != initval[i])
 							log_error("Trying to assign a different init value for %s.%s.%s which technically "
 									"have a conflicted init value.\n",
-									module, cell, it.second.unescape());
+									module, cell, design->twines.unescaped_str(it.second));
 						value.set(i, initval[i]);
 					}
 
 					if (highlow_mode && GetSize(value) != 0) {
 						if (GetSize(value) != 1)
 							log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
-									module, cell, it.second.unescape());
+									module, cell, design->twines.unescaped_str(it.second));
 						if (value[0] == State::S1)
 							value = Const(high_string);
 						else
@@ -138,7 +138,7 @@ struct DffinitPass : public Pass {
 					}
 
 					if (value.size() != 0) {
-						log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, it.second.unescape(),
+						log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, design->twines.unescaped_str(it.second),
 								it.first.unescape(), log_signal(sig), log_signal(value));
 						cell->setParam(it.second, value);
 					}
diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc
index c39eda1c1..d1d5845d7 100644
--- a/passes/techmap/dfflegalize.cc
+++ b/passes/techmap/dfflegalize.cc
@@ -263,7 +263,7 @@ struct DffLegalizePass : public Pass {
 	}
 
 	void fail_ff(const FfData &ff, const char *reason) {
-		log_error("FF %s.%s (type %s) cannot be legalized: %s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name), ff.cell->type.unescape(), reason);
+		log_error("FF %s.%s (type %s) cannot be legalized: %s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(ff.cell->type), reason);
 	}
 
 	bool try_flip(FfData &ff, int supported_mask) {
@@ -381,7 +381,7 @@ struct DffLegalizePass : public Pass {
 		if (ff.has_ce && !supported_cells[FF_ADFFE])
 			ff.unmap_ce();
 
-		log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name));
+		log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
 
 		log_assert(ff.width == 1);
 		ff.remove();
@@ -600,7 +600,7 @@ struct DffLegalizePass : public Pass {
 				ff.unmap_ce();
 
 			if (ff.cell)
-				log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name));
+				log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
 			emulate_split_init_arst(ff);
 			return;
 		}
@@ -752,7 +752,7 @@ struct DffLegalizePass : public Pass {
 			// The only hope left is breaking down to adlatch + dlatch + dlatch + mux.
 
 			if (ff.cell)
-				log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name));
+				log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
 			ff.remove();
 
 			emulate_split_init_arst(ff);
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 2b544f09f..259c32cd1 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -55,31 +55,31 @@ static void logmap(IdString dff)
 
 static void logmap_all()
 {
-	logmap(ID($_DFF_N_));
-	logmap(ID($_DFF_P_));
+	logmap(TW($_DFF_N_));
+	logmap(TW($_DFF_P_));
 
-	logmap(ID($_DFF_NN0_));
-	logmap(ID($_DFF_NN1_));
-	logmap(ID($_DFF_NP0_));
-	logmap(ID($_DFF_NP1_));
-	logmap(ID($_DFF_PN0_));
-	logmap(ID($_DFF_PN1_));
-	logmap(ID($_DFF_PP0_));
-	logmap(ID($_DFF_PP1_));
+	logmap(TW($_DFF_NN0_));
+	logmap(TW($_DFF_NN1_));
+	logmap(TW($_DFF_NP0_));
+	logmap(TW($_DFF_NP1_));
+	logmap(TW($_DFF_PN0_));
+	logmap(TW($_DFF_PN1_));
+	logmap(TW($_DFF_PP0_));
+	logmap(TW($_DFF_PP1_));
 
-	logmap(ID($_DFFE_NN_));
-	logmap(ID($_DFFE_NP_));
-	logmap(ID($_DFFE_PN_));
-	logmap(ID($_DFFE_PP_));
+	logmap(TW($_DFFE_NN_));
+	logmap(TW($_DFFE_NP_));
+	logmap(TW($_DFFE_PN_));
+	logmap(TW($_DFFE_PP_));
 
-	logmap(ID($_DFFSR_NNN_));
-	logmap(ID($_DFFSR_NNP_));
-	logmap(ID($_DFFSR_NPN_));
-	logmap(ID($_DFFSR_NPP_));
-	logmap(ID($_DFFSR_PNN_));
-	logmap(ID($_DFFSR_PNP_));
-	logmap(ID($_DFFSR_PPN_));
-	logmap(ID($_DFFSR_PPP_));
+	logmap(TW($_DFFSR_NNN_));
+	logmap(TW($_DFFSR_NNP_));
+	logmap(TW($_DFFSR_NPN_));
+	logmap(TW($_DFFSR_NPP_));
+	logmap(TW($_DFFSR_PNN_));
+	logmap(TW($_DFFSR_PNP_));
+	logmap(TW($_DFFSR_PPN_));
+	logmap(TW($_DFFSR_PPP_));
 }
 
 static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std::string &data_name, bool &data_not_inverted, std::string &enable_name, bool &enable_not_inverted)
@@ -504,7 +504,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 	for (auto cell : module->cells()) {
 		if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0)
 			cell_list.push_back(cell);
-		if (cell->type == ID($_NOT_))
+		if (cell->type == TW($_NOT_))
 			notmap[sigmap(cell->getPort(TW::A))].insert(cell);
 	}
 
@@ -660,31 +660,31 @@ struct DfflibmapPass : public Pass {
 			delete f;
 		}
 
-		find_cell(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
 
-		find_cell(merged.cells, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
 
-		find_cell(merged.cells, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
-		find_cell(merged.cells, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
-		find_cell(merged.cells, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
+		find_cell(merged.cells, TW($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
+		find_cell(merged.cells, TW($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
+		find_cell(merged.cells, TW($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
 
-		find_cell_sr(merged.cells, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
-		find_cell_sr(merged.cells, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
-		find_cell_sr(merged.cells, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
-		find_cell_sr(merged.cells, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
-		find_cell_sr(merged.cells, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
-		find_cell_sr(merged.cells, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
-		find_cell_sr(merged.cells, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
-		find_cell_sr(merged.cells, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
+		find_cell_sr(merged.cells, TW($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
 
 		log("  final dff cell mappings:\n");
 		logmap_all();
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 2d7295345..ddcd816c0 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -155,12 +155,12 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
 	std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
 
 	if (sel && !sel->selected(mod)) {
-		log("  Skipping module %s as it is not selected.\n", mod->name.unescape());
+		log("  Skipping module %s as it is not selected.\n", design->twines.unescaped_str(mod->name));
 		return false;
 	}
 
 	if (mod->processes.size() > 0) {
-		log("  Skipping module %s as it contains unprocessed processes.\n", mod->name.unescape());
+		log("  Skipping module %s as it contains unprocessed processes.\n", design->twines.unescaped_str(mod->name));
 		return false;
 	}
 
@@ -626,7 +626,7 @@ struct ExtractPass : public Pass {
 		if (!mine_mode)
 			for (auto module : map->modules()) {
 				SubCircuit::Graph mod_graph;
-				std::string graph_name = "needle_" + module->name.unescape();
+				std::string graph_name = "needle_" + design->twines.unescaped_str(module->name);
 				log("Creating needle graph %s.\n", graph_name);
 				if (module2graph(mod_graph, module, constports)) {
 					solver.addGraph(graph_name, mod_graph);
@@ -637,7 +637,7 @@ struct ExtractPass : public Pass {
 
 		for (auto module : design->modules()) {
 			SubCircuit::Graph mod_graph;
-			std::string graph_name = "haystack_" + module->name.unescape();
+			std::string graph_name = "haystack_" + design->twines.unescaped_str(module->name);
 			log("Creating haystack graph %s.\n", graph_name);
 			if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) {
 				solver.addGraph(graph_name, mod_graph);
@@ -654,8 +654,8 @@ struct ExtractPass : public Pass {
 
 			for (auto needle : needle_list)
 			for (auto &haystack_it : haystack_map) {
-				log("Solving for %s in %s.\n", ("needle_" + needle->name.unescape()), haystack_it.first);
-				solver.solve(results, "needle_" + needle->name.unescape(), haystack_it.first, false);
+				log("Solving for %s in %s.\n", ("needle_" + design->twines.unescaped_str(needle->name)), haystack_it.first);
+				solver.solve(results, "needle_" + design->twines.unescaped_str(needle->name), haystack_it.first, false);
 			}
 			log("Found %d matches.\n", GetSize(results));
 
@@ -691,12 +691,12 @@ struct ExtractPass : public Pass {
 			for (auto &result: results)
 			{
 				log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
-				log("  primary match in %s:", haystack_map.at(result.graphId)->name.unescape());
+				log("  primary match in %s:", design->twines.unescaped_str(haystack_map.at(result.graphId)->name));
 				for (auto &node : result.nodes)
 					log(" %s", RTLIL::unescape_id(node.nodeId));
 				log("\n");
 				for (auto &it : result.matchesPerGraph)
-					log("  matches in %s: %d\n", haystack_map.at(it.first)->name.unescape(), it.second);
+					log("  matches in %s: %d\n", design->twines.unescaped_str(haystack_map.at(it.first)->name), it.second);
 
 				RTLIL::Module *mod = haystack_map.at(result.graphId);
 				std::set<RTLIL::Cell*> cells;
@@ -717,7 +717,7 @@ struct ExtractPass : public Pass {
 
 				RTLIL::Module *newMod = new RTLIL::Module;
 				newMod->design = map;
-				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, haystack_map.at(result.graphId)->name.unescape(), result.totalMatchesAfterLimits);
+				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, design->twines.unescaped_str(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
 				map->add(newMod);
 
 				for (auto wire : wires) {
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index 29be586b8..0ed21b098 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -258,7 +258,7 @@ int counter_tryextract(
 		return 9;
 	Cell* count_mux = *y_loads.begin();
 	extract.count_mux = count_mux;
-	if(count_mux->type != ID($mux))
+	if(count_mux->type != TW($mux))
 		return 10;
 	if(!is_full_bus(aluy, index, cell, ID::Y, count_mux, ID::A))
 		return 11;
@@ -287,9 +287,9 @@ int counter_tryextract(
 	Cell* overflow_cell = NULL;
 	for(auto c : muxsel_conns)
 	{
-		if(extract.count_is_up && c->type != ID($eq))
+		if(extract.count_is_up && c->type != TW($eq))
 			continue;
-		if(!extract.count_is_up && c->type != ID($logic_not))
+		if(!extract.count_is_up && c->type != TW($logic_not))
 			continue;
 		if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID::S, true))
 			continue;
@@ -311,7 +311,7 @@ int counter_tryextract(
 	Cell* count_reg = muxload;
 	Cell* cemux = NULL;
 	RTLIL::SigSpec cey;
-	if(muxload->type == ID($mux))
+	if(muxload->type == TW($mux))
 	{
 		//This mux is probably a clock enable mux.
 		//Find our count register (should be our only load)
@@ -349,9 +349,9 @@ int counter_tryextract(
 		extract.has_ce = false;
 
 	extract.count_reg = count_reg;
-	if(count_reg->type == ID($dff))
+	if(count_reg->type == TW($dff))
 		extract.has_reset = false;
-	else if(count_reg->type == ID($adff))
+	else if(count_reg->type == TW($adff))
 	{
 		if (!settings.allow_arst)
 			return 25;
@@ -517,7 +517,7 @@ void counter_worker(
 	SigMap& sigmap = index.sigmap;
 
 	//Core of the counter must be an ALU
-	if (cell->type != ID($alu))
+	if (cell->type != TW($alu))
 		return;
 
 	//A input is the count value. Check if it has COUNT_EXTRACT set.
@@ -611,7 +611,7 @@ void counter_worker(
 	}
 
 	//Get new cell name
-	string countname = string("$COUNTx$") + extract.rwire->name.unescape();
+	string countname = string("$COUNTx$") + design->twines.unescaped_str(extract.rwire->name);
 
 	//Wipe all of the old connections to the ALU
 	cell->unsetPort(TW::A);
@@ -697,7 +697,7 @@ void counter_worker(
 	//Hook up any parallel outputs
 	for(auto load : extract.pouts)
 	{
-		log("    Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), load.port.unescape());
+		log("    Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(load.port));
 	}
 	if(extract.has_pout)
 	{
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc
index d6a41c33f..2ad76fe67 100644
--- a/passes/techmap/extract_fa.cc
+++ b/passes/techmap/extract_fa.cc
@@ -85,9 +85,9 @@ struct ExtractFaWorker
 	{
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type.in( ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
-					ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
-					ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
+			if (cell->type.in( TW($_BUF_), TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_),
+					TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_), TW($_MUX_), TW($_NMUX_),
+					TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)))
 			{
 				SigBit y = sigmap(SigBit(cell->getPort(TW::Y)));
 				log_assert(driver.count(y) == 0);
@@ -293,7 +293,7 @@ struct ExtractFaWorker
 
 		for (auto it : driver)
 		{
-			if (it.second->type.in(ID($_BUF_), ID($_NOT_)))
+			if (it.second->type.in(TW($_BUF_), TW($_NOT_)))
 				continue;
 
 			SigBit root = it.first;
@@ -394,7 +394,7 @@ struct ExtractFaWorker
 				}
 				else
 				{
-					Cell *cell = module->addCell(NEW_TWINE, ID($fa));
+					Cell *cell = module->addCell(NEW_TWINE, TW($fa));
 					cell->setParam(ID::WIDTH, 1);
 
 					log("      Created $fa cell %s.\n", cell);
@@ -501,7 +501,7 @@ struct ExtractFaWorker
 				}
 				else
 				{
-					Cell *cell = module->addCell(NEW_TWINE, ID($fa));
+					Cell *cell = module->addCell(NEW_TWINE, TW($fa));
 					cell->setParam(ID::WIDTH, 1);
 
 					log("      Created $fa cell %s.\n", cell);
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index ca7226e76..7f48c4fc7 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -58,9 +58,9 @@ struct ExtractReducePass : public Pass
 
 	inline bool IsRightType(Cell* cell, GateType gt)
 	{
-		return (cell->type == ID($_AND_) && gt == GateType::And) ||
-				(cell->type == ID($_OR_) && gt == GateType::Or) ||
-				(cell->type == ID($_XOR_) && gt == GateType::Xor);
+		return (cell->type == TW($_AND_) && gt == GateType::And) ||
+				(cell->type == TW($_OR_) && gt == GateType::Or) ||
+				(cell->type == TW($_XOR_) && gt == GateType::Xor);
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -124,11 +124,11 @@ struct ExtractReducePass : public Pass
 
 				GateType gt;
 
-				if (cell->type == ID($_AND_))
+				if (cell->type == TW($_AND_))
 					gt = GateType::And;
-				else if (cell->type == ID($_OR_))
+				else if (cell->type == TW($_OR_))
 					gt = GateType::Or;
-				else if (cell->type == ID($_XOR_))
+				else if (cell->type == TW($_XOR_))
 					gt = GateType::Xor;
 				else
 					continue;
@@ -261,7 +261,7 @@ struct ExtractReducePass : public Pass
 						SigSpec input;
 						for (auto it : sources) {
 							bool cond;
-							if (head_cell->type == ID($_XOR_))
+							if (head_cell->type == TW($_XOR_))
 								cond = it.second & 1;
 							else
 								cond = it.second != 0;
@@ -269,11 +269,11 @@ struct ExtractReducePass : public Pass
 								input.append(it.first);
 						}
 
-						if (head_cell->type == ID($_AND_)) {
+						if (head_cell->type == TW($_AND_)) {
 							module->addReduceAnd(NEW_TWINE, input, output);
-						} else if (head_cell->type == ID($_OR_)) {
+						} else if (head_cell->type == TW($_OR_)) {
 							module->addReduceOr(NEW_TWINE, input, output);
-						} else if (head_cell->type == ID($_XOR_)) {
+						} else if (head_cell->type == TW($_XOR_)) {
 							module->addReduceXor(NEW_TWINE, input, output);
 						} else {
 							log_assert(false);
diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc
index 03252b6c0..7c68e6dc2 100644
--- a/passes/techmap/extractinv.cc
+++ b/passes/techmap/extractinv.cc
@@ -100,7 +100,7 @@ struct ExtractinvPass : public Pass {
 					continue;
 				SigSpec sig = port.second;
 				if (it2->second.size() != sig.size())
-					log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", module->name.unescape(), cell->type.unescape(), port.first.unescape(), param_name.unescape());
+					log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", design->twines.unescaped_str(module->name), cell->type.unescaped(), design->twines.unescaped_str(port.first), design->twines.unescaped_str(param_name));
 				RTLIL::Const invmask = it2->second;
 				cell->parameters.erase(param_name);
 				if (invmask.is_fully_zero())
@@ -111,7 +111,7 @@ struct ExtractinvPass : public Pass {
 						RTLIL::Cell *icell = module->addCell(NEW_TWINE, RTLIL::escape_id(inv_celltype));
 						icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
 						icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
-						log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescape(), port.first.unescape(), i);
+						log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescaped(), design->twines.unescaped_str(port.first), i);
 						sig[i] = SigBit(iwire, i);
 					}
 				cell->setPort(port.first, sig);
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index a7c779a50..879c0f127 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -674,8 +674,8 @@ struct FlowmapWorker
 			labels[node] = -1;
 		for (auto input : inputs)
 		{
-			if (input.wire->attributes.count(ID($flowmap_level)))
-				labels[input] = input.wire->attributes[ID($flowmap_level)].as_int();
+			if (input.wire->attributes.count(TW($flowmap_level)))
+				labels[input] = input.wire->attributes[TW($flowmap_level)].as_int();
 			else
 				labels[input] = 0;
 		}
@@ -1590,7 +1590,7 @@ struct FlowmapPass : public Pass {
 		}
 		else
 		{
-			cell_types = {ID($_NOT_), ID($_AND_), ID($_OR_), ID($_XOR_), ID($_MUX_)};
+			cell_types = {TW($_NOT_), TW($_AND_), TW($_OR_), TW($_XOR_), TW($_MUX_)};
 		}
 
 		const char *algo_r = relax ? "-r" : "";
diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc
index c2c005d40..0ae30955d 100644
--- a/passes/techmap/insbuf.cc
+++ b/passes/techmap/insbuf.cc
@@ -44,7 +44,7 @@ struct InsbufPass : public Pass {
 	{
 		log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
 
-		IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
+		IdString celltype = TW($_BUF_), in_portname = ID::A, out_portname = ID::Y;
 		bool chain_mode = false;
 
 		size_t argidx;
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 87db13eed..24fa4b0db 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -253,7 +253,7 @@ struct IopadmapPass : public Pass {
 
 				// Gather tristate buffers and always-on drivers.
 				for (auto cell : module->cells())
-					if (cell->type == ID($_TBUF_)) {
+					if (cell->type == TW($_TBUF_)) {
 						SigBit bit = cell->getPort(TW::Y).as_bit();
 						tbuf_bits[bit] = cell;
 					} else {
@@ -436,7 +436,7 @@ struct IopadmapPass : public Pass {
 						SigBit wire_bit(wire, i);
 
 						RTLIL::Cell *cell = module->addCell(
-							module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
+							module->uniquify(stringf("$iopadmap$%s.%s", design->twines.unescaped_str(module->name), design->twines.unescaped_str(wire->name))),
 							RTLIL::escape_id(celltype));
 						cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
 
@@ -452,7 +452,7 @@ struct IopadmapPass : public Pass {
 				else
 				{
 					RTLIL::Cell *cell = module->addCell(
-						module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
+						module->uniquify(stringf("$iopadmap$%s.%s", design->twines.unescaped_str(module->name), design->twines.unescaped_str(wire->name))),
 						RTLIL::escape_id(celltype));
 					cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
 
@@ -468,7 +468,7 @@ struct IopadmapPass : public Pass {
 					if (!widthparam.empty())
 						cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
 					if (!nameparam.empty())
-						cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(wire->name.unescape());
+						cell->parameters[RTLIL::escape_id(nameparam)] = design->twines.unescaped_str(RTLIL::Const(wire->name));
 					cell->attributes[ID::keep] = RTLIL::Const(1);
 				}
 
diff --git a/passes/techmap/lut2bmux.cc b/passes/techmap/lut2bmux.cc
index 69f8cabc2..48d01d29c 100644
--- a/passes/techmap/lut2bmux.cc
+++ b/passes/techmap/lut2bmux.cc
@@ -43,7 +43,7 @@ struct Lut2BmuxPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		for (auto cell : module->selected_cells()) {
-			if (cell->type == ID($lut)) {
+			if (cell->type == TW($lut)) {
 				cell->type_impl = TW::$bmux;
 				cell->setPort(TW::S, cell->getPort(TW::A));
 				cell->setPort(TW::A, cell->getParam(ID::LUT));
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index db36bce42..c72aabf10 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -94,10 +94,10 @@ struct Lut2muxPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		for (auto cell : module->selected_cells()) {
-			if (cell->type == ID($lut)) {
+			if (cell->type == TW($lut)) {
 				IdString cell_name = cell->name;
 				int count = lut2mux(cell, word_mode);
-				log("Converted %s.%s to %d MUX cells.\n", module, cell_name.unescape(), count);
+				log("Converted %s.%s to %d MUX cells.\n", module, design->twines.unescaped_str(cell_name), count);
 			}
 		}
 	}
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index 825eb5e0e..a8ba5b1cb 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -111,7 +111,7 @@ struct MaccmapWorker
 			RTLIL::Wire *w1 = module->addWire(NEW_TWINE, width);
 			RTLIL::Wire *w2 = module->addWire(NEW_TWINE, width);
 
-			RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($fa));
+			RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW($fa));
 			cell->setParam(ID::WIDTH, width);
 			cell->setPort(TW::A, in1);
 			cell->setPort(TW::B, in2);
@@ -237,7 +237,7 @@ struct MaccmapWorker
 		}
 
 
-		RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($alu));
+		RTLIL::Cell *c = module->addCell(NEW_TWINE, TW($alu));
 		c->setPort(TW::A, summands.front());
 		c->setPort(TW::B, summands.back());
 		c->setPort(TW::CI, State::S0);
@@ -403,8 +403,8 @@ struct MaccmapPass : public Pass {
 
 		for (auto mod : design->selected_modules())
 		for (auto cell : mod->selected_cells())
-			if (cell->type.in(ID($macc), ID($macc_v2))) {
-				log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescape());
+			if (cell->type.in(TW($macc), TW($macc_v2))) {
+				log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescaped());
 				maccmap(mod, cell, unmap_mode);
 				mod->remove(cell);
 			}
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 5a43cfa95..03ae51217 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -116,12 +116,12 @@ struct MuxcoverWorker
 				if (!cell->input(conn.first))
 					continue;
 				for (auto bit : sigmap(conn.second)) {
-					if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID::S)
+					if (used_once.count(bit) || cell->type != TW($_MUX_) || conn.first == ID::S)
 						roots.insert(bit);
 					used_once.insert(bit);
 				}
 			}
-			if (cell->type == ID($_MUX_))
+			if (cell->type == TW($_MUX_))
 				sig_to_mux[sigmap(cell->getPort(TW::Y))] = cell;
 		}
 
@@ -513,7 +513,7 @@ struct MuxcoverWorker
 
 		if (GetSize(mux.inputs) == 2) {
 			count_muxes_by_type[0]++;
-			Cell *cell = module->addCell(NEW_TWINE, ID($_MUX_));
+			Cell *cell = module->addCell(NEW_TWINE, TW($_MUX_));
 			cell->setPort(TW::A, mux.inputs[0]);
 			cell->setPort(TW::B, mux.inputs[1]);
 			cell->setPort(TW::S, mux.selects[0]);
@@ -523,7 +523,7 @@ struct MuxcoverWorker
 
 		if (GetSize(mux.inputs) == 4) {
 			count_muxes_by_type[1]++;
-			Cell *cell = module->addCell(NEW_TWINE, ID($_MUX4_));
+			Cell *cell = module->addCell(NEW_TWINE, TW($_MUX4_));
 			cell->setPort(TW::A, mux.inputs[0]);
 			cell->setPort(TW::B, mux.inputs[1]);
 			cell->setPort(TW::C, mux.inputs[2]);
@@ -536,7 +536,7 @@ struct MuxcoverWorker
 
 		if (GetSize(mux.inputs) == 8) {
 			count_muxes_by_type[2]++;
-			Cell *cell = module->addCell(NEW_TWINE, ID($_MUX8_));
+			Cell *cell = module->addCell(NEW_TWINE, TW($_MUX8_));
 			cell->setPort(TW::A, mux.inputs[0]);
 			cell->setPort(TW::B, mux.inputs[1]);
 			cell->setPort(TW::C, mux.inputs[2]);
@@ -554,7 +554,7 @@ struct MuxcoverWorker
 
 		if (GetSize(mux.inputs) == 16) {
 			count_muxes_by_type[3]++;
-			Cell *cell = module->addCell(NEW_TWINE, ID($_MUX16_));
+			Cell *cell = module->addCell(NEW_TWINE, TW($_MUX16_));
 			cell->setPort(TW::A, mux.inputs[0]);
 			cell->setPort(TW::B, mux.inputs[1]);
 			cell->setPort(TW::C, mux.inputs[2]);
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc
index 7737a629d..7ca43886d 100644
--- a/passes/techmap/nlutmap.cc
+++ b/passes/techmap/nlutmap.cc
@@ -82,7 +82,7 @@ struct NlutmapWorker
 
 			for (auto cell : module->cells())
 			{
-				if (cell->type != ID($lut) || mapped_cells.count(cell))
+				if (cell->type != TW($lut) || mapped_cells.count(cell))
 					continue;
 
 				if (GetSize(cell->getPort(TW::A)) == lut_size || lut_size == 2)
@@ -119,7 +119,7 @@ struct NlutmapWorker
 
 		if (config.assert_mode) {
 			for (auto cell : module->cells())
-				if (cell->type == ID($lut) && !mapped_cells.count(cell))
+				if (cell->type == TW($lut) && !mapped_cells.count(cell))
 					log_error("Insufficient number of LUTs to map all logic cells!\n");
 		}
 
diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc
index 06e3b40be..718efba34 100644
--- a/passes/techmap/pmuxtree.cc
+++ b/passes/techmap/pmuxtree.cc
@@ -89,7 +89,7 @@ struct PmuxtreePass : public Pass {
 		for (auto module : design->selected_modules())
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type != ID($pmux))
+			if (cell->type != TW($pmux))
 				continue;
 
 			SigSpec sig_data = cell->getPort(TW::B);
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index c239c922c..2e1a08dd2 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -319,13 +319,13 @@ struct ShregmapWorker
 				int param_clkpol = -1;
 				int param_enpol = 2;
 
-				if (first_cell->type == ID($_DFF_N_)) param_clkpol = 0;
-				if (first_cell->type == ID($_DFF_P_)) param_clkpol = 1;
+				if (first_cell->type == TW($_DFF_N_)) param_clkpol = 0;
+				if (first_cell->type == TW($_DFF_P_)) param_clkpol = 1;
 
-				if (first_cell->type == ID($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
-				if (first_cell->type == ID($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
-				if (first_cell->type == ID($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
-				if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
+				if (first_cell->type == TW($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
+				if (first_cell->type == TW($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
+				if (first_cell->type == TW($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
+				if (first_cell->type == TW($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
 
 				log_assert(param_clkpol >= 0);
 				first_cell->setParam(ID(CLKPOL), param_clkpol);
@@ -519,19 +519,19 @@ struct ShregmapPass : public Pass {
 			bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
 
 			if (clk_pos && en_none)
-				opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
+				opts.ffcells[TW($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
 			if (clk_neg && en_none)
-				opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
+				opts.ffcells[TW($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
 
 			if (clk_pos && en_pos)
-				opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
+				opts.ffcells[TW($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
 			if (clk_pos && en_neg)
-				opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
+				opts.ffcells[TW($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
 
 			if (clk_neg && en_pos)
-				opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
+				opts.ffcells[TW($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
 			if (clk_neg && en_neg)
-				opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
+				opts.ffcells[TW($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
 
 			if (en_pos || en_neg)
 				opts.ffe = true;
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 1474330b1..1963438de 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -40,7 +40,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 	sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
+		RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_NOT_));
 		transfer_src(gate, cell);
 		gate->setPort(TW::A, sig_a[i]);
 		gate->setPort(TW::Y, sig_y[i]);
@@ -86,17 +86,17 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_b = cell->getPort(TW::B);
 	RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
 
-	if (cell->type != ID($bweqx)) {
+	if (cell->type != TW($bweqx)) {
 		sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
 		sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
 	}
 
 	IdString gate_type;
-	if (cell->type == ID($and))   gate_type = ID($_AND_);
-	if (cell->type == ID($or))    gate_type = ID($_OR_);
-	if (cell->type == ID($xor))   gate_type = ID($_XOR_);
-	if (cell->type == ID($xnor))  gate_type = ID($_XNOR_);
-	if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_);
+	if (cell->type == TW($and))   gate_type = TW($_AND_);
+	if (cell->type == TW($or))    gate_type = TW($_OR_);
+	if (cell->type == TW($xor))   gate_type = TW($_XOR_);
+	if (cell->type == TW($xnor))  gate_type = TW($_XNOR_);
+	if (cell->type == TW($bweqx)) gate_type = TW($_XNOR_);
 	log_assert(!gate_type.empty());
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
@@ -117,11 +117,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 		return;
 
 	if (sig_a.size() == 0) {
-		if (cell->type == ID($reduce_and))  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
-		if (cell->type == ID($reduce_or))   module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
-		if (cell->type == ID($reduce_xor))  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
-		if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
-		if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == TW($reduce_and))  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+		if (cell->type == TW($reduce_or))   module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == TW($reduce_xor))  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == TW($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+		if (cell->type == TW($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 		return;
 	}
 
@@ -131,11 +131,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	IdString gate_type;
-	if (cell->type == ID($reduce_and))  gate_type = ID($_AND_);
-	if (cell->type == ID($reduce_or))   gate_type = ID($_OR_);
-	if (cell->type == ID($reduce_xor))  gate_type = ID($_XOR_);
-	if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_);
-	if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_);
+	if (cell->type == TW($reduce_and))  gate_type = TW($_AND_);
+	if (cell->type == TW($reduce_or))   gate_type = TW($_OR_);
+	if (cell->type == TW($reduce_xor))  gate_type = TW($_XOR_);
+	if (cell->type == TW($reduce_xnor)) gate_type = TW($_XOR_);
+	if (cell->type == TW($reduce_bool)) gate_type = TW($_OR_);
 	log_assert(!gate_type.empty());
 
 	RTLIL::Cell *last_output_cell = NULL;
@@ -162,9 +162,9 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 		sig_a = sig_t;
 	}
 
-	if (cell->type == ID($reduce_xnor)) {
+	if (cell->type == TW($reduce_xnor)) {
 		RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE);
-		RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
+		RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_NOT_));
 		transfer_src(gate, cell);
 		gate->setPort(TW::A, sig_a);
 		gate->setPort(TW::Y, sig_t);
@@ -192,7 +192,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
 				continue;
 			}
 
-			RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_OR_));
+			RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_OR_));
 			transfer_src(gate, cell);
 			gate->setPort(TW::A, sig[i]);
 			gate->setPort(TW::B, sig[i+1]);
@@ -221,7 +221,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 		sig_y = sig_y.extract(0, 1);
 	}
 
-	RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
+	RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_NOT_));
 	transfer_src(gate, cell);
 	gate->setPort(TW::A, sig_a);
 	gate->setPort(TW::Y, sig_y);
@@ -246,8 +246,8 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	IdString gate_type;
-	if (cell->type == ID($logic_and)) gate_type = ID($_AND_);
-	if (cell->type == ID($logic_or))  gate_type = ID($_OR_);
+	if (cell->type == TW($logic_and)) gate_type = TW($_AND_);
+	if (cell->type == TW($logic_or))  gate_type = TW($_OR_);
 	log_assert(!gate_type.empty());
 
 	RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
@@ -263,7 +263,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_b = cell->getPort(TW::B);
 	RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
 	bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
-	bool is_ne = cell->type.in(ID($ne), ID($nex));
+	bool is_ne = cell->type.in(TW($ne), TW($nex));
 
 	RTLIL::SigSpec xor_out = module->addWire(NEW_TWINE, max(GetSize(sig_a), GetSize(sig_b)));
 	RTLIL::Cell *xor_cell = module->addXor(NEW_TWINE, sig_a, sig_b, xor_out, is_signed);
@@ -292,7 +292,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
+		RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
 		transfer_src(gate, cell);
 		gate->setPort(TW::A, sig_a[i]);
 		gate->setPort(TW::B, sig_b[i]);
@@ -309,7 +309,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
+		RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
 		transfer_src(gate, cell);
 		gate->setPort(TW::A, sig_a[i]);
 		gate->setPort(TW::B, sig_b[i]);
@@ -325,7 +325,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_TBUF_));
+		RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_TBUF_));
 		transfer_src(gate, cell);
 		gate->setPort(TW::A, sig_a[i]);
 		gate->setPort(TW::E, sig_e);
@@ -343,7 +343,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
 		SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2);
 		for (int i = 0; i < GetSize(new_data); i += width) {
 			for (int k = 0; k < width; k++) {
-				RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
+				RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
 				transfer_src(gate, cell);
 				gate->setPort(TW::A, data[i*2+k]);
 				gate->setPort(TW::B, data[i*2+width+k]);
@@ -366,7 +366,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
 	for (int idx = 0; GetSize(lut_data) > 1; idx++) {
 		SigSpec new_lut_data = module->addWire(NEW_TWINE, GetSize(lut_data)/2);
 		for (int i = 0; i < GetSize(lut_data); i += 2) {
-			RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
+			RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
 			transfer_src(gate, cell);
 			gate->setPort(TW::A, lut_data[i]);
 			gate->setPort(TW::B, lut_data[i+1]);
@@ -454,7 +454,7 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
 
 		// Implement: B_AND_BITS = B_AND_S[WIDTH*j+i]
 		for (int j = 0; j < s_width; j++) {
-			RTLIL::Cell *and_gate = module->addCell(NEW_TWINE, ID($_AND_));
+			RTLIL::Cell *and_gate = module->addCell(NEW_TWINE, TW($_AND_));
 			transfer_src(and_gate, cell);
 			and_gate->setPort(TW::A, sig_b[j * width + i]);
 			and_gate->setPort(TW::B, sig_s[j]);
@@ -468,7 +468,7 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
 		logic_reduce(module, b_and_bits, cell);
 
 		// Implement: Y[i] = |S ? Y_B[i] : A[i]
-		RTLIL::Cell *mux_gate = module->addCell(NEW_TWINE, ID($_MUX_));
+		RTLIL::Cell *mux_gate = module->addCell(NEW_TWINE, TW($_MUX_));
 		transfer_src(mux_gate, cell);
 		mux_gate->setPort(TW::A, sig_a[i]);
 		mux_gate->setPort(TW::B, b_and_bits);
@@ -479,51 +479,51 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
 
 void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
 {
-	mappers[ID($not)]         = simplemap_not;
-	mappers[ID($pos)]         = simplemap_pos;
-	mappers[ID($buf)]         = simplemap_buf;
-	mappers[ID($and)]         = simplemap_bitop;
-	mappers[ID($or)]          = simplemap_bitop;
-	mappers[ID($xor)]         = simplemap_bitop;
-	mappers[ID($xnor)]        = simplemap_bitop;
-	mappers[ID($bweqx)]       = simplemap_bitop;
-	mappers[ID($reduce_and)]  = simplemap_reduce;
-	mappers[ID($reduce_or)]   = simplemap_reduce;
-	mappers[ID($reduce_xor)]  = simplemap_reduce;
-	mappers[ID($reduce_xnor)] = simplemap_reduce;
-	mappers[ID($reduce_bool)] = simplemap_reduce;
-	mappers[ID($logic_not)]   = simplemap_lognot;
-	mappers[ID($logic_and)]   = simplemap_logbin;
-	mappers[ID($logic_or)]    = simplemap_logbin;
-	mappers[ID($eq)]          = simplemap_eqne;
-	mappers[ID($eqx)]         = simplemap_eqne;
-	mappers[ID($ne)]          = simplemap_eqne;
-	mappers[ID($nex)]         = simplemap_eqne;
-	mappers[ID($mux)]         = simplemap_mux;
-	mappers[ID($pmux)]        = simplemap_pmux;
-	mappers[ID($bwmux)]       = simplemap_bwmux;
-	mappers[ID($tribuf)]      = simplemap_tribuf;
-	mappers[ID($bmux)]        = simplemap_bmux;
-	mappers[ID($lut)]         = simplemap_lut;
-	mappers[ID($sop)]         = simplemap_sop;
-	mappers[ID($slice)]       = simplemap_slice;
-	mappers[ID($concat)]      = simplemap_concat;
-	mappers[ID($sr)]          = simplemap_ff;
-	mappers[ID($ff)]          = simplemap_ff;
-	mappers[ID($dff)]         = simplemap_ff;
-	mappers[ID($dffe)]        = simplemap_ff;
-	mappers[ID($dffsr)]       = simplemap_ff;
-	mappers[ID($dffsre)]      = simplemap_ff;
-	mappers[ID($adff)]        = simplemap_ff;
-	mappers[ID($sdff)]        = simplemap_ff;
-	mappers[ID($adffe)]       = simplemap_ff;
-	mappers[ID($sdffe)]       = simplemap_ff;
-	mappers[ID($sdffce)]      = simplemap_ff;
-	mappers[ID($aldff)]       = simplemap_ff;
-	mappers[ID($aldffe)]      = simplemap_ff;
-	mappers[ID($dlatch)]      = simplemap_ff;
-	mappers[ID($adlatch)]     = simplemap_ff;
-	mappers[ID($dlatchsr)]    = simplemap_ff;
+	mappers[TW($not)]         = simplemap_not;
+	mappers[TW($pos)]         = simplemap_pos;
+	mappers[TW($buf)]         = simplemap_buf;
+	mappers[TW($and)]         = simplemap_bitop;
+	mappers[TW($or)]          = simplemap_bitop;
+	mappers[TW($xor)]         = simplemap_bitop;
+	mappers[TW($xnor)]        = simplemap_bitop;
+	mappers[TW($bweqx)]       = simplemap_bitop;
+	mappers[TW($reduce_and)]  = simplemap_reduce;
+	mappers[TW($reduce_or)]   = simplemap_reduce;
+	mappers[TW($reduce_xor)]  = simplemap_reduce;
+	mappers[TW($reduce_xnor)] = simplemap_reduce;
+	mappers[TW($reduce_bool)] = simplemap_reduce;
+	mappers[TW($logic_not)]   = simplemap_lognot;
+	mappers[TW($logic_and)]   = simplemap_logbin;
+	mappers[TW($logic_or)]    = simplemap_logbin;
+	mappers[TW($eq)]          = simplemap_eqne;
+	mappers[TW($eqx)]         = simplemap_eqne;
+	mappers[TW($ne)]          = simplemap_eqne;
+	mappers[TW($nex)]         = simplemap_eqne;
+	mappers[TW($mux)]         = simplemap_mux;
+	mappers[TW($pmux)]        = simplemap_pmux;
+	mappers[TW($bwmux)]       = simplemap_bwmux;
+	mappers[TW($tribuf)]      = simplemap_tribuf;
+	mappers[TW($bmux)]        = simplemap_bmux;
+	mappers[TW($lut)]         = simplemap_lut;
+	mappers[TW($sop)]         = simplemap_sop;
+	mappers[TW($slice)]       = simplemap_slice;
+	mappers[TW($concat)]      = simplemap_concat;
+	mappers[TW($sr)]          = simplemap_ff;
+	mappers[TW($ff)]          = simplemap_ff;
+	mappers[TW($dff)]         = simplemap_ff;
+	mappers[TW($dffe)]        = simplemap_ff;
+	mappers[TW($dffsr)]       = simplemap_ff;
+	mappers[TW($dffsre)]      = simplemap_ff;
+	mappers[TW($adff)]        = simplemap_ff;
+	mappers[TW($sdff)]        = simplemap_ff;
+	mappers[TW($adffe)]       = simplemap_ff;
+	mappers[TW($sdffe)]       = simplemap_ff;
+	mappers[TW($sdffce)]      = simplemap_ff;
+	mappers[TW($aldff)]       = simplemap_ff;
+	mappers[TW($aldffe)]      = simplemap_ff;
+	mappers[TW($dlatch)]      = simplemap_ff;
+	mappers[TW($adlatch)]     = simplemap_ff;
+	mappers[TW($dlatchsr)]    = simplemap_ff;
 }
 
 void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -577,7 +577,7 @@ struct SimplemapPass : public Pass {
 					continue;
 				if (!design->selected(mod, cell))
 					continue;
-				log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescape());
+				log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescaped());
 				mappers.at(cell->type)(mod, cell);
 				mod->remove(cell);
 			}
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index e725d1aef..2d146c0ee 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -93,17 +93,17 @@ struct TechmapWorker
 				RTLIL::SigBit bit = sigmap(conn.second[i]);
 				if (bit.wire == nullptr) {
 					if (verbose)
-						log("  Constant input on bit %d of port %s: %s\n", i, conn.first.unescape(), log_signal(bit));
-					constmap_info += stringf("|%s %d %d", conn.first.unescape(), i, bit.data);
+						log("  Constant input on bit %d of port %s: %s\n", i, design->twines.unescaped_str(conn.first), log_signal(bit));
+					constmap_info += stringf("|%s %d %d", design->twines.unescaped_str(conn.first), i, bit.data);
 				} else if (connbits_map.count(bit)) {
 					if (verbose)
-						log("  Bit %d of port %s and bit %d of port %s are connected.\n", i, conn.first.unescape(),
-								connbits_map.at(bit).second, connbits_map.at(bit).first.unescape());
-					constmap_info += stringf("|%s %d %s %d", conn.first.unescape(), i,
+						log("  Bit %d of port %s and bit %d of port %s are connected.\n", i, design->twines.unescaped_str(conn.first),
+								connbits_map.at(bit).second, design->twines.unescaped_str(connbits_map.at(bit).first));
+					constmap_info += stringf("|%s %d %s %d", design->twines.unescaped_str(conn.first), i,
 							connbits_map.at(bit).first.unescape(), connbits_map.at(bit).second);
 				} else {
 					connbits_map.emplace(bit, std::make_pair(conn.first, i));
-					constmap_info += stringf("|%s %d", conn.first.unescape(), i);
+					constmap_info += stringf("|%s %d", design->twines.unescaped_str(conn.first), i);
 				}
 			}
 
@@ -146,7 +146,7 @@ struct TechmapWorker
 		if (tpl->processes.size() != 0) {
 			log("Technology map yielded processes:");
 			for (auto &it : tpl->processes)
-				log(" %s",it.first.unescape());
+				log(" design->twines.unescaped_str(%s",it.first));
 			log("\n");
 			if (autoproc_mode) {
 				Pass::call_on_module(tpl->design, tpl, "proc");
@@ -440,7 +440,7 @@ struct TechmapWorker
 
 			if (celltypeMap.count(cell->type) == 0) {
 				if (assert_mode && !cell->type.ends_with("_"))
-					log_error("(ASSERT MODE) No matching template cell for type %s found.\n", cell->type.unescape());
+					log_error("(ASSERT MODE) No matching template cell for type %s found.\n", cell->type.unescaped());
 				continue;
 			}
 
@@ -503,10 +503,10 @@ struct TechmapWorker
 				{
 					if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
 					{
-						std::string m_name = stringf("$extern:%s:%s", extmapper_name, cell->type.unescape());
+						std::string m_name = stringf("$extern:%s:%s", extmapper_name, cell->type.unescaped());
 
 						for (auto &c : cell->parameters)
-							m_name += stringf(":%s=%s", c.first.unescape(), log_signal(c.second));
+							m_name += stringf(":%s=%s", design->twines.unescaped_str(c.first), log_signal(c.second));
 
 						if (extmapper_name == "wrap")
 							m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
@@ -539,15 +539,15 @@ struct TechmapWorker
 							if (extmapper_name == "simplemap") {
 								log("Creating %s with simplemap.\n", extmapper_module);
 								if (simplemap_mappers.count(extmapper_cell->type) == 0)
-									log_error("No simplemap mapper for cell type %s found!\n", extmapper_cell->type.unescape());
+									log_error("No simplemap mapper for cell type %s found!\n", design->twines.unescaped_str(extmapper_cell->type));
 								simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
 								extmapper_module->remove(extmapper_cell);
 							}
 
 							if (extmapper_name == "maccmap") {
 								log("Creating %s with maccmap.\n", extmapper_module);
-								if (!extmapper_cell->type.in(ID($macc), ID($macc_v2)))
-									log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", extmapper_cell->type.unescape());
+								if (!extmapper_cell->type.in(TW($macc), TW($macc_v2)))
+									log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", design->twines.unescaped_str(extmapper_cell->type));
 								maccmap(extmapper_module, extmapper_cell);
 								extmapper_module->remove(extmapper_cell);
 							}
@@ -570,31 +570,31 @@ struct TechmapWorker
 							goto use_wrapper_tpl;
 						}
 
-						auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_module, cell->type.unescape());
+						auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_module, cell->type.unescaped());
 						if (!log_msg_cache.count(msg)) {
 							log_msg_cache.insert(msg);
 							log("%s\n", msg);
 						}
-						log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_module);
+						log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), extmapper_module);
 					}
 					else
 					{
-						auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, cell->type.unescape());
+						auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, cell->type.unescaped());
 						if (!log_msg_cache.count(msg)) {
 							log_msg_cache.insert(msg);
 							log("%s\n", msg);
 						}
-						log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_name);
+						log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), extmapper_name);
 
 						if (extmapper_name == "simplemap") {
 							if (simplemap_mappers.count(cell->type) == 0)
-								log_error("No simplemap mapper for cell type %s found!\n", cell->type.unescape());
+								log_error("No simplemap mapper for cell type %s found!\n", cell->type.unescaped());
 							simplemap_mappers.at(cell->type)(module, cell);
 						}
 
 						if (extmapper_name == "maccmap") {
-							if (!cell->type.in(ID($macc), ID($macc_v2)))
-								log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", cell->type.unescape());
+							if (!cell->type.in(TW($macc), TW($macc_v2)))
+								log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", cell->type.unescaped());
 							maccmap(module, cell);
 						}
 
@@ -623,26 +623,26 @@ struct TechmapWorker
 				}
 
 				if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
-					parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescape());
+					parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescaped());
 				if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0)
 					parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->module->design->twines.str(cell->meta_->name));
 
 				for (auto &conn : cell->connections()) {
-					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape())) != 0) {
+					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", design->twines.unescaped_str(conn.first))) != 0) {
 						std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
 						for (auto &bit : v)
 							bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
-						parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
+						parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", design->twines.unescaped_str(conn.first)), RTLIL::SigSpec(v).as_const());
 					}
-					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape())) != 0) {
+					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", design->twines.unescaped_str(conn.first))) != 0) {
 						std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
 						for (auto &bit : v)
 							if (bit.wire != nullptr)
 								bit = RTLIL::SigBit(RTLIL::State::Sx);
-						parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
+						parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", design->twines.unescaped_str(conn.first)), RTLIL::SigSpec(v).as_const());
 					}
-					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape())) != 0) {
-						parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape()), initvals(conn.second));
+					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", design->twines.unescaped_str(conn.first))) != 0) {
+						parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", design->twines.unescaped_str(conn.first)), initvals(conn.second));
 					}
 				}
 
@@ -655,7 +655,7 @@ struct TechmapWorker
 					unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
 
 					for (auto &conn : cell->connections())
-						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
+						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first))) != 0) {
 							for (auto &bit : sigmap(conn.second))
 								if (unique_bit_id.count(bit) == 0)
 									unique_bit_id[bit] = unique_bit_id_counter++;
@@ -672,7 +672,7 @@ struct TechmapWorker
 						parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
 
 					for (auto &conn : cell->connections())
-						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
+						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first))) != 0) {
 							SigSpec sm = sigmap(conn.second);
 							RTLIL::Const::Builder builder(GetSize(sm) * bits);
 							for (auto &bit : sm) {
@@ -682,7 +682,7 @@ struct TechmapWorker
 									val = val >> 1;
 								}
 							}
-							parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape()), builder.build());
+							parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first)), builder.build());
 						}
 				}
 
@@ -731,7 +731,7 @@ struct TechmapWorker
 								RTLIL::SigSpec value = elem.value;
 								if (value.is_fully_const() && value.as_bool()) {
 									log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
-											derived_name.c_str(), elem.wire->name.unescape(), log_signal(value));
+											derived_name.c_str(), design->twines.unescaped_str(elem.wire->name), log_signal(value));
 									techmap_do_cache[tpl] = false;
 								}
 							}
@@ -748,7 +748,7 @@ struct TechmapWorker
 							auto &data = it.second.front();
 
 							if (!data.value.is_fully_const())
-								log_error("Techmap yielded config wire %s with non-const value %s.\n", data.wire->name.unescape(), log_signal(data.value));
+								log_error("Techmap yielded config wire %s with non-const value %s.\n", design->twines.unescaped_str(data.wire->name), log_signal(data.value));
 
 							techmap_wire_names.erase(it.first);
 
@@ -765,7 +765,7 @@ struct TechmapWorker
 
 								log("Analyzing pattern of constant bits for this cell:\n");
 								IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
-								log("Creating constmapped module `%s'.\n", new_tpl_name.unescape());
+								log("Creating constmapped module `%s'.\n", design->twines.unescaped_str(new_tpl_name));
 								log_assert(map->module(new_tpl_name) == nullptr);
 
 								RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
@@ -873,16 +873,16 @@ struct TechmapWorker
 					TechmapWires twd = techmap_find_special_wires(tpl);
 					for (auto &it : twd) {
 						if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_"))
-							log_error("Techmap yielded unknown config wire %s.\n", it.first.unescape());
+							log_error("Techmap yielded unknown config wire %s.\n", design->twines.unescaped_str(it.first));
 						if (techmap_do_cache[tpl])
 							for (auto &it2 : it.second)
 								if (!it2.value.is_fully_const())
-									log_error("Techmap yielded config wire %s with non-const value %s.\n", it2.wire->name.unescape(), log_signal(it2.value));
+									log_error("Techmap yielded config wire %s with non-const value %s.\n", design->twines.unescaped_str(it2.wire->name), log_signal(it2.value));
 						techmap_wire_names.erase(it.first);
 					}
 
 					for (auto &it : techmap_wire_names)
-						log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", it.unescape());
+						log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", design->twines.unescaped_str(it));
 
 					if (recursive_mode) {
 						if (log_continue) {
@@ -938,12 +938,12 @@ struct TechmapWorker
 				}
 				else
 				{
-					auto msg = stringf("Using template %s for cells of type %s.", tpl, cell->type.unescape());
+					auto msg = stringf("Using template %s for cells of type %s.", tpl, cell->type.unescaped());
 					if (!log_msg_cache.count(msg)) {
 						log_msg_cache.insert(msg);
 						log("%s\n", msg);
 					}
-					log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), tpl);
+					log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), tpl);
 					techmap_module_worker(design, module, cell, tpl);
 					cell = nullptr;
 				}
@@ -953,7 +953,7 @@ struct TechmapWorker
 			}
 
 			if (assert_mode && !mapped_cell)
-				log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", module, cell, cell->type.unescape());
+				log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
 
 			handled_cells.insert(cell);
 		}
@@ -1275,8 +1275,8 @@ struct TechmapPass : public Pass {
 			i.second.sort(RTLIL::sort_by_id_str());
 			std::string maps = "";
 			for (auto &map : i.second)
-				maps += stringf(" %s", map.unescape());
-			log_debug("    %s:%s\n", i.first.unescape(), maps);
+				maps += stringf(" %s", design->twines.unescaped_str(map));
+			log_debug("    %s:%s\n", design->twines.unescaped_str(i.first), maps);
 		}
 		log_debug("\n");
 
diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc
index c33233999..a75eddd8b 100644
--- a/passes/techmap/tribuf.cc
+++ b/passes/techmap/tribuf.cc
@@ -65,16 +65,16 @@ struct TribufWorker {
 
 		for (auto cell : module->selected_cells())
 		{
-			if (cell->type == ID($tribuf))
+			if (cell->type == TW($tribuf))
 				tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
 
-			if (cell->type == ID($_TBUF_))
+			if (cell->type == TW($_TBUF_))
 				tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
 
-			if (cell->type.in(ID($mux), ID($_MUX_)))
+			if (cell->type.in(TW($mux), TW($_MUX_)))
 			{
-				IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E;
-				IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
+				IdString en_port = cell->type == TW($mux) ? ID::EN : ID::E;
+				IdString tri_type = cell->type == TW($mux) ? TW($tribuf) : TW($_TBUF_);
 
 				if (is_all_z(cell->getPort(TW::A)) && is_all_z(cell->getPort(TW::B))) {
 					module->remove(cell);
@@ -130,13 +130,13 @@ struct TribufWorker {
 						for (auto other_cell : it.second) {
 							if (other_cell == cell)
 								continue;
-							else if (other_cell->type == ID($tribuf))
+							else if (other_cell->type == TW($tribuf))
 								others_s.append(other_cell->getPort(TW::EN));
 							else
 								others_s.append(other_cell->getPort(TW::E));
 						}
 
-						auto cell_s = cell->type == ID($tribuf) ? cell->getPort(TW::EN) : cell->getPort(TW::E);
+						auto cell_s = cell->type == TW($tribuf) ? cell->getPort(TW::EN) : cell->getPort(TW::E);
 
 						auto other_s = module->ReduceOr(NEW_TWINE, others_s);
 
@@ -154,7 +154,7 @@ struct TribufWorker {
 
 				SigSpec pmux_b, pmux_s;
 				for (auto cell : it.second) {
-					if (cell->type == ID($tribuf))
+					if (cell->type == TW($tribuf))
 						pmux_s.append(cell->getPort(TW::EN));
 					else
 						pmux_s.append(cell->getPort(TW::E));
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index 5b6a3adaf..092b992eb 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -68,7 +68,7 @@ struct ZinitPass : public Pass {
 
 				FfData ff(&initvals, cell);
 
-				log("FF init value for cell %s (%s): %s = %s\n", cell, cell->type.unescape(),
+				log("FF init value for cell %s (%s): %s = %s\n", cell, cell->type.unescaped(),
 						log_signal(ff.sig_q), log_signal(ff.val_init));
 
 				pool<int> bits;
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 825763fda..1c22ee3cb 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -45,10 +45,10 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 	RTLIL::Cell *cell = module->addCell(design->twines.add(Twine{ID(UUT).str()}), cell_type);
 	RTLIL::Wire *wire;
 
-	if (cell_type.in(ID($mux), ID($pmux)))
+	if (cell_type.in(TW($mux), TW($pmux)))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
-		int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8);
+		int swidth = cell_type == TW($mux) ? 1 : 1 + xorshift32(8);
 
 		wire = module->addWire(TW::A);
 		wire->width = width;
@@ -71,7 +71,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type.in(ID($_MUX_), ID($_NMUX_)))
+	if (cell_type.in(TW($_MUX_), TW($_NMUX_)))
 	{
 		wire = module->addWire(TW::A);
 		wire->width = 1;
@@ -94,7 +94,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type == ID($bmux))
+	if (cell_type == TW($bmux))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
 		int swidth = 1 + xorshift32(4 * bloat_factor);
@@ -115,7 +115,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type == ID($demux))
+	if (cell_type == TW($demux))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
 		int swidth = 1 + xorshift32(6 * bloat_factor);
@@ -136,7 +136,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type == ID($fa))
+	if (cell_type == TW($fa))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
 
@@ -166,7 +166,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type == ID($lcu))
+	if (cell_type == TW($lcu))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
 
@@ -190,7 +190,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::CO, wire);
 	}
 
-	if (cell_type == ID($macc_v2))
+	if (cell_type == TW($macc_v2))
 	{
 		Macc macc;
 		int width = 1 + xorshift32(8 * bloat_factor);
@@ -234,7 +234,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type == ID($lut))
+	if (cell_type == TW($lut))
 	{
 		int width = 1 + xorshift32(6 * bloat_factor);
 
@@ -254,7 +254,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setParam(ID::LUT, config.as_const());
 	}
 
-	if (cell_type == ID($sop))
+	if (cell_type == TW($sop))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
 		int depth = 1 + xorshift32(8 * bloat_factor);
@@ -355,22 +355,22 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type.in(ID($shiftx))) {
+	if (cell_type.in(TW($shiftx))) {
 		cell->parameters[ID::A_SIGNED] = false;
 	}
 
-	if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
+	if (cell_type.in(TW($shl), TW($shr), TW($sshl), TW($sshr))) {
 		cell->parameters[ID::B_SIGNED] = false;
 	}
 
-	if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+	if (muxdiv && cell_type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
 		auto b_not_zero = module->ReduceBool(NEW_TWINE, cell->getPort(TW::B));
 		auto div_out = module->addWire(NEW_TWINE, GetSize(cell->getPort(TW::Y)));
 		module->addMux(NEW_TWINE, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(TW::Y));
 		cell->setPort(TW::Y, div_out);
 	}
 
-	if (cell_type == ID($alu))
+	if (cell_type == TW($alu))
 	{
 		wire = module->addWire(TW::CI);
 		wire->port_input = true;
@@ -391,7 +391,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::CO, wire);
 	}
 
-	if (cell_type == ID($slice))
+	if (cell_type == TW($slice))
 	{
 		int a_size = GetSize(cell->getPort(TW::A));
 		int y_size = 1;
@@ -407,7 +407,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 			cell->setParam(ID::OFFSET, 0);
 	}
 
-	if (cell_type == ID($concat))
+	if (cell_type == TW($concat))
 	{
 		wire = module->addWire(TW::Y);
 		wire->width = GetSize(cell->getPort(TW::A)) + GetSize(cell->getPort(TW::B));
@@ -415,7 +415,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type == ID($buf))
+	if (cell_type == TW($buf))
 	{
 		wire = module->addWire(TW::Y);
 		wire->width = GetSize(cell->getPort(TW::A));
@@ -423,14 +423,14 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(TW::Y, wire);
 	}
 
-	if (cell_type.in(ID($bwmux), ID($bweqx)))
+	if (cell_type.in(TW($bwmux), TW($bweqx)))
 	{
 		int a_size = GetSize(cell->getPort(TW::A));
 		wire = module->addWire(TW::B);
 		wire->width = a_size;
 		wire->port_input = true;
 		cell->setPort(TW::B, wire);
-		if (cell_type == ID($bwmux))
+		if (cell_type == TW($bwmux))
 		{
 			wire = module->addWire(TW::S);
 			wire->width = a_size;
@@ -984,101 +984,101 @@ struct TestCellPass : public Pass {
 		std::map<IdString, std::string> cell_types;
 		std::vector<IdString> selected_cell_types;
 
-		cell_types[ID($not)] = "ASY";
-		cell_types[ID($pos)] = "ASY";
-		cell_types[ID($neg)] = "ASY";
+		cell_types[TW($not)] = "ASY";
+		cell_types[TW($pos)] = "ASY";
+		cell_types[TW($neg)] = "ASY";
 		// $buf is unsupported with techmap -assert
 		if (techmap_cmd.compare("techmap -assert") != 0)
-			cell_types[ID($buf)] = "A";
+			cell_types[TW($buf)] = "A";
 
-		cell_types[ID($and)]  = "ABSY";
-		cell_types[ID($or)]   = "ABSY";
-		cell_types[ID($xor)]  = "ABSY";
-		cell_types[ID($xnor)] = "ABSY";
+		cell_types[TW($and)]  = "ABSY";
+		cell_types[TW($or)]   = "ABSY";
+		cell_types[TW($xor)]  = "ABSY";
+		cell_types[TW($xnor)] = "ABSY";
 
-		cell_types[ID($reduce_and)]  = "ASY";
-		cell_types[ID($reduce_or)]   = "ASY";
-		cell_types[ID($reduce_xor)]  = "ASY";
-		cell_types[ID($reduce_xnor)] = "ASY";
-		cell_types[ID($reduce_bool)] = "ASY";
+		cell_types[TW($reduce_and)]  = "ASY";
+		cell_types[TW($reduce_or)]   = "ASY";
+		cell_types[TW($reduce_xor)]  = "ASY";
+		cell_types[TW($reduce_xnor)] = "ASY";
+		cell_types[TW($reduce_bool)] = "ASY";
 
-		cell_types[ID($shl)]    = "ABshY";
-		cell_types[ID($shr)]    = "ABshY";
-		cell_types[ID($sshl)]   = "ABshY";
-		cell_types[ID($sshr)]   = "ABshY";
-		cell_types[ID($shift)]  = "ABshY";
-		cell_types[ID($shiftx)] = "ABshY";
+		cell_types[TW($shl)]    = "ABshY";
+		cell_types[TW($shr)]    = "ABshY";
+		cell_types[TW($sshl)]   = "ABshY";
+		cell_types[TW($sshr)]   = "ABshY";
+		cell_types[TW($shift)]  = "ABshY";
+		cell_types[TW($shiftx)] = "ABshY";
 
-		cell_types[ID($lt)]  = "ABSY";
-		cell_types[ID($le)]  = "ABSY";
-		cell_types[ID($eq)]  = "ABSY";
-		cell_types[ID($ne)]  = "ABSY";
+		cell_types[TW($lt)]  = "ABSY";
+		cell_types[TW($le)]  = "ABSY";
+		cell_types[TW($eq)]  = "ABSY";
+		cell_types[TW($ne)]  = "ABSY";
 		// $eqx, $nex, and $bweqx don't work in sat, and are unsupported with
 		// 'techmap -assert'
 		if (nosat && techmap_cmd.compare("techmap -assert") != 0)
 		{
-			cell_types[ID($eqx)] = "ABSY";
-			cell_types[ID($nex)] = "ABSY";
-			cell_types[ID($bweqx)] = "A";
+			cell_types[TW($eqx)] = "ABSY";
+			cell_types[TW($nex)] = "ABSY";
+			cell_types[TW($bweqx)] = "A";
 		}
-		cell_types[ID($ge)]  = "ABSY";
-		cell_types[ID($gt)]  = "ABSY";
+		cell_types[TW($ge)]  = "ABSY";
+		cell_types[TW($gt)]  = "ABSY";
 
-		cell_types[ID($add)] = "ABSY";
-		cell_types[ID($sub)] = "ABSY";
-		cell_types[ID($mul)] = "ABSY";
-		cell_types[ID($div)] = "ABSY";
-		cell_types[ID($mod)] = "ABSY";
-		cell_types[ID($divfloor)] = "ABSY";
-		cell_types[ID($modfloor)] = "ABSY";
+		cell_types[TW($add)] = "ABSY";
+		cell_types[TW($sub)] = "ABSY";
+		cell_types[TW($mul)] = "ABSY";
+		cell_types[TW($div)] = "ABSY";
+		cell_types[TW($mod)] = "ABSY";
+		cell_types[TW($divfloor)] = "ABSY";
+		cell_types[TW($modfloor)] = "ABSY";
 		// $pow doesnt work in sat, not supported with 'techmap -assert', and only
 		// only partially supported with '-simlib'
 		if (nosat && techmap_cmd.compare("aigmap") == 0)
-			cell_types[ID($pow)] = "ABsY";
+			cell_types[TW($pow)] = "ABsY";
 
-		cell_types[ID($logic_not)] = "ASY";
-		cell_types[ID($logic_and)] = "ABSY";
-		cell_types[ID($logic_or)]  = "ABSY";
+		cell_types[TW($logic_not)] = "ASY";
+		cell_types[TW($logic_and)] = "ABSY";
+		cell_types[TW($logic_or)]  = "ABSY";
 
-		cell_types[ID($mux)] = "*";
-		cell_types[ID($bmux)] = "*";
-		cell_types[ID($demux)] = "*";
+		cell_types[TW($mux)] = "*";
+		cell_types[TW($bmux)] = "*";
+		cell_types[TW($demux)] = "*";
 		// $pmux doesn't work in sat, and is not supported with 'techmap -assert' or
 		// '-simlib'
 		if (nosat && techmap_cmd.compare("aigmap") == 0)
-			cell_types[ID($pmux)] = "*";
-		cell_types[ID($bwmux)] = "A";
+			cell_types[TW($pmux)] = "*";
+		cell_types[TW($bwmux)] = "A";
 
-		cell_types[ID($slice)] = "A";
-		cell_types[ID($concat)] = "AB";
+		cell_types[TW($slice)] = "A";
+		cell_types[TW($concat)] = "AB";
 
-		cell_types[ID($lut)] = "*";
-		cell_types[ID($sop)] = "*";
-		cell_types[ID($alu)] = "ABSY";
-		cell_types[ID($lcu)] = "*";
-		cell_types[ID($macc_v2)] = "*";
-		cell_types[ID($fa)] = "*";
+		cell_types[TW($lut)] = "*";
+		cell_types[TW($sop)] = "*";
+		cell_types[TW($alu)] = "ABSY";
+		cell_types[TW($lcu)] = "*";
+		cell_types[TW($macc_v2)] = "*";
+		cell_types[TW($fa)] = "*";
 
-		cell_types[ID($_BUF_)] = "AYb";
-		cell_types[ID($_NOT_)] = "AYb";
-		cell_types[ID($_AND_)] = "ABYb";
-		cell_types[ID($_NAND_)] = "ABYb";
-		cell_types[ID($_OR_)] = "ABYb";
-		cell_types[ID($_NOR_)] = "ABYb";
-		cell_types[ID($_XOR_)] = "ABYb";
-		cell_types[ID($_XNOR_)] = "ABYb";
-		cell_types[ID($_ANDNOT_)] = "ABYb";
-		cell_types[ID($_ORNOT_)] = "ABYb";
-		cell_types[ID($_MUX_)] = "*";
-		cell_types[ID($_NMUX_)] = "*";
+		cell_types[TW($_BUF_)] = "AYb";
+		cell_types[TW($_NOT_)] = "AYb";
+		cell_types[TW($_AND_)] = "ABYb";
+		cell_types[TW($_NAND_)] = "ABYb";
+		cell_types[TW($_OR_)] = "ABYb";
+		cell_types[TW($_NOR_)] = "ABYb";
+		cell_types[TW($_XOR_)] = "ABYb";
+		cell_types[TW($_XNOR_)] = "ABYb";
+		cell_types[TW($_ANDNOT_)] = "ABYb";
+		cell_types[TW($_ORNOT_)] = "ABYb";
+		cell_types[TW($_MUX_)] = "*";
+		cell_types[TW($_NMUX_)] = "*";
 		// wide $_MUX_ cells are not yet implemented
-		// cell_types[ID($_MUX4_)] = "*";
-		// cell_types[ID($_MUX8_)] = "*";
-		// cell_types[ID($_MUX16_)] = "*";
-		cell_types[ID($_AOI3_)] = "ABCYb";
-		cell_types[ID($_OAI3_)] = "ABCYb";
-		cell_types[ID($_AOI4_)] = "ABCDYb";
-		cell_types[ID($_OAI4_)] = "ABCDYb";
+		// cell_types[TW($_MUX4_)] = "*";
+		// cell_types[TW($_MUX8_)] = "*";
+		// cell_types[TW($_MUX16_)] = "*";
+		cell_types[TW($_AOI3_)] = "ABCYb";
+		cell_types[TW($_OAI3_)] = "ABCYb";
+		cell_types[TW($_AOI4_)] = "ABCDYb";
+		cell_types[TW($_OAI4_)] = "ABCDYb";
 
 		for (; argidx < GetSize(args); argidx++)
 		{
@@ -1106,10 +1106,10 @@ struct TestCellPass : public Pass {
 				int charcount = 100;
 				for (auto &it : cell_types) {
 					if (charcount > 60) {
-						cell_type_list += stringf("\n%s", it.first.unescape());
+						cell_type_list += stringf("\n%s", design->twines.unescaped_str(it.first));
 						charcount = 0;
 					} else
-						cell_type_list += stringf(" %s", it.first.unescape());
+						cell_type_list += stringf(" %s", design->twines.unescaped_str(it.first));
 					charcount += GetSize(it.first);
 				}
 				log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc
index 408ce5d75..93117ec59 100644
--- a/techlibs/anlogic/anlogic_fixcarry.cc
+++ b/techlibs/anlogic/anlogic_fixcarry.cc
@@ -69,7 +69,7 @@ static void fix_carry_chain(Module *module)
 				continue;
 
 			adders_to_fix_cells.push_back(cell);
-			log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescape(), cell);
+			log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescaped(), cell);
 		}
 	}
 
@@ -78,7 +78,7 @@ static void fix_carry_chain(Module *module)
 		SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c));
 		SigBit canonical_bit = sigmap(bit_ci);
 		auto bit = mapping_bits.at(canonical_bit);
-		log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
+		log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescaped(), cell);
 		Cell *c = module->addCell(NEW_TWINE, ID(AL_MAP_ADDER));
 		SigBit new_bit = module->addWire(NEW_TWINE);
 		SigBit dummy_bit = module->addWire(NEW_TWINE);
diff --git a/techlibs/common/opensta.cc b/techlibs/common/opensta.cc
index 6061f6b74..9c8bf41dd 100644
--- a/techlibs/common/opensta.cc
+++ b/techlibs/common/opensta.cc
@@ -98,7 +98,7 @@ struct OpenstaPass : public Pass
 
 		f_script << "read_verilog " << verilog_filename << "\n";
 		f_script << "read_lib " << liberty_filename << "\n";
-		f_script << "link_design " << top_mod->name.unescape() << "\n";
+		f_script << "link_design " << design->twines.unescaped_str(top_mod->name) << "\n";
 		f_script << "read_sdc " << sdc_filename << "\n";
 		f_script << "write_sdc " << sdc_expanded_filename << "\n";
 		f_script.close();
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index e2c30d50a..539a9d38e 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -47,7 +47,7 @@ struct Coolrunner2SopPass : public Pass {
 			dict<SigBit, tuple<SigBit, Cell*>> not_cells;
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == ID($_NOT_))
+				if (cell->type == TW($_NOT_))
 				{
 					auto not_input = sigmap(cell->getPort(TW::A)[0]);
 					auto not_output = sigmap(cell->getPort(TW::Y)[0]);
@@ -85,7 +85,7 @@ struct Coolrunner2SopPass : public Pass {
 			// Process $sop cells
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == ID($sop))
+				if (cell->type == TW($sop))
 				{
 					// Read the inputs/outputs/parameters of the $sop cell
 					auto sop_inputs = sigmap(cell->getPort(TW::A));
diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc
index cb415ffa3..ada8f7393 100644
--- a/techlibs/efinix/efinix_fixcarry.cc
+++ b/techlibs/efinix/efinix_fixcarry.cc
@@ -65,7 +65,7 @@ static void fix_carry_chain(Module *module)
 				continue;
 
 			adders_to_fix_cells.push_back(cell);
-			log("Found %s cell named %s with invalid CI signal.\n", cell->type.unescape(), cell);
+			log("Found %s cell named %s with invalid CI signal.\n", cell->type.unescaped(), cell);
 		}
 	}
 
@@ -74,7 +74,7 @@ static void fix_carry_chain(Module *module)
 		SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI));
 		SigBit canonical_bit = sigmap(bit_ci);
 		auto bit = mapping_bits.at(canonical_bit);
-		log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
+		log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescaped(), cell);
 		Cell *c = module->addCell(NEW_TWINE, ID(EFX_ADD));
 		SigBit new_bit = module->addWire(NEW_TWINE);
 		c->setParam(ID(I0_POLARITY), State::S1);
diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc
index 0c1f39e32..03ed998cd 100644
--- a/techlibs/gatemate/gatemate_foldinv.cc
+++ b/techlibs/gatemate/gatemate_foldinv.cc
@@ -68,7 +68,7 @@ struct FoldInvWorker {
     void find_inverted_bits()
     {
         for (auto cell : module->selected_cells()) {
-            if (cell->type != ID($__CC_NOT))
+            if (cell->type != TW($__CC_NOT))
                 continue;
             SigBit a = sigmap(cell->getPort(TW::A)[0]);
             SigBit y = sigmap(cell->getPort(TW::Y)[0]);
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index 30e6d99cd..6851b41e0 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -86,7 +86,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
 		cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
 
 	log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
-			cell->module, cell, cell_type.c_str()+1, cell->type.unescape());
+			cell->module, cell, cell_type.c_str()+1, cell->type.unescaped());
 }
 
 struct Greenpak4DffInvPass : public Pass {
diff --git a/techlibs/ice40/ice40_dsp.cc b/techlibs/ice40/ice40_dsp.cc
index a63105348..2fce3e696 100644
--- a/techlibs/ice40/ice40_dsp.cc
+++ b/techlibs/ice40/ice40_dsp.cc
@@ -31,15 +31,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
 
-	log_debug("ffA:    %s\n", st.ffA ? st.ffA->name.unescape() : "--");
-	log_debug("ffB:    %s\n", st.ffB ? st.ffB->name.unescape() : "--");
-	log_debug("ffCD:   %s\n", st.ffCD ? st.ffCD->name.unescape() : "--");
-	log_debug("mul:    %s\n", st.mul ? st.mul->name.unescape() : "--");
-	log_debug("ffFJKG: %s\n", st.ffFJKG ? st.ffFJKG->name.unescape() : "--");
-	log_debug("ffH:    %s\n", st.ffH ? st.ffH->name.unescape() : "--");
-	log_debug("add:    %s\n", st.add ? st.add->name.unescape() : "--");
-	log_debug("mux:    %s\n", st.mux ? st.mux->name.unescape() : "--");
-	log_debug("ffO:    %s\n", st.ffO ? st.ffO->name.unescape() : "--");
+	log_debug("ffA:    %s\n", st.ffA ? design->twines.unescaped_str(st.ffA->name) : "--");
+	log_debug("ffB:    %s\n", st.ffB ? design->twines.unescaped_str(st.ffB->name) : "--");
+	log_debug("ffCD:   %s\n", st.ffCD ? design->twines.unescaped_str(st.ffCD->name) : "--");
+	log_debug("mul:    %s\n", st.mul ? design->twines.unescaped_str(st.mul->name) : "--");
+	log_debug("ffFJKG: %s\n", st.ffFJKG ? design->twines.unescaped_str(st.ffFJKG->name) : "--");
+	log_debug("ffH:    %s\n", st.ffH ? design->twines.unescaped_str(st.ffH->name) : "--");
+	log_debug("add:    %s\n", st.add ? design->twines.unescaped_str(st.add->name) : "--");
+	log_debug("mux:    %s\n", st.mux ? design->twines.unescaped_str(st.mux->name) : "--");
+	log_debug("ffO:    %s\n", st.ffO ? design->twines.unescaped_str(st.ffO->name) : "--");
 	log_debug("\n");
 
 	if (GetSize(st.sigA) > 16) {
@@ -63,8 +63,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	}
 
 	Cell *cell = st.mul;
-	if (cell->type == ID($mul)) {
-		log("  replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape());
+	if (cell->type == TW($mul)) {
+		log("  replacing %s with SB_MAC16 cell.\n", design->twines.unescaped_str(st.mul->type));
 
 		cell = pm.module->addCell(NEW_TWINE, ID(SB_MAC16));
 		pm.module->swap_names(cell, st.mul);
@@ -196,11 +196,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	if (st.add) {
 		accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
 		if (accum)
-			log("  accumulator %s (%s)\n", st.add, st.add->type.unescape());
+			log("  accumulator %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
 		else
-			log("  adder %s (%s)\n", st.add, st.add->type.unescape());
-		cell->setPort(TW::ADDSUBTOP, st.add->type == ID($add) ? State::S0 : State::S1);
-		cell->setPort(TW::ADDSUBBOT, st.add->type == ID($add) ? State::S0 : State::S1);
+			log("  adder %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
+		cell->setPort(TW::ADDSUBTOP, st.add->type == TW($add) ? State::S0 : State::S1);
+		cell->setPort(TW::ADDSUBBOT, st.add->type == TW($add) ? State::S0 : State::S1);
 	} else {
 		cell->setPort(TW::ADDSUBTOP, State::S0);
 		cell->setPort(TW::ADDSUBBOT, State::S0);
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 07f386a9b..10bc00043 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -41,7 +41,7 @@ static void run_ice40_opts(Module *module)
 
 	for (auto cell : module->selected_cells())
 	{
-		if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), ID($__ICE40_CARRY_WRAPPER)))
+		if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), TW($__ICE40_CARRY_WRAPPER)))
 			continue;
 		if (cell->has_keep_attr())
 			continue;
@@ -89,7 +89,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == ID($__ICE40_CARRY_WRAPPER))
+		if (cell->type == TW($__ICE40_CARRY_WRAPPER))
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -138,7 +138,7 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						module, cell, log_signal(replacement_output));
-				cell->type = ID($lut);
+				cell->type = TW($lut);
 				auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
 				cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) });
 				cell->setPort(TW::Y, cell->getPort(TW::O));
@@ -177,7 +177,7 @@ static void run_ice40_opts(Module *module)
 		module->design->scratchpad_set_bool("opt.did_something", true);
 		log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
 
-		cell->type = ID($lut);
+		cell->type = TW($lut);
 		cell->setParam(ID::WIDTH, 4);
 		cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
 		cell->unsetParam(ID(LUT_INIT));
diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc
index d8fa85b78..a9652f86b 100644
--- a/techlibs/ice40/ice40_wrapcarry.cc
+++ b/techlibs/ice40/ice40_wrapcarry.cc
@@ -31,13 +31,13 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
 
 #if 0
 	log("\n");
-	log("carry: %s\n", st.carry ? st.carry->name.unescape() : "--");
-	log("lut:   %s\n", st.lut ? st.lut->name.unescape() : "--");
+	log("carry: %s\n", st.carry ? design->twines.unescaped_str(st.carry->name) : "--");
+	log("lut:   %s\n", st.lut ? design->twines.unescaped_str(st.lut->name) : "--");
 #endif
 
 	log("  replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
 
-	Cell *cell = pm.module->addCell(NEW_TWINE, ID($__ICE40_CARRY_WRAPPER));
+	Cell *cell = pm.module->addCell(NEW_TWINE, TW($__ICE40_CARRY_WRAPPER));
 	pm.module->swap_names(cell, st.carry);
 
 	cell->setPort(TW::A, st.carry->getPort(TW::I0));
@@ -131,7 +131,7 @@ struct Ice40WrapCarryPass : public Pass {
 				ice40_wrapcarry_pm(module, &sigmap, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
 			} else {
 				for (auto cell : module->selected_cells()) {
-					if (cell->type != ID($__ICE40_CARRY_WRAPPER))
+					if (cell->type != TW($__ICE40_CARRY_WRAPPER))
 						continue;
 
 					auto carry = module->addCell(NEW_TWINE, ID(SB_CARRY));
@@ -141,7 +141,7 @@ struct Ice40WrapCarryPass : public Pass {
 					carry->setPort(TW::CO, cell->getPort(TW::CO));
 					module->swap_names(carry, cell);
 					auto lut_name = cell->attributes.at(IdString{"\\SB_LUT4.name"}, Const(NEW_ID.str())).decode_string();
-					auto lut = module->addCell(lut_name, ID($lut));
+					auto lut = module->addCell(lut_name, TW($lut));
 					lut->setParam(ID::WIDTH, 4);
 					lut->setParam(ID::LUT, cell->getParam(ID::LUT));
 					auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));
diff --git a/techlibs/lattice/lattice_gsr.cc b/techlibs/lattice/lattice_gsr.cc
index 3903f04c4..6fee611da 100644
--- a/techlibs/lattice/lattice_gsr.cc
+++ b/techlibs/lattice/lattice_gsr.cc
@@ -100,7 +100,7 @@ struct LatticeGsrPass : public Pass {
 			log_debug("GSR net in module %s is %s.\n", module, log_signal(gsr));
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type != ID($_NOT_))
+				if (cell->type != TW($_NOT_))
 					continue;
 				SigSpec sig_a = cell->getPort(TW::A), sig_y = cell->getPort(TW::Y);
 				if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
diff --git a/techlibs/microchip/microchip_dsp.cc b/techlibs/microchip/microchip_dsp.cc
index 7d706d87f..77a0718c2 100644
--- a/techlibs/microchip/microchip_dsp.cc
+++ b/techlibs/microchip/microchip_dsp.cc
@@ -37,7 +37,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
 	// pack pre-adder
 	if (st.preAdderStatic) {
 		SigSpec &pasub = cell->connections_.at(ID(PASUB));
-		log("  static PASUB preadder %s (%s)\n", st.preAdderStatic, st.preAdderStatic->type.unescape());
+		log("  static PASUB preadder %s (%s)\n", st.preAdderStatic, design->twines.unescaped_str(st.preAdderStatic->type));
 		bool D_SIGNED = st.preAdderStatic->getParam(ID::B_SIGNED).as_bool();
 		bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
 		st.sigB.extend_u0(18, B_SIGNED);
@@ -49,9 +49,9 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
 		cell->setPort(TW::D, st.sigD);
 		// MACC_PA supports both addition and subtraction with the pre-adder.
 		//   Affects the sign of the 'D' port.
-		if (st.preAdderStatic->type == ID($add))
+		if (st.preAdderStatic->type == TW($add))
 			pasub[0] = State::S0;
-		else if (st.preAdderStatic->type == ID($sub))
+		else if (st.preAdderStatic->type == TW($sub))
 			pasub[0] = State::S1;
 		else
 			log_assert(!"strange pre-adder type");
@@ -60,13 +60,13 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
 	}
 	// pack post-adder
 	if (st.postAdderStatic) {
-		log("  postadder %s (%s)\n", st.postAdderStatic, st.postAdderStatic->type.unescape());
+		log("  postadder %s (%s)\n", st.postAdderStatic, design->twines.unescaped_str(st.postAdderStatic->type));
 		SigSpec &sub = cell->connections_.at(ID(SUB));
 		// Post-adder in MACC_PA also supports subtraction
 		//   Determines the sign of the output from the multiplier.
-		if (st.postAdderStatic->type == ID($add))
+		if (st.postAdderStatic->type == TW($add))
 			sub[0] = State::S0;
-		else if (st.postAdderStatic->type == ID($sub))
+		else if (st.postAdderStatic->type == TW($sub))
 			sub[0] = State::S1;
 		else
 			log_assert(!"strange post-adder type");
@@ -94,12 +94,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstport != IdString()) {
-				if (ff->type.in(ID($sdff), ID($sdffe))) {
+				if (ff->type.in(TW($sdff), TW($sdffe))) {
 					SigSpec srst = ff->getPort(TW::SRST);
 					bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
 					// active low sync rst
 					cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
-				} else if (ff->type.in(ID($adff), ID($adffe))) {
+				} else if (ff->type.in(TW($adff), TW($adffe))) {
 					SigSpec arst = ff->getPort(TW::ARST);
 					bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
 					// active low async rst
@@ -109,7 +109,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
 					cell->setPort(rstport, State::S1);
 				}
 			}
-			if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
+			if (ff->type.in(TW($dffe), TW($sdffe), TW($adffe))) {
 				SigSpec ce = ff->getPort(TW::EN);
 				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
 				// enables are all active high
@@ -153,7 +153,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
 		}
 		if (st.ffD) {
 			SigSpec D = cell->getPort(TW::D);
-			if (st.ffD->type.in(ID($adff), ID($adffe))) {
+			if (st.ffD->type.in(TW($adff), TW($adffe))) {
 				f(D, st.ffD, ID(D_EN), ID(D_ARST_N), ID(D_BYPASS));
 			} else {
 				f(D, st.ffD, ID(D_EN), ID(D_SRST_N), ID(D_BYPASS));
@@ -195,7 +195,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
 	auto &st = pm.st_microchip_dsp_packC;
 
 	log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", pm.module, st.dsp);
-	log_debug("ffC:        %s\n", st.ffC ? st.ffC->name.unescape() : "--");
+	log_debug("ffC:        %s\n", st.ffC ? design->twines.unescaped_str(st.ffC->name) : "--");
 
 	Cell *cell = st.dsp;
 
@@ -210,12 +210,12 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstport != IdString()) {
-				if (ff->type.in(ID($sdff), ID($sdffe))) {
+				if (ff->type.in(TW($sdff), TW($sdffe))) {
 					SigSpec srst = ff->getPort(TW::SRST);
 					bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
 					// active low sync rst
 					cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
-				} else if (ff->type.in(ID($adff), ID($adffe))) {
+				} else if (ff->type.in(TW($adff), TW($adffe))) {
 					SigSpec arst = ff->getPort(TW::ARST);
 					bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
 					// active low async rst
@@ -225,7 +225,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
 					cell->setPort(rstport, State::S1);
 				}
 			}
-			if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
+			if (ff->type.in(TW($dffe), TW($sdffe), TW($adffe))) {
 				SigSpec ce = ff->getPort(TW::EN);
 				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
 				// enables are all active high
@@ -252,7 +252,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
 		if (st.ffC) {
 			SigSpec C = cell->getPort(TW::C);
 
-			if (st.ffC->type.in(ID($adff), ID($adffe))) {
+			if (st.ffC->type.in(TW($adff), TW($adffe))) {
 				f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
 			} else {
 				f(C, st.ffC, ID(C_EN), ID(C_SRST_N), ID(C_BYPASS));
diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc
index 80d3b4111..f58a6e78e 100644
--- a/techlibs/quicklogic/ql_bram_merge.cc
+++ b/techlibs/quicklogic/ql_bram_merge.cc
@@ -39,7 +39,7 @@ struct QlBramMergeWorker {
 
 	QlBramMergeWorker(RTLIL::Module* module) : module(module)
 	{
-		const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
+		const RTLIL::IdString split_cell_type = TW($__QLF_TDP36K);
 
 		for (RTLIL::Cell* cell : module->selected_cells())
 		{
@@ -124,11 +124,11 @@ struct QlBramMergeWorker {
 
 	void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
 	{
-		const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
+		const RTLIL::IdString merged_cell_type = TW($__QLF_TDP36K_MERGED);
 
 		// Create the new cell
 		RTLIL::Cell* merged = module->addCell(NEW_TWINE, merged_cell_type);
-		log_debug("Merging split BRAM cells %s and %s -> %s\n", bram1->name.unescape(), bram2->name.unescape(), merged->name.unescape());
+		log_debug("Merging split BRAM cells %s and %s -> %s\n", design->twines.unescaped_str(bram1->name), design->twines.unescaped_str(bram2->name), design->twines.unescaped_str(merged->name));
 
 		for (auto &it : param_map(false))
 		{
@@ -146,14 +146,14 @@ struct QlBramMergeWorker {
 			if (bram1->hasPort(it.first))
 				merged->setPort(it.second, bram1->getPort(it.first));
 			else
-				log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram1->name.unescape());
+				log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram1->name));
 		}
 		for (auto &it : port_map(true))
 		{
 			if (bram2->hasPort(it.first))
 				merged->setPort(it.second, bram2->getPort(it.first));
 			else
-				log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram2->name.unescape());
+				log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram2->name));
 		}
 		merged->attributes = bram1->attributes;
 		for (auto attr: bram2->attributes)
diff --git a/techlibs/quicklogic/ql_bram_types.cc b/techlibs/quicklogic/ql_bram_types.cc
index c525afcfa..780fc5c65 100644
--- a/techlibs/quicklogic/ql_bram_types.cc
+++ b/techlibs/quicklogic/ql_bram_types.cc
@@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass {
 				}
 
 				cell->type = RTLIL::escape_id(type);
-				log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
+				log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
 			}
 	}
 
diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc
index cebe9b77c..60c279ced 100644
--- a/techlibs/quicklogic/ql_dsp_macc.cc
+++ b/techlibs/quicklogic/ql_dsp_macc.cc
@@ -73,11 +73,11 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
     }
 
     type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
-    log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, type.unescape());
+    log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, design->twines.unescaped_str(type));
 
     for (auto cell : {st.mul, st.add, st.mux, st.ff})
     if (cell)
-        log("  %s (%s)\n", cell, cell->type.unescape());
+        log("  %s (%s)\n", cell, cell->type.unescaped());
 
     // Add the DSP cell
     RTLIL::Cell *cell = pm.module->addCell(NEW_TWINE, type);
@@ -169,7 +169,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
     // 3 - output post acc; 1 - output pre acc
     cell->setPort(TW::output_select_i, RTLIL::Const(st.output_registered ? 1 : 3, 3));
 
-    bool subtract = (st.add->type == ID($sub));
+    bool subtract = (st.add->type == TW($sub));
     cell->setPort(TW::subtract_i, RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
 
     // Mark the cells for removal
diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc
index 97c36dd22..4bd35da46 100644
--- a/techlibs/quicklogic/ql_dsp_simd.cc
+++ b/techlibs/quicklogic/ql_dsp_simd.cc
@@ -150,8 +150,8 @@ struct QlDspSimdPass : public Pass {
 					// Create the new cell
 					Cell *simd = module->addCell(NEW_TWINE, m_SimdDspType);
 
-					log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, dsp_a->type.unescape(),
-						dsp_b, dsp_b->type.unescape(), simd, simd->type.unescape());
+					log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, design->twines.unescaped_str(dsp_a->type),
+						dsp_b, design->twines.unescaped_str(dsp_b->type), simd, design->twines.unescaped_str(simd->type));
 
 					// Check if the target cell is known (important to know
 					// its port widths)
diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc
index 725a1c28a..92b68fc0f 100644
--- a/techlibs/xilinx/xilinx_dsp.cc
+++ b/techlibs/xilinx/xilinx_dsp.cc
@@ -115,7 +115,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
 	SigPool simds = simd_signals(module, sigmap);
 
 	for (auto cell : selected_cells) {
-		if (!cell->type.in(ID($add), ID($sub)))
+		if (!cell->type.in(TW($add), TW($sub)))
 			continue;
 		SigSpec Y = cell->getPort(TW::Y);
 		if (!is_allowed(Y, simds))
@@ -129,9 +129,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
 				continue;
 			if (GetSize(B) > 12)
 				continue;
-			if (cell->type == ID($add))
+			if (cell->type == TW($add))
 				simd12_add.push_back(cell);
-			else if (cell->type == ID($sub))
+			else if (cell->type == TW($sub))
 				simd12_sub.push_back(cell);
 		}
 		else if (GetSize(Y) <= 25) {
@@ -139,9 +139,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
 				continue;
 			if (GetSize(B) > 24)
 				continue;
-			if (cell->type == ID($add))
+			if (cell->type == TW($add))
 				simd24_add.push_back(cell);
-			else if (cell->type == ID($sub))
+			else if (cell->type == TW($sub))
 				simd24_sub.push_back(cell);
 		}
 		else
@@ -222,7 +222,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
 			cell->setPort(TW::C, C);
 			cell->setPort(TW::P, P);
 			cell->setPort(TW::CARRYOUT, CARRYOUT);
-			if (lane1->type == ID($sub))
+			if (lane1->type == TW($sub))
 				cell->setPort(TW::ALUMODE, Const::from_string("0011"));
 
 			module->remove(lane1);
@@ -286,7 +286,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
 			cell->setPort(TW::C, C);
 			cell->setPort(TW::P, P);
 			cell->setPort(TW::CARRYOUT, CARRYOUT);
-			if (lane1->type == ID($sub))
+			if (lane1->type == TW($sub))
 				cell->setPort(TW::ALUMODE, Const::from_string("0011"));
 
 			module->remove(lane1);
@@ -305,27 +305,27 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 
 	log("Analysing %s.%s for Xilinx DSP packing.\n", pm.module, st.dsp);
 
-	log_debug("preAdd:     %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
-	log_debug("preSub:     %s\n", st.preSub ? st.preSub->name.unescape() : "--");
-	log_debug("ffAD:       %s\n", st.ffAD ? st.ffAD->name.unescape() : "--");
-	log_debug("ffA2:       %s\n", st.ffA2 ? st.ffA2->name.unescape() : "--");
-	log_debug("ffA1:       %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
-	log_debug("ffB2:       %s\n", st.ffB2 ? st.ffB2->name.unescape() : "--");
-	log_debug("ffB1:       %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
-	log_debug("ffD:        %s\n", st.ffD ? st.ffD->name.unescape() : "--");
-	log_debug("dsp:        %s\n", st.dsp ? st.dsp->name.unescape() : "--");
-	log_debug("ffM:        %s\n", st.ffM ? st.ffM->name.unescape() : "--");
-	log_debug("postAdd:    %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
-	log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
-	log_debug("ffP:        %s\n", st.ffP ? st.ffP->name.unescape() : "--");
-	log_debug("overflow:   %s\n", st.overflow ? st.overflow->name.unescape() : "--");
+	log_debug("preAdd:     %s\n", st.preAdd ? design->twines.unescaped_str(st.preAdd->name) : "--");
+	log_debug("preSub:     %s\n", st.preSub ? design->twines.unescaped_str(st.preSub->name) : "--");
+	log_debug("ffAD:       %s\n", st.ffAD ? design->twines.unescaped_str(st.ffAD->name) : "--");
+	log_debug("ffA2:       %s\n", st.ffA2 ? design->twines.unescaped_str(st.ffA2->name) : "--");
+	log_debug("ffA1:       %s\n", st.ffA1 ? design->twines.unescaped_str(st.ffA1->name) : "--");
+	log_debug("ffB2:       %s\n", st.ffB2 ? design->twines.unescaped_str(st.ffB2->name) : "--");
+	log_debug("ffB1:       %s\n", st.ffB1 ? design->twines.unescaped_str(st.ffB1->name) : "--");
+	log_debug("ffD:        %s\n", st.ffD ? design->twines.unescaped_str(st.ffD->name) : "--");
+	log_debug("dsp:        %s\n", st.dsp ? design->twines.unescaped_str(st.dsp->name) : "--");
+	log_debug("ffM:        %s\n", st.ffM ? design->twines.unescaped_str(st.ffM->name) : "--");
+	log_debug("postAdd:    %s\n", st.postAdd ? design->twines.unescaped_str(st.postAdd->name) : "--");
+	log_debug("postAddMux: %s\n", st.postAddMux ? design->twines.unescaped_str(st.postAddMux->name) : "--");
+	log_debug("ffP:        %s\n", st.ffP ? design->twines.unescaped_str(st.ffP->name) : "--");
+	log_debug("overflow:   %s\n", st.overflow ? design->twines.unescaped_str(st.overflow->name) : "--");
 
 	Cell *cell = st.dsp;
 
 	if (st.preAdd || st.preSub) {
 		Cell* preAdder = st.preAdd ? st.preAdd : st.preSub;
 
-		log("  preadder %s (%s)\n", preAdder, preAdder->type.unescape());
+		log("  preadder %s (%s)\n", preAdder, design->twines.unescaped_str(preAdder->type));
 		bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool();
 		bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool();
 		if (st.sigA == preAdder->getPort(TW::B))
@@ -334,13 +334,13 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		st.sigD.extend_u0(25, D_SIGNED);
 		cell->setPort(TW::A, st.sigA);
 		cell->setPort(TW::D, st.sigD);
-		if (preAdder->type == ID($add))
+		if (preAdder->type == TW($add))
 			cell->setPort(TW::INMODE, Const::from_string("00100"));
 		else
 			cell->setPort(TW::INMODE, Const::from_string("01100"));
 
 		if (st.ffAD) {
-			if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
+			if (st.ffAD->type.in(TW($dffe), TW($sdffe))) {
 				bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
 				SigSpec S = st.ffAD->getPort(TW::EN);
 				cell->setPort(TW::CEAD, pol ? S : pm.module->Not(NEW_TWINE, S));
@@ -355,7 +355,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		pm.autoremove(preAdder);
 	}
 	if (st.postAdd) {
-		log("  postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
+		log("  postadder %s (%s)\n", st.postAdd, design->twines.unescaped_str(st.postAdd->type));
 
 		SigSpec &opmode = cell->connections_.at(ID(OPMODE));
 		if (st.postAddMux) {
@@ -381,12 +381,12 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 		pm.autoremove(st.postAdd);
 	}
 	if (st.overflow) {
-		log("  overflow %s (%s)\n", st.overflow, st.overflow->type.unescape());
+		log("  overflow %s (%s)\n", st.overflow, design->twines.unescaped_str(st.overflow->type));
 		cell->setParam(ID(USE_PATTERN_DETECT), Const("PATDET"));
 		cell->setParam(ID(SEL_PATTERN), Const("PATTERN"));
 		cell->setParam(ID(SEL_MASK), Const("MASK"));
 
-		if (st.overflow->type == ID($ge)) {
+		if (st.overflow->type == TW($ge)) {
 			Const B = st.overflow->getPort(TW::B).as_const();
 			log_assert(std::count(B.begin(), B.end(), State::S1) == 1);
 			// Since B is an exact power of 2, subtract 1
@@ -419,7 +419,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstport != IdString()) {
-				if (ff->type.in(ID($sdff), ID($sdffe))) {
+				if (ff->type.in(TW($sdff), TW($sdffe))) {
 					SigSpec srst = ff->getPort(TW::SRST);
 					bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
 					cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@@ -427,7 +427,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 					cell->setPort(rstport, State::S0);
 				}
 			}
-			if (ff->type.in(ID($dffe), ID($sdffe))) {
+			if (ff->type.in(TW($dffe), TW($sdffe))) {
 				SigSpec ce = ff->getPort(TW::EN);
 				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
 				cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
@@ -538,23 +538,23 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 
 	log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", pm.module, st.dsp);
 
-	log_debug("preAdd:     %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
-	log_debug("ffA1:       %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
-	log_debug("ffA0:       %s\n", st.ffA0 ? st.ffA0->name.unescape() : "--");
-	log_debug("ffB1:       %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
-	log_debug("ffB0:       %s\n", st.ffB0 ? st.ffB0->name.unescape() : "--");
-	log_debug("ffD:        %s\n", st.ffD ? st.ffD->name.unescape() : "--");
-	log_debug("dsp:        %s\n", st.dsp ? st.dsp->name.unescape() : "--");
-	log_debug("ffM:        %s\n", st.ffM ? st.ffM->name.unescape() : "--");
-	log_debug("postAdd:    %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
-	log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
-	log_debug("ffP:        %s\n", st.ffP ? st.ffP->name.unescape() : "--");
+	log_debug("preAdd:     %s\n", st.preAdd ? design->twines.unescaped_str(st.preAdd->name) : "--");
+	log_debug("ffA1:       %s\n", st.ffA1 ? design->twines.unescaped_str(st.ffA1->name) : "--");
+	log_debug("ffA0:       %s\n", st.ffA0 ? design->twines.unescaped_str(st.ffA0->name) : "--");
+	log_debug("ffB1:       %s\n", st.ffB1 ? design->twines.unescaped_str(st.ffB1->name) : "--");
+	log_debug("ffB0:       %s\n", st.ffB0 ? design->twines.unescaped_str(st.ffB0->name) : "--");
+	log_debug("ffD:        %s\n", st.ffD ? design->twines.unescaped_str(st.ffD->name) : "--");
+	log_debug("dsp:        %s\n", st.dsp ? design->twines.unescaped_str(st.dsp->name) : "--");
+	log_debug("ffM:        %s\n", st.ffM ? design->twines.unescaped_str(st.ffM->name) : "--");
+	log_debug("postAdd:    %s\n", st.postAdd ? design->twines.unescaped_str(st.postAdd->name) : "--");
+	log_debug("postAddMux: %s\n", st.postAddMux ? design->twines.unescaped_str(st.postAddMux->name) : "--");
+	log_debug("ffP:        %s\n", st.ffP ? design->twines.unescaped_str(st.ffP->name) : "--");
 
 	Cell *cell = st.dsp;
 	SigSpec &opmode = cell->connections_.at(ID(OPMODE));
 
 	if (st.preAdd) {
-		log("  preadder %s (%s)\n", st.preAdd, st.preAdd->type.unescape());
+		log("  preadder %s (%s)\n", st.preAdd, design->twines.unescaped_str(st.preAdd->type));
 		bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
 		bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
 		st.sigB.extend_u0(18, B_SIGNED);
@@ -562,9 +562,9 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 		cell->setPort(TW::B, st.sigB);
 		cell->setPort(TW::D, st.sigD);
 		opmode[4] = State::S1;
-		if (st.preAdd->type == ID($add))
+		if (st.preAdd->type == TW($add))
 			opmode[6] = State::S0;
-		else if (st.preAdd->type == ID($sub))
+		else if (st.preAdd->type == TW($sub))
 			opmode[6] = State::S1;
 		else
 			log_assert(!"strange pre-adder type");
@@ -572,7 +572,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 		pm.autoremove(st.preAdd);
 	}
 	if (st.postAdd) {
-		log("  postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
+		log("  postadder %s (%s)\n", st.postAdd, design->twines.unescaped_str(st.postAdd->type));
 
 		if (st.postAddMux) {
 			log_assert(st.ffP);
@@ -606,7 +606,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstport != IdString()) {
-				if (ff->type.in(ID($sdff), ID($sdffe))) {
+				if (ff->type.in(TW($sdff), TW($sdffe))) {
 					SigSpec srst = ff->getPort(TW::SRST);
 					bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
 					cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@@ -614,7 +614,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 					cell->setPort(rstport, State::S0);
 				}
 			}
-			if (ff->type.in(ID($dffe), ID($sdffe))) {
+			if (ff->type.in(TW($dffe), TW($sdffe))) {
 				SigSpec ce = ff->getPort(TW::EN);
 				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
 				cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
@@ -715,7 +715,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 	auto &st = pm.st_xilinx_dsp_packC;
 
 	log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", pm.module, st.dsp);
-	log_debug("ffC:        %s\n", st.ffC ? st.ffC->name.unescape() : "--");
+	log_debug("ffC:        %s\n", st.ffC ? design->twines.unescaped_str(st.ffC->name) : "--");
 
 	Cell *cell = st.dsp;
 
@@ -729,7 +729,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 			if (!A.empty())
 				A.replace(Q, D);
 			if (rstport != IdString()) {
-				if (ff->type.in(ID($sdff), ID($sdffe))) {
+				if (ff->type.in(TW($sdff), TW($sdffe))) {
 					SigSpec srst = ff->getPort(TW::SRST);
 					bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
 					cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@@ -737,7 +737,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 					cell->setPort(rstport, State::S0);
 				}
 			}
-			if (ff->type.in(ID($dffe), ID($sdffe))) {
+			if (ff->type.in(TW($dffe), TW($sdffe))) {
 				SigSpec ce = ff->getPort(TW::EN);
 				bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
 				cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc
index 74139784e..7fea8778c 100644
--- a/techlibs/xilinx/xilinx_srl.cc
+++ b/techlibs/xilinx/xilinx_srl.cc
@@ -30,12 +30,12 @@ void run_fixed(xilinx_srl_pm &pm)
 {
 	auto &st = pm.st_fixed;
 	auto &ud = pm.ud_fixed;
-	log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
+	log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), design->twines.unescaped_str(st.first->type));
 
 	SigSpec initval;
 	for (auto cell : ud.longest_chain) {
 		log_debug("    %s\n", cell);
-		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
+		if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_))) {
 			SigBit Q = cell->getPort(TW::Q);
 			log_assert(Q.wire);
 			auto it = Q.wire->attributes.find(ID::init);
@@ -59,15 +59,15 @@ void run_fixed(xilinx_srl_pm &pm)
 
 	auto first_cell = ud.longest_chain.back();
 	auto last_cell = ud.longest_chain.front();
-	Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
+	Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
 	pm.module->swap_names(c, first_cell);
 
-	if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
+	if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
 		c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
 		c->setParam(ID::INIT, initval.as_const());
-		if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+		if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
 			c->setParam(ID(CLKPOL), 1);
-		else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
+		else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_), ID(FDRE_1)))
 			c->setParam(ID(CLKPOL), 0);
 		else if (first_cell->type.in(ID(FDRE))) {
 			if (!first_cell->getParam(ID(IS_C_INVERTED)).as_bool())
@@ -77,9 +77,9 @@ void run_fixed(xilinx_srl_pm &pm)
 		}
 		else
 			log_abort();
-		if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
+		if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
 			c->setParam(ID(ENPOL), 1);
-		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
+		else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
 			c->setParam(ID(ENPOL), 0);
 		else
 			c->setParam(ID(ENPOL), 2);
@@ -88,9 +88,9 @@ void run_fixed(xilinx_srl_pm &pm)
 		c->setPort(TW::D, first_cell->getPort(TW::D));
 		c->setPort(TW::Q, last_cell->getPort(TW::Q));
 		c->setPort(TW::L, GetSize(ud.longest_chain)-1);
-		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+		if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
 			c->setPort(TW::E, State::S1);
-		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+		else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
 			c->setPort(TW::E, first_cell->getPort(TW::E));
 		else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
 			c->setPort(TW::E, first_cell->getPort(TW::CE));
@@ -100,7 +100,7 @@ void run_fixed(xilinx_srl_pm &pm)
 	else
 		log_abort();
 
-	log("    -> %s (%s)\n", c, c->type.unescape());
+	log("    -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
 }
 
 void run_variable(xilinx_srl_pm &pm)
@@ -108,14 +108,14 @@ void run_variable(xilinx_srl_pm &pm)
 	auto &st = pm.st_variable;
 	auto &ud = pm.ud_variable;
 
-	log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), st.first->type.unescape());
+	log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), design->twines.unescaped_str(st.first->type));
 
 	SigSpec initval;
 	for (const auto &i : ud.chain) {
 		auto cell = i.first;
 		auto slice = i.second;
 		log_debug("    %s\n", cell);
-		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
+		if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
 			SigBit Q = cell->getPort(TW::Q)[slice];
 			log_assert(Q.wire);
 			auto it = Q.wire->attributes.find(ID::init);
@@ -134,46 +134,46 @@ void run_variable(xilinx_srl_pm &pm)
 	auto first_cell = ud.chain.back().first;
 	auto first_slice = ud.chain.back().second;
 
-	Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
+	Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
 	pm.module->swap_names(c, first_cell);
 
-	if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
+	if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
 		c->setParam(ID::DEPTH, GetSize(ud.chain));
 		c->setParam(ID::INIT, initval.as_const());
 		Const clkpol, enpol;
-		if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+		if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
 			clkpol = 1;
-		else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
+		else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_)))
 			clkpol = 0;
-		else if (first_cell->type.in(ID($dff), ID($dffe)))
+		else if (first_cell->type.in(TW($dff), TW($dffe)))
 			clkpol = first_cell->getParam(ID::CLK_POLARITY);
 		else
 			log_abort();
-		if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
+		if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
 			enpol = 1;
-		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
+		else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
 			enpol = 0;
-		else if (first_cell->type.in(ID($dffe)))
+		else if (first_cell->type.in(TW($dffe)))
 			enpol = first_cell->getParam(ID::EN_POLARITY);
 		else
 			enpol = 2;
 		c->setParam(ID(CLKPOL), clkpol);
 		c->setParam(ID(ENPOL), enpol);
 
-		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+		if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
 			c->setPort(TW::C, first_cell->getPort(TW::C));
-		else if (first_cell->type.in(ID($dff), ID($dffe)))
+		else if (first_cell->type.in(TW($dff), TW($dffe)))
 			c->setPort(TW::C, first_cell->getPort(TW::CLK));
 		else
 			log_abort();
 		c->setPort(TW::D, first_cell->getPort(TW::D)[first_slice]);
 		c->setPort(TW::Q, st.shiftx->getPort(TW::Y));
 		c->setPort(TW::L, st.shiftx->getPort(TW::B));
-		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
+		if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($dff)))
 			c->setPort(TW::E, State::S1);
-		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+		else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
 			c->setPort(TW::E, first_cell->getPort(TW::E));
-		else if (first_cell->type.in(ID($dffe)))
+		else if (first_cell->type.in(TW($dffe)))
 			c->setPort(TW::E, first_cell->getPort(TW::EN));
 		else
 			log_abort();
@@ -181,7 +181,7 @@ void run_variable(xilinx_srl_pm &pm)
 	else
 		log_abort();
 
-	log("    -> %s (%s)\n", c, c->type.unescape());
+	log("    -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
 }
 
 struct XilinxSrlPass : public Pass {
diff --git a/tests/unit/kernel/cellTypesTest.cc b/tests/unit/kernel/cellTypesTest.cc
index f2c044df4..9cde0ffd3 100644
--- a/tests/unit/kernel/cellTypesTest.cc
+++ b/tests/unit/kernel/cellTypesTest.cc
@@ -16,10 +16,10 @@ TEST(CellTypesTest, basic)
 	NewCellTypes newer;
 	older.setup(nullptr);
 	newer.setup(nullptr);
-	older.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true);
-	newer.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true);
-	EXPECT_EQ(older.cell_known(ID(aaaaa)), newer.cell_known(ID(aaaaa)));
-	EXPECT_EQ(older.cell_known(ID($and)), newer.cell_known(ID($and)));
+	older.setup_type(TW(bleh), {TW::G}, {TW::H, TW::I}, false, true);
+	newer.setup_type(TW(bleh), {TW::G}, {TW::H, TW::I}, false, true);
+	EXPECT_EQ(older.cell_known(TW(aaaaa)), newer.cell_known(TW(aaaaa)));
+	EXPECT_EQ(older.cell_known(TW($and)), newer.cell_known(TW($and)));
 	auto check_port = [&](auto type, auto port) {
 		EXPECT_EQ(older.cell_port_dir(type, port), newer.cell_port_dir(type, port));
 		EXPECT_EQ(older.cell_input(type, port), newer.cell_input(type, port));
@@ -27,53 +27,54 @@ TEST(CellTypesTest, basic)
 	};
 
 	// ground truth
-	const pool<IdString> expected_ff_types = {
-		ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre),
-		ID($adff), ID($adffe), ID($aldff), ID($aldffe),
-		ID($sdff), ID($sdffe), ID($sdffce),
-		ID($dlatch), ID($adlatch), ID($dlatchsr),
-		ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
-		ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
-		ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),
-		ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
-		ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
-		ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
-		ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_),
-		ID($_DFF_N_), ID($_DFF_P_),
-		ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
-		ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
-		ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
-		ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
-		ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
-		ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_),
-		ID($_ALDFF_NN_), ID($_ALDFF_NP_), ID($_ALDFF_PN_), ID($_ALDFF_PP_),
-		ID($_ALDFFE_NNN_), ID($_ALDFFE_NNP_), ID($_ALDFFE_NPN_), ID($_ALDFFE_NPP_),
-		ID($_ALDFFE_PNN_), ID($_ALDFFE_PNP_), ID($_ALDFFE_PPN_), ID($_ALDFFE_PPP_),
-		ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
-		ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_),
-		ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
-		ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
-		ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
-		ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
-		ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
-		ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
-		ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
-		ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_),
-		ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_),
-		ID($_DLATCH_N_), ID($_DLATCH_P_),
-		ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
-		ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_),
-		ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
-		ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
-		ID($_FF_),
+	const pool<TwineRef> expected_ff_types = {
+		TW($sr), TW($ff), TW($dff), TW($dffe), TW($dffsr), TW($dffsre),
+		TW($adff), TW($adffe), TW($aldff), TW($aldffe),
+		TW($sdff), TW($sdffe), TW($sdffce),
+		TW($dlatch), TW($adlatch), TW($dlatchsr),
+		TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_),
+		TW($_DFFSR_NNN_), TW($_DFFSR_NNP_), TW($_DFFSR_NPN_), TW($_DFFSR_NPP_),
+		TW($_DFFSR_PNN_), TW($_DFFSR_PNP_), TW($_DFFSR_PPN_), TW($_DFFSR_PPP_),
+		TW($_DFFSRE_NNNN_), TW($_DFFSRE_NNNP_), TW($_DFFSRE_NNPN_), TW($_DFFSRE_NNPP_),
+		TW($_DFFSRE_NPNN_), TW($_DFFSRE_NPNP_), TW($_DFFSRE_NPPN_), TW($_DFFSRE_NPPP_),
+		TW($_DFFSRE_PNNN_), TW($_DFFSRE_PNNP_), TW($_DFFSRE_PNPN_), TW($_DFFSRE_PNPP_),
+		TW($_DFFSRE_PPNN_), TW($_DFFSRE_PPNP_), TW($_DFFSRE_PPPN_), TW($_DFFSRE_PPPP_),
+		TW($_DFF_N_), TW($_DFF_P_),
+		TW($_DFF_NN0_), TW($_DFF_NN1_), TW($_DFF_NP0_), TW($_DFF_NP1_),
+		TW($_DFF_PN0_), TW($_DFF_PN1_), TW($_DFF_PP0_), TW($_DFF_PP1_),
+		TW($_DFFE_NN0N_), TW($_DFFE_NN0P_), TW($_DFFE_NN1N_), TW($_DFFE_NN1P_),
+		TW($_DFFE_NP0N_), TW($_DFFE_NP0P_), TW($_DFFE_NP1N_), TW($_DFFE_NP1P_),
+		TW($_DFFE_PN0N_), TW($_DFFE_PN0P_), TW($_DFFE_PN1N_), TW($_DFFE_PN1P_),
+		TW($_DFFE_PP0N_), TW($_DFFE_PP0P_), TW($_DFFE_PP1N_), TW($_DFFE_PP1P_),
+		TW($_ALDFF_NN_), TW($_ALDFF_NP_), TW($_ALDFF_PN_), TW($_ALDFF_PP_),
+		TW($_ALDFFE_NNN_), TW($_ALDFFE_NNP_), TW($_ALDFFE_NPN_), TW($_ALDFFE_NPP_),
+		TW($_ALDFFE_PNN_), TW($_ALDFFE_PNP_), TW($_ALDFFE_PPN_), TW($_ALDFFE_PPP_),
+		TW($_SDFF_NN0_), TW($_SDFF_NN1_), TW($_SDFF_NP0_), TW($_SDFF_NP1_),
+		TW($_SDFF_PN0_), TW($_SDFF_PN1_), TW($_SDFF_PP0_), TW($_SDFF_PP1_),
+		TW($_SDFFE_NN0N_), TW($_SDFFE_NN0P_), TW($_SDFFE_NN1N_), TW($_SDFFE_NN1P_),
+		TW($_SDFFE_NP0N_), TW($_SDFFE_NP0P_), TW($_SDFFE_NP1N_), TW($_SDFFE_NP1P_),
+		TW($_SDFFE_PN0N_), TW($_SDFFE_PN0P_), TW($_SDFFE_PN1N_), TW($_SDFFE_PN1P_),
+		TW($_SDFFE_PP0N_), TW($_SDFFE_PP0P_), TW($_SDFFE_PP1N_), TW($_SDFFE_PP1P_),
+		TW($_SDFFCE_NN0N_), TW($_SDFFCE_NN0P_), TW($_SDFFCE_NN1N_), TW($_SDFFCE_NN1P_),
+		TW($_SDFFCE_NP0N_), TW($_SDFFCE_NP0P_), TW($_SDFFCE_NP1N_), TW($_SDFFCE_NP1P_),
+		TW($_SDFFCE_PN0N_), TW($_SDFFCE_PN0P_), TW($_SDFFCE_PN1N_), TW($_SDFFCE_PN1P_),
+		TW($_SDFFCE_PP0N_), TW($_SDFFCE_PP0P_), TW($_SDFFCE_PP1N_), TW($_SDFFCE_PP1P_),
+		TW($_SR_NN_), TW($_SR_NP_), TW($_SR_PN_), TW($_SR_PP_),
+		TW($_DLATCH_N_), TW($_DLATCH_P_),
+		TW($_DLATCH_NN0_), TW($_DLATCH_NN1_), TW($_DLATCH_NP0_), TW($_DLATCH_NP1_),
+		TW($_DLATCH_PN0_), TW($_DLATCH_PN1_), TW($_DLATCH_PP0_), TW($_DLATCH_PP1_),
+		TW($_DLATCHSR_NNN_), TW($_DLATCHSR_NNP_), TW($_DLATCHSR_NPN_), TW($_DLATCHSR_NPP_),
+		TW($_DLATCHSR_PNN_), TW($_DLATCHSR_PNP_), TW($_DLATCHSR_PPN_), TW($_DLATCHSR_PPP_),
+		TW($_FF_),
 	};
 
-	for (size_t i = 0; i < static_cast<size_t>(RTLIL::StaticId::STATIC_ID_END); i++) {
-		IdString type;
-		type.index_ = i;
+	TwinePool empty_pool;
+	for (size_t i = 0; i < static_cast<size_t>(STATIC_TWINE_END); i++) {
+		TwineRef type;
+		type = i;
 		EXPECT_EQ(older.cell_known(type), newer.cell_known(type));
 		if (older.cell_evaluable(type) != newer.cell_evaluable(type))
-			std::cout << type.str() << "\n";
+			std::cout << empty_pool.unescaped_str(type) << "\n";
 		EXPECT_EQ(older.cell_evaluable(type), newer.cell_evaluable(type));
 		for (auto port : StaticCellTypes::builder.cells.data()->inputs.ports)
 			check_port(type, port);