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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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98
techlibs/xilinx/xilinx_dsp.cc
View file

@ -115,7 +115,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
SigPool simds = simd_signals(module, sigmap);
for (auto cell : selected_cells) {
if (!cell->type.in(ID($add), ID($sub)))
if (!cell->type.in(TW($add), TW($sub)))
continue;
SigSpec Y = cell->getPort(TW::Y);
if (!is_allowed(Y, simds))
@ -129,9 +129,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
continue;
if (GetSize(B) > 12)
continue;
if (cell->type == ID($add))
if (cell->type == TW($add))
simd12_add.push_back(cell);
else if (cell->type == ID($sub))
else if (cell->type == TW($sub))
simd12_sub.push_back(cell);
}
else if (GetSize(Y) <= 25) {
@ -139,9 +139,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
continue;
if (GetSize(B) > 24)
continue;
if (cell->type == ID($add))
if (cell->type == TW($add))
simd24_add.push_back(cell);
else if (cell->type == ID($sub))
else if (cell->type == TW($sub))
simd24_sub.push_back(cell);
}
else
@ -222,7 +222,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(TW::CARRYOUT, CARRYOUT);
if (lane1->type == ID($sub))
if (lane1->type == TW($sub))
cell->setPort(TW::ALUMODE, Const::from_string("0011"));
module->remove(lane1);
@ -286,7 +286,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(TW::CARRYOUT, CARRYOUT);
if (lane1->type == ID($sub))
if (lane1->type == TW($sub))
cell->setPort(TW::ALUMODE, Const::from_string("0011"));
module->remove(lane1);
@ -305,27 +305,27 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
log("Analysing %s.%s for Xilinx DSP packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
log_debug("preSub: %s\n", st.preSub ? st.preSub->name.unescape() : "--");
log_debug("ffAD: %s\n", st.ffAD ? st.ffAD->name.unescape() : "--");
log_debug("ffA2: %s\n", st.ffA2 ? st.ffA2->name.unescape() : "--");
log_debug("ffA1: %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
log_debug("ffB2: %s\n", st.ffB2 ? st.ffB2->name.unescape() : "--");
log_debug("ffB1: %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
log_debug("ffD: %s\n", st.ffD ? st.ffD->name.unescape() : "--");
log_debug("dsp: %s\n", st.dsp ? st.dsp->name.unescape() : "--");
log_debug("ffM: %s\n", st.ffM ? st.ffM->name.unescape() : "--");
log_debug("postAdd: %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
log_debug("ffP: %s\n", st.ffP ? st.ffP->name.unescape() : "--");
log_debug("overflow: %s\n", st.overflow ? st.overflow->name.unescape() : "--");
log_debug("preAdd: %s\n", st.preAdd ? design->twines.unescaped_str(st.preAdd->name) : "--");
log_debug("preSub: %s\n", st.preSub ? design->twines.unescaped_str(st.preSub->name) : "--");
log_debug("ffAD: %s\n", st.ffAD ? design->twines.unescaped_str(st.ffAD->name) : "--");
log_debug("ffA2: %s\n", st.ffA2 ? design->twines.unescaped_str(st.ffA2->name) : "--");
log_debug("ffA1: %s\n", st.ffA1 ? design->twines.unescaped_str(st.ffA1->name) : "--");
log_debug("ffB2: %s\n", st.ffB2 ? design->twines.unescaped_str(st.ffB2->name) : "--");
log_debug("ffB1: %s\n", st.ffB1 ? design->twines.unescaped_str(st.ffB1->name) : "--");
log_debug("ffD: %s\n", st.ffD ? design->twines.unescaped_str(st.ffD->name) : "--");
log_debug("dsp: %s\n", st.dsp ? design->twines.unescaped_str(st.dsp->name) : "--");
log_debug("ffM: %s\n", st.ffM ? design->twines.unescaped_str(st.ffM->name) : "--");
log_debug("postAdd: %s\n", st.postAdd ? design->twines.unescaped_str(st.postAdd->name) : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? design->twines.unescaped_str(st.postAddMux->name) : "--");
log_debug("ffP: %s\n", st.ffP ? design->twines.unescaped_str(st.ffP->name) : "--");
log_debug("overflow: %s\n", st.overflow ? design->twines.unescaped_str(st.overflow->name) : "--");
Cell *cell = st.dsp;
if (st.preAdd || st.preSub) {
Cell* preAdder = st.preAdd ? st.preAdd : st.preSub;
log(" preadder %s (%s)\n", preAdder, preAdder->type.unescape());
log(" preadder %s (%s)\n", preAdder, design->twines.unescaped_str(preAdder->type));
bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool();
bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool();
if (st.sigA == preAdder->getPort(TW::B))
@ -334,13 +334,13 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
st.sigD.extend_u0(25, D_SIGNED);
cell->setPort(TW::A, st.sigA);
cell->setPort(TW::D, st.sigD);
if (preAdder->type == ID($add))
if (preAdder->type == TW($add))
cell->setPort(TW::INMODE, Const::from_string("00100"));
else
cell->setPort(TW::INMODE, Const::from_string("01100"));
if (st.ffAD) {
if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
if (st.ffAD->type.in(TW($dffe), TW($sdffe))) {
bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
SigSpec S = st.ffAD->getPort(TW::EN);
cell->setPort(TW::CEAD, pol ? S : pm.module->Not(NEW_TWINE, S));
@ -355,7 +355,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(preAdder);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
log(" postadder %s (%s)\n", st.postAdd, design->twines.unescaped_str(st.postAdd->type));
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) {
@ -381,12 +381,12 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(st.postAdd);
}
if (st.overflow) {
log(" overflow %s (%s)\n", st.overflow, st.overflow->type.unescape());
log(" overflow %s (%s)\n", st.overflow, design->twines.unescaped_str(st.overflow->type));
cell->setParam(ID(USE_PATTERN_DETECT), Const("PATDET"));
cell->setParam(ID(SEL_PATTERN), Const("PATTERN"));
cell->setParam(ID(SEL_MASK), Const("MASK"));
if (st.overflow->type == ID($ge)) {
if (st.overflow->type == TW($ge)) {
Const B = st.overflow->getPort(TW::B).as_const();
log_assert(std::count(B.begin(), B.end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1
@ -419,7 +419,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@ -427,7 +427,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setPort(rstport, State::S0);
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
if (ff->type.in(TW($dffe), TW($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
@ -538,23 +538,23 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
log_debug("ffA1: %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
log_debug("ffA0: %s\n", st.ffA0 ? st.ffA0->name.unescape() : "--");
log_debug("ffB1: %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
log_debug("ffB0: %s\n", st.ffB0 ? st.ffB0->name.unescape() : "--");
log_debug("ffD: %s\n", st.ffD ? st.ffD->name.unescape() : "--");
log_debug("dsp: %s\n", st.dsp ? st.dsp->name.unescape() : "--");
log_debug("ffM: %s\n", st.ffM ? st.ffM->name.unescape() : "--");
log_debug("postAdd: %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
log_debug("ffP: %s\n", st.ffP ? st.ffP->name.unescape() : "--");
log_debug("preAdd: %s\n", st.preAdd ? design->twines.unescaped_str(st.preAdd->name) : "--");
log_debug("ffA1: %s\n", st.ffA1 ? design->twines.unescaped_str(st.ffA1->name) : "--");
log_debug("ffA0: %s\n", st.ffA0 ? design->twines.unescaped_str(st.ffA0->name) : "--");
log_debug("ffB1: %s\n", st.ffB1 ? design->twines.unescaped_str(st.ffB1->name) : "--");
log_debug("ffB0: %s\n", st.ffB0 ? design->twines.unescaped_str(st.ffB0->name) : "--");
log_debug("ffD: %s\n", st.ffD ? design->twines.unescaped_str(st.ffD->name) : "--");
log_debug("dsp: %s\n", st.dsp ? design->twines.unescaped_str(st.dsp->name) : "--");
log_debug("ffM: %s\n", st.ffM ? design->twines.unescaped_str(st.ffM->name) : "--");
log_debug("postAdd: %s\n", st.postAdd ? design->twines.unescaped_str(st.postAdd->name) : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? design->twines.unescaped_str(st.postAddMux->name) : "--");
log_debug("ffP: %s\n", st.ffP ? design->twines.unescaped_str(st.ffP->name) : "--");
Cell *cell = st.dsp;
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.preAdd) {
log(" preadder %s (%s)\n", st.preAdd, st.preAdd->type.unescape());
log(" preadder %s (%s)\n", st.preAdd, design->twines.unescaped_str(st.preAdd->type));
bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -562,9 +562,9 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setPort(TW::B, st.sigB);
cell->setPort(TW::D, st.sigD);
opmode[4] = State::S1;
if (st.preAdd->type == ID($add))
if (st.preAdd->type == TW($add))
opmode[6] = State::S0;
else if (st.preAdd->type == ID($sub))
else if (st.preAdd->type == TW($sub))
opmode[6] = State::S1;
else
log_assert(!"strange pre-adder type");
@ -572,7 +572,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
pm.autoremove(st.preAdd);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
log(" postadder %s (%s)\n", st.postAdd, design->twines.unescaped_str(st.postAdd->type));
if (st.postAddMux) {
log_assert(st.ffP);
@ -606,7 +606,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@ -614,7 +614,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setPort(rstport, State::S0);
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
if (ff->type.in(TW($dffe), TW($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
@ -715,7 +715,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
auto &st = pm.st_xilinx_dsp_packC;
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", st.ffC ? st.ffC->name.unescape() : "--");
log_debug("ffC: %s\n", st.ffC ? design->twines.unescaped_str(st.ffC->name) : "--");
Cell *cell = st.dsp;
@ -729,7 +729,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@ -737,7 +737,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
cell->setPort(rstport, State::S0);
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
if (ff->type.in(TW($dffe), TW($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));

54
techlibs/xilinx/xilinx_srl.cc
View file

@ -30,12 +30,12 @@ void run_fixed(xilinx_srl_pm &pm)
{
auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed;
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), design->twines.unescaped_str(st.first->type));
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_))) {
SigBit Q = cell->getPort(TW::Q);
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
@ -59,15 +59,15 @@ void run_fixed(xilinx_srl_pm &pm)
auto first_cell = ud.longest_chain.back();
auto last_cell = ud.longest_chain.front();
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
c->setParam(ID::INIT, initval.as_const());
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setParam(ID(CLKPOL), 1);
else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_), ID(FDRE_1)))
c->setParam(ID(CLKPOL), 0);
else if (first_cell->type.in(ID(FDRE))) {
if (!first_cell->getParam(ID(IS_C_INVERTED)).as_bool())
@ -77,9 +77,9 @@ void run_fixed(xilinx_srl_pm &pm)
}
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
c->setParam(ID(ENPOL), 1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
c->setParam(ID(ENPOL), 0);
else
c->setParam(ID(ENPOL), 2);
@ -88,9 +88,9 @@ void run_fixed(xilinx_srl_pm &pm)
c->setPort(TW::D, first_cell->getPort(TW::D));
c->setPort(TW::Q, last_cell->getPort(TW::Q));
c->setPort(TW::L, GetSize(ud.longest_chain)-1);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
c->setPort(TW::E, first_cell->getPort(TW::CE));
@ -100,7 +100,7 @@ void run_fixed(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, c->type.unescape());
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
}
void run_variable(xilinx_srl_pm &pm)
@ -108,14 +108,14 @@ void run_variable(xilinx_srl_pm &pm)
auto &st = pm.st_variable;
auto &ud = pm.ud_variable;
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), st.first->type.unescape());
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), design->twines.unescaped_str(st.first->type));
SigSpec initval;
for (const auto &i : ud.chain) {
auto cell = i.first;
auto slice = i.second;
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
SigBit Q = cell->getPort(TW::Q)[slice];
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
@ -134,46 +134,46 @@ void run_variable(xilinx_srl_pm &pm)
auto first_cell = ud.chain.back().first;
auto first_slice = ud.chain.back().second;
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
c->setParam(ID::DEPTH, GetSize(ud.chain));
c->setParam(ID::INIT, initval.as_const());
Const clkpol, enpol;
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
clkpol = 1;
else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_)))
clkpol = 0;
else if (first_cell->type.in(ID($dff), ID($dffe)))
else if (first_cell->type.in(TW($dff), TW($dffe)))
clkpol = first_cell->getParam(ID::CLK_POLARITY);
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
enpol = 1;
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
enpol = 0;
else if (first_cell->type.in(ID($dffe)))
else if (first_cell->type.in(TW($dffe)))
enpol = first_cell->getParam(ID::EN_POLARITY);
else
enpol = 2;
c->setParam(ID(CLKPOL), clkpol);
c->setParam(ID(ENPOL), enpol);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::C, first_cell->getPort(TW::C));
else if (first_cell->type.in(ID($dff), ID($dffe)))
else if (first_cell->type.in(TW($dff), TW($dffe)))
c->setPort(TW::C, first_cell->getPort(TW::CLK));
else
log_abort();
c->setPort(TW::D, first_cell->getPort(TW::D)[first_slice]);
c->setPort(TW::Q, st.shiftx->getPort(TW::Y));
c->setPort(TW::L, st.shiftx->getPort(TW::B));
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($dff)))
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID($dffe)))
else if (first_cell->type.in(TW($dffe)))
c->setPort(TW::E, first_cell->getPort(TW::EN));
else
log_abort();
@ -181,7 +181,7 @@ void run_variable(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, c->type.unescape());
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
}
struct XilinxSrlPass : public Pass {