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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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4
techlibs/quicklogic/ql_dsp_simd.cc
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@ -150,8 +150,8 @@ struct QlDspSimdPass : public Pass {
// Create the new cell
Cell *simd = module->addCell(NEW_TWINE, m_SimdDspType);
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, dsp_a->type.unescape(),
dsp_b, dsp_b->type.unescape(), simd, simd->type.unescape());
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, design->twines.unescaped_str(dsp_a->type),
dsp_b, design->twines.unescaped_str(dsp_b->type), simd, design->twines.unescaped_str(simd->type));
// Check if the target cell is known (important to know
// its port widths)