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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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10
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -39,7 +39,7 @@ struct QlBramMergeWorker {
QlBramMergeWorker(RTLIL::Module* module) : module(module)
{
const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
const RTLIL::IdString split_cell_type = TW($__QLF_TDP36K);
for (RTLIL::Cell* cell : module->selected_cells())
{
@ -124,11 +124,11 @@ struct QlBramMergeWorker {
void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
{
const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
const RTLIL::IdString merged_cell_type = TW($__QLF_TDP36K_MERGED);
// Create the new cell
RTLIL::Cell* merged = module->addCell(NEW_TWINE, merged_cell_type);
log_debug("Merging split BRAM cells %s and %s -> %s\n", bram1->name.unescape(), bram2->name.unescape(), merged->name.unescape());
log_debug("Merging split BRAM cells %s and %s -> %s\n", design->twines.unescaped_str(bram1->name), design->twines.unescaped_str(bram2->name), design->twines.unescaped_str(merged->name));
for (auto &it : param_map(false))
{
@ -146,14 +146,14 @@ struct QlBramMergeWorker {
if (bram1->hasPort(it.first))
merged->setPort(it.second, bram1->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram1->name.unescape());
log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram1->name));
}
for (auto &it : port_map(true))
{
if (bram2->hasPort(it.first))
merged->setPort(it.second, bram2->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram2->name.unescape());
log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram2->name));
}
merged->attributes = bram1->attributes;
for (auto attr: bram2->attributes)

2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass {
}
cell->type = RTLIL::escape_id(type);
log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
}
}

6
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -73,11 +73,11 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
}
type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, type.unescape());
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, design->twines.unescaped_str(type));
for (auto cell : {st.mul, st.add, st.mux, st.ff})
if (cell)
log(" %s (%s)\n", cell, cell->type.unescape());
log(" %s (%s)\n", cell, cell->type.unescaped());
// Add the DSP cell
RTLIL::Cell *cell = pm.module->addCell(NEW_TWINE, type);
@ -169,7 +169,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// 3 - output post acc; 1 - output pre acc
cell->setPort(TW::output_select_i, RTLIL::Const(st.output_registered ? 1 : 3, 3));
bool subtract = (st.add->type == ID($sub));
bool subtract = (st.add->type == TW($sub));
cell->setPort(TW::subtract_i, RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
// Mark the cells for removal

4
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -150,8 +150,8 @@ struct QlDspSimdPass : public Pass {
// Create the new cell
Cell *simd = module->addCell(NEW_TWINE, m_SimdDspType);
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, dsp_a->type.unescape(),
dsp_b, dsp_b->type.unescape(), simd, simd->type.unescape());
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, design->twines.unescaped_str(dsp_a->type),
dsp_b, design->twines.unescaped_str(dsp_b->type), simd, design->twines.unescaped_str(simd->type));
// Check if the target cell is known (important to know
// its port widths)