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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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30
techlibs/ice40/ice40_dsp.cc
View file

@ -31,15 +31,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
log_debug("ffA: %s\n", st.ffA ? st.ffA->name.unescape() : "--");
log_debug("ffB: %s\n", st.ffB ? st.ffB->name.unescape() : "--");
log_debug("ffCD: %s\n", st.ffCD ? st.ffCD->name.unescape() : "--");
log_debug("mul: %s\n", st.mul ? st.mul->name.unescape() : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? st.ffFJKG->name.unescape() : "--");
log_debug("ffH: %s\n", st.ffH ? st.ffH->name.unescape() : "--");
log_debug("add: %s\n", st.add ? st.add->name.unescape() : "--");
log_debug("mux: %s\n", st.mux ? st.mux->name.unescape() : "--");
log_debug("ffO: %s\n", st.ffO ? st.ffO->name.unescape() : "--");
log_debug("ffA: %s\n", st.ffA ? design->twines.unescaped_str(st.ffA->name) : "--");
log_debug("ffB: %s\n", st.ffB ? design->twines.unescaped_str(st.ffB->name) : "--");
log_debug("ffCD: %s\n", st.ffCD ? design->twines.unescaped_str(st.ffCD->name) : "--");
log_debug("mul: %s\n", st.mul ? design->twines.unescaped_str(st.mul->name) : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? design->twines.unescaped_str(st.ffFJKG->name) : "--");
log_debug("ffH: %s\n", st.ffH ? design->twines.unescaped_str(st.ffH->name) : "--");
log_debug("add: %s\n", st.add ? design->twines.unescaped_str(st.add->name) : "--");
log_debug("mux: %s\n", st.mux ? design->twines.unescaped_str(st.mux->name) : "--");
log_debug("ffO: %s\n", st.ffO ? design->twines.unescaped_str(st.ffO->name) : "--");
log_debug("\n");
if (GetSize(st.sigA) > 16) {
@ -63,8 +63,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
}
Cell *cell = st.mul;
if (cell->type == ID($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape());
if (cell->type == TW($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", design->twines.unescaped_str(st.mul->type));
cell = pm.module->addCell(NEW_TWINE, ID(SB_MAC16));
pm.module->swap_names(cell, st.mul);
@ -196,11 +196,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.add) {
accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
if (accum)
log(" accumulator %s (%s)\n", st.add, st.add->type.unescape());
log(" accumulator %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
else
log(" adder %s (%s)\n", st.add, st.add->type.unescape());
cell->setPort(TW::ADDSUBTOP, st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(TW::ADDSUBBOT, st.add->type == ID($add) ? State::S0 : State::S1);
log(" adder %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
cell->setPort(TW::ADDSUBTOP, st.add->type == TW($add) ? State::S0 : State::S1);
cell->setPort(TW::ADDSUBBOT, st.add->type == TW($add) ? State::S0 : State::S1);
} else {
cell->setPort(TW::ADDSUBTOP, State::S0);
cell->setPort(TW::ADDSUBBOT, State::S0);

8
techlibs/ice40/ice40_opt.cc
View file

@ -41,7 +41,7 @@ static void run_ice40_opts(Module *module)
for (auto cell : module->selected_cells())
{
if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), ID($__ICE40_CARRY_WRAPPER)))
if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), TW($__ICE40_CARRY_WRAPPER)))
continue;
if (cell->has_keep_attr())
continue;
@ -89,7 +89,7 @@ static void run_ice40_opts(Module *module)
continue;
}
if (cell->type == ID($__ICE40_CARRY_WRAPPER))
if (cell->type == TW($__ICE40_CARRY_WRAPPER))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
@ -138,7 +138,7 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
cell->type = TW($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) });
cell->setPort(TW::Y, cell->getPort(TW::O));
@ -177,7 +177,7 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
cell->type = ID($lut);
cell->type = TW($lut);
cell->setParam(ID::WIDTH, 4);
cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
cell->unsetParam(ID(LUT_INIT));

10
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -31,13 +31,13 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
#if 0
log("\n");
log("carry: %s\n", st.carry ? st.carry->name.unescape() : "--");
log("lut: %s\n", st.lut ? st.lut->name.unescape() : "--");
log("carry: %s\n", st.carry ? design->twines.unescaped_str(st.carry->name) : "--");
log("lut: %s\n", st.lut ? design->twines.unescaped_str(st.lut->name) : "--");
#endif
log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
Cell *cell = pm.module->addCell(NEW_TWINE, ID($__ICE40_CARRY_WRAPPER));
Cell *cell = pm.module->addCell(NEW_TWINE, TW($__ICE40_CARRY_WRAPPER));
pm.module->swap_names(cell, st.carry);
cell->setPort(TW::A, st.carry->getPort(TW::I0));
@ -131,7 +131,7 @@ struct Ice40WrapCarryPass : public Pass {
ice40_wrapcarry_pm(module, &sigmap, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
} else {
for (auto cell : module->selected_cells()) {
if (cell->type != ID($__ICE40_CARRY_WRAPPER))
if (cell->type != TW($__ICE40_CARRY_WRAPPER))
continue;
auto carry = module->addCell(NEW_TWINE, ID(SB_CARRY));
@ -141,7 +141,7 @@ struct Ice40WrapCarryPass : public Pass {
carry->setPort(TW::CO, cell->getPort(TW::CO));
module->swap_names(carry, cell);
auto lut_name = cell->attributes.at(IdString{"\\SB_LUT4.name"}, Const(NEW_ID.str())).decode_string();
auto lut = module->addCell(lut_name, ID($lut));
auto lut = module->addCell(lut_name, TW($lut));
lut->setParam(ID::WIDTH, 4);
lut->setParam(ID::LUT, cell->getParam(ID::LUT));
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));