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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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4
techlibs/anlogic/anlogic_fixcarry.cc
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@ -69,7 +69,7 @@ static void fix_carry_chain(Module *module)
continue;
adders_to_fix_cells.push_back(cell);
log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescape(), cell);
log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescaped(), cell);
}
}
@ -78,7 +78,7 @@ static void fix_carry_chain(Module *module)
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescaped(), cell);
Cell *c = module->addCell(NEW_TWINE, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_TWINE);
SigBit dummy_bit = module->addWire(NEW_TWINE);