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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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4
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -69,7 +69,7 @@ static void fix_carry_chain(Module *module)
continue;
adders_to_fix_cells.push_back(cell);
log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescape(), cell);
log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescaped(), cell);
}
}
@ -78,7 +78,7 @@ static void fix_carry_chain(Module *module)
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescaped(), cell);
Cell *c = module->addCell(NEW_TWINE, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_TWINE);
SigBit dummy_bit = module->addWire(NEW_TWINE);

2
techlibs/common/opensta.cc
View file

@ -98,7 +98,7 @@ struct OpenstaPass : public Pass
f_script << "read_verilog " << verilog_filename << "\n";
f_script << "read_lib " << liberty_filename << "\n";
f_script << "link_design " << top_mod->name.unescape() << "\n";
f_script << "link_design " << design->twines.unescaped_str(top_mod->name) << "\n";
f_script << "read_sdc " << sdc_filename << "\n";
f_script << "write_sdc " << sdc_expanded_filename << "\n";
f_script.close();

4
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -47,7 +47,7 @@ struct Coolrunner2SopPass : public Pass {
dict<SigBit, tuple<SigBit, Cell*>> not_cells;
for (auto cell : module->selected_cells())
{
if (cell->type == ID($_NOT_))
if (cell->type == TW($_NOT_))
{
auto not_input = sigmap(cell->getPort(TW::A)[0]);
auto not_output = sigmap(cell->getPort(TW::Y)[0]);
@ -85,7 +85,7 @@ struct Coolrunner2SopPass : public Pass {
// Process $sop cells
for (auto cell : module->selected_cells())
{
if (cell->type == ID($sop))
if (cell->type == TW($sop))
{
// Read the inputs/outputs/parameters of the $sop cell
auto sop_inputs = sigmap(cell->getPort(TW::A));

4
techlibs/efinix/efinix_fixcarry.cc
View file

@ -65,7 +65,7 @@ static void fix_carry_chain(Module *module)
continue;
adders_to_fix_cells.push_back(cell);
log("Found %s cell named %s with invalid CI signal.\n", cell->type.unescape(), cell);
log("Found %s cell named %s with invalid CI signal.\n", cell->type.unescaped(), cell);
}
}
@ -74,7 +74,7 @@ static void fix_carry_chain(Module *module)
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescaped(), cell);
Cell *c = module->addCell(NEW_TWINE, ID(EFX_ADD));
SigBit new_bit = module->addWire(NEW_TWINE);
c->setParam(ID(I0_POLARITY), State::S1);

2
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -68,7 +68,7 @@ struct FoldInvWorker {
void find_inverted_bits()
{
for (auto cell : module->selected_cells()) {
if (cell->type != ID($__CC_NOT))
if (cell->type != TW($__CC_NOT))
continue;
SigBit a = sigmap(cell->getPort(TW::A)[0]);
SigBit y = sigmap(cell->getPort(TW::Y)[0]);

2
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -86,7 +86,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
cell->module, cell, cell_type.c_str()+1, cell->type.unescape());
cell->module, cell, cell_type.c_str()+1, cell->type.unescaped());
}
struct Greenpak4DffInvPass : public Pass {

30
techlibs/ice40/ice40_dsp.cc
View file

@ -31,15 +31,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
log_debug("ffA: %s\n", st.ffA ? st.ffA->name.unescape() : "--");
log_debug("ffB: %s\n", st.ffB ? st.ffB->name.unescape() : "--");
log_debug("ffCD: %s\n", st.ffCD ? st.ffCD->name.unescape() : "--");
log_debug("mul: %s\n", st.mul ? st.mul->name.unescape() : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? st.ffFJKG->name.unescape() : "--");
log_debug("ffH: %s\n", st.ffH ? st.ffH->name.unescape() : "--");
log_debug("add: %s\n", st.add ? st.add->name.unescape() : "--");
log_debug("mux: %s\n", st.mux ? st.mux->name.unescape() : "--");
log_debug("ffO: %s\n", st.ffO ? st.ffO->name.unescape() : "--");
log_debug("ffA: %s\n", st.ffA ? design->twines.unescaped_str(st.ffA->name) : "--");
log_debug("ffB: %s\n", st.ffB ? design->twines.unescaped_str(st.ffB->name) : "--");
log_debug("ffCD: %s\n", st.ffCD ? design->twines.unescaped_str(st.ffCD->name) : "--");
log_debug("mul: %s\n", st.mul ? design->twines.unescaped_str(st.mul->name) : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? design->twines.unescaped_str(st.ffFJKG->name) : "--");
log_debug("ffH: %s\n", st.ffH ? design->twines.unescaped_str(st.ffH->name) : "--");
log_debug("add: %s\n", st.add ? design->twines.unescaped_str(st.add->name) : "--");
log_debug("mux: %s\n", st.mux ? design->twines.unescaped_str(st.mux->name) : "--");
log_debug("ffO: %s\n", st.ffO ? design->twines.unescaped_str(st.ffO->name) : "--");
log_debug("\n");
if (GetSize(st.sigA) > 16) {
@ -63,8 +63,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
}
Cell *cell = st.mul;
if (cell->type == ID($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape());
if (cell->type == TW($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", design->twines.unescaped_str(st.mul->type));
cell = pm.module->addCell(NEW_TWINE, ID(SB_MAC16));
pm.module->swap_names(cell, st.mul);
@ -196,11 +196,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.add) {
accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
if (accum)
log(" accumulator %s (%s)\n", st.add, st.add->type.unescape());
log(" accumulator %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
else
log(" adder %s (%s)\n", st.add, st.add->type.unescape());
cell->setPort(TW::ADDSUBTOP, st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(TW::ADDSUBBOT, st.add->type == ID($add) ? State::S0 : State::S1);
log(" adder %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
cell->setPort(TW::ADDSUBTOP, st.add->type == TW($add) ? State::S0 : State::S1);
cell->setPort(TW::ADDSUBBOT, st.add->type == TW($add) ? State::S0 : State::S1);
} else {
cell->setPort(TW::ADDSUBTOP, State::S0);
cell->setPort(TW::ADDSUBBOT, State::S0);

8
techlibs/ice40/ice40_opt.cc
View file

@ -41,7 +41,7 @@ static void run_ice40_opts(Module *module)
for (auto cell : module->selected_cells())
{
if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), ID($__ICE40_CARRY_WRAPPER)))
if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), TW($__ICE40_CARRY_WRAPPER)))
continue;
if (cell->has_keep_attr())
continue;
@ -89,7 +89,7 @@ static void run_ice40_opts(Module *module)
continue;
}
if (cell->type == ID($__ICE40_CARRY_WRAPPER))
if (cell->type == TW($__ICE40_CARRY_WRAPPER))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
@ -138,7 +138,7 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
cell->type = TW($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) });
cell->setPort(TW::Y, cell->getPort(TW::O));
@ -177,7 +177,7 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
cell->type = ID($lut);
cell->type = TW($lut);
cell->setParam(ID::WIDTH, 4);
cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
cell->unsetParam(ID(LUT_INIT));

10
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -31,13 +31,13 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
#if 0
log("\n");
log("carry: %s\n", st.carry ? st.carry->name.unescape() : "--");
log("lut: %s\n", st.lut ? st.lut->name.unescape() : "--");
log("carry: %s\n", st.carry ? design->twines.unescaped_str(st.carry->name) : "--");
log("lut: %s\n", st.lut ? design->twines.unescaped_str(st.lut->name) : "--");
#endif
log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
Cell *cell = pm.module->addCell(NEW_TWINE, ID($__ICE40_CARRY_WRAPPER));
Cell *cell = pm.module->addCell(NEW_TWINE, TW($__ICE40_CARRY_WRAPPER));
pm.module->swap_names(cell, st.carry);
cell->setPort(TW::A, st.carry->getPort(TW::I0));
@ -131,7 +131,7 @@ struct Ice40WrapCarryPass : public Pass {
ice40_wrapcarry_pm(module, &sigmap, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
} else {
for (auto cell : module->selected_cells()) {
if (cell->type != ID($__ICE40_CARRY_WRAPPER))
if (cell->type != TW($__ICE40_CARRY_WRAPPER))
continue;
auto carry = module->addCell(NEW_TWINE, ID(SB_CARRY));
@ -141,7 +141,7 @@ struct Ice40WrapCarryPass : public Pass {
carry->setPort(TW::CO, cell->getPort(TW::CO));
module->swap_names(carry, cell);
auto lut_name = cell->attributes.at(IdString{"\\SB_LUT4.name"}, Const(NEW_ID.str())).decode_string();
auto lut = module->addCell(lut_name, ID($lut));
auto lut = module->addCell(lut_name, TW($lut));
lut->setParam(ID::WIDTH, 4);
lut->setParam(ID::LUT, cell->getParam(ID::LUT));
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));

2
techlibs/lattice/lattice_gsr.cc
View file

@ -100,7 +100,7 @@ struct LatticeGsrPass : public Pass {
log_debug("GSR net in module %s is %s.\n", module, log_signal(gsr));
for (auto cell : module->selected_cells())
{
if (cell->type != ID($_NOT_))
if (cell->type != TW($_NOT_))
continue;
SigSpec sig_a = cell->getPort(TW::A), sig_y = cell->getPort(TW::Y);
if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)

30
techlibs/microchip/microchip_dsp.cc
View file

@ -37,7 +37,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
// pack pre-adder
if (st.preAdderStatic) {
SigSpec &pasub = cell->connections_.at(ID(PASUB));
log(" static PASUB preadder %s (%s)\n", st.preAdderStatic, st.preAdderStatic->type.unescape());
log(" static PASUB preadder %s (%s)\n", st.preAdderStatic, design->twines.unescaped_str(st.preAdderStatic->type));
bool D_SIGNED = st.preAdderStatic->getParam(ID::B_SIGNED).as_bool();
bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -49,9 +49,9 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
cell->setPort(TW::D, st.sigD);
// MACC_PA supports both addition and subtraction with the pre-adder.
// Affects the sign of the 'D' port.
if (st.preAdderStatic->type == ID($add))
if (st.preAdderStatic->type == TW($add))
pasub[0] = State::S0;
else if (st.preAdderStatic->type == ID($sub))
else if (st.preAdderStatic->type == TW($sub))
pasub[0] = State::S1;
else
log_assert(!"strange pre-adder type");
@ -60,13 +60,13 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
// pack post-adder
if (st.postAdderStatic) {
log(" postadder %s (%s)\n", st.postAdderStatic, st.postAdderStatic->type.unescape());
log(" postadder %s (%s)\n", st.postAdderStatic, design->twines.unescaped_str(st.postAdderStatic->type));
SigSpec &sub = cell->connections_.at(ID(SUB));
// Post-adder in MACC_PA also supports subtraction
// Determines the sign of the output from the multiplier.
if (st.postAdderStatic->type == ID($add))
if (st.postAdderStatic->type == TW($add))
sub[0] = State::S0;
else if (st.postAdderStatic->type == ID($sub))
else if (st.postAdderStatic->type == TW($sub))
sub[0] = State::S1;
else
log_assert(!"strange post-adder type");
@ -94,12 +94,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
} else if (ff->type.in(TW($adff), TW($adffe))) {
SigSpec arst = ff->getPort(TW::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
@ -109,7 +109,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
cell->setPort(rstport, State::S1);
}
}
if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
if (ff->type.in(TW($dffe), TW($sdffe), TW($adffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
@ -153,7 +153,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
if (st.ffD) {
SigSpec D = cell->getPort(TW::D);
if (st.ffD->type.in(ID($adff), ID($adffe))) {
if (st.ffD->type.in(TW($adff), TW($adffe))) {
f(D, st.ffD, ID(D_EN), ID(D_ARST_N), ID(D_BYPASS));
} else {
f(D, st.ffD, ID(D_EN), ID(D_SRST_N), ID(D_BYPASS));
@ -195,7 +195,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
auto &st = pm.st_microchip_dsp_packC;
log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", st.ffC ? st.ffC->name.unescape() : "--");
log_debug("ffC: %s\n", st.ffC ? design->twines.unescaped_str(st.ffC->name) : "--");
Cell *cell = st.dsp;
@ -210,12 +210,12 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
} else if (ff->type.in(TW($adff), TW($adffe))) {
SigSpec arst = ff->getPort(TW::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
@ -225,7 +225,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
cell->setPort(rstport, State::S1);
}
}
if (ff->type.in(ID($dffe), ID($sdffe), ID($adffe))) {
if (ff->type.in(TW($dffe), TW($sdffe), TW($adffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
@ -252,7 +252,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
if (st.ffC) {
SigSpec C = cell->getPort(TW::C);
if (st.ffC->type.in(ID($adff), ID($adffe))) {
if (st.ffC->type.in(TW($adff), TW($adffe))) {
f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
} else {
f(C, st.ffC, ID(C_EN), ID(C_SRST_N), ID(C_BYPASS));

10
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -39,7 +39,7 @@ struct QlBramMergeWorker {
QlBramMergeWorker(RTLIL::Module* module) : module(module)
{
const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
const RTLIL::IdString split_cell_type = TW($__QLF_TDP36K);
for (RTLIL::Cell* cell : module->selected_cells())
{
@ -124,11 +124,11 @@ struct QlBramMergeWorker {
void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
{
const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
const RTLIL::IdString merged_cell_type = TW($__QLF_TDP36K_MERGED);
// Create the new cell
RTLIL::Cell* merged = module->addCell(NEW_TWINE, merged_cell_type);
log_debug("Merging split BRAM cells %s and %s -> %s\n", bram1->name.unescape(), bram2->name.unescape(), merged->name.unescape());
log_debug("Merging split BRAM cells %s and %s -> %s\n", design->twines.unescaped_str(bram1->name), design->twines.unescaped_str(bram2->name), design->twines.unescaped_str(merged->name));
for (auto &it : param_map(false))
{
@ -146,14 +146,14 @@ struct QlBramMergeWorker {
if (bram1->hasPort(it.first))
merged->setPort(it.second, bram1->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram1->name.unescape());
log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram1->name));
}
for (auto &it : port_map(true))
{
if (bram2->hasPort(it.first))
merged->setPort(it.second, bram2->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram2->name.unescape());
log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram2->name));
}
merged->attributes = bram1->attributes;
for (auto attr: bram2->attributes)

2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass {
}
cell->type = RTLIL::escape_id(type);
log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
}
}

6
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -73,11 +73,11 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
}
type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, type.unescape());
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, design->twines.unescaped_str(type));
for (auto cell : {st.mul, st.add, st.mux, st.ff})
if (cell)
log(" %s (%s)\n", cell, cell->type.unescape());
log(" %s (%s)\n", cell, cell->type.unescaped());
// Add the DSP cell
RTLIL::Cell *cell = pm.module->addCell(NEW_TWINE, type);
@ -169,7 +169,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// 3 - output post acc; 1 - output pre acc
cell->setPort(TW::output_select_i, RTLIL::Const(st.output_registered ? 1 : 3, 3));
bool subtract = (st.add->type == ID($sub));
bool subtract = (st.add->type == TW($sub));
cell->setPort(TW::subtract_i, RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
// Mark the cells for removal

4
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -150,8 +150,8 @@ struct QlDspSimdPass : public Pass {
// Create the new cell
Cell *simd = module->addCell(NEW_TWINE, m_SimdDspType);
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, dsp_a->type.unescape(),
dsp_b, dsp_b->type.unescape(), simd, simd->type.unescape());
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, design->twines.unescaped_str(dsp_a->type),
dsp_b, design->twines.unescaped_str(dsp_b->type), simd, design->twines.unescaped_str(simd->type));
// Check if the target cell is known (important to know
// its port widths)

98
techlibs/xilinx/xilinx_dsp.cc
View file

@ -115,7 +115,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
SigPool simds = simd_signals(module, sigmap);
for (auto cell : selected_cells) {
if (!cell->type.in(ID($add), ID($sub)))
if (!cell->type.in(TW($add), TW($sub)))
continue;
SigSpec Y = cell->getPort(TW::Y);
if (!is_allowed(Y, simds))
@ -129,9 +129,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
continue;
if (GetSize(B) > 12)
continue;
if (cell->type == ID($add))
if (cell->type == TW($add))
simd12_add.push_back(cell);
else if (cell->type == ID($sub))
else if (cell->type == TW($sub))
simd12_sub.push_back(cell);
}
else if (GetSize(Y) <= 25) {
@ -139,9 +139,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
continue;
if (GetSize(B) > 24)
continue;
if (cell->type == ID($add))
if (cell->type == TW($add))
simd24_add.push_back(cell);
else if (cell->type == ID($sub))
else if (cell->type == TW($sub))
simd24_sub.push_back(cell);
}
else
@ -222,7 +222,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(TW::CARRYOUT, CARRYOUT);
if (lane1->type == ID($sub))
if (lane1->type == TW($sub))
cell->setPort(TW::ALUMODE, Const::from_string("0011"));
module->remove(lane1);
@ -286,7 +286,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(TW::CARRYOUT, CARRYOUT);
if (lane1->type == ID($sub))
if (lane1->type == TW($sub))
cell->setPort(TW::ALUMODE, Const::from_string("0011"));
module->remove(lane1);
@ -305,27 +305,27 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
log("Analysing %s.%s for Xilinx DSP packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
log_debug("preSub: %s\n", st.preSub ? st.preSub->name.unescape() : "--");
log_debug("ffAD: %s\n", st.ffAD ? st.ffAD->name.unescape() : "--");
log_debug("ffA2: %s\n", st.ffA2 ? st.ffA2->name.unescape() : "--");
log_debug("ffA1: %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
log_debug("ffB2: %s\n", st.ffB2 ? st.ffB2->name.unescape() : "--");
log_debug("ffB1: %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
log_debug("ffD: %s\n", st.ffD ? st.ffD->name.unescape() : "--");
log_debug("dsp: %s\n", st.dsp ? st.dsp->name.unescape() : "--");
log_debug("ffM: %s\n", st.ffM ? st.ffM->name.unescape() : "--");
log_debug("postAdd: %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
log_debug("ffP: %s\n", st.ffP ? st.ffP->name.unescape() : "--");
log_debug("overflow: %s\n", st.overflow ? st.overflow->name.unescape() : "--");
log_debug("preAdd: %s\n", st.preAdd ? design->twines.unescaped_str(st.preAdd->name) : "--");
log_debug("preSub: %s\n", st.preSub ? design->twines.unescaped_str(st.preSub->name) : "--");
log_debug("ffAD: %s\n", st.ffAD ? design->twines.unescaped_str(st.ffAD->name) : "--");
log_debug("ffA2: %s\n", st.ffA2 ? design->twines.unescaped_str(st.ffA2->name) : "--");
log_debug("ffA1: %s\n", st.ffA1 ? design->twines.unescaped_str(st.ffA1->name) : "--");
log_debug("ffB2: %s\n", st.ffB2 ? design->twines.unescaped_str(st.ffB2->name) : "--");
log_debug("ffB1: %s\n", st.ffB1 ? design->twines.unescaped_str(st.ffB1->name) : "--");
log_debug("ffD: %s\n", st.ffD ? design->twines.unescaped_str(st.ffD->name) : "--");
log_debug("dsp: %s\n", st.dsp ? design->twines.unescaped_str(st.dsp->name) : "--");
log_debug("ffM: %s\n", st.ffM ? design->twines.unescaped_str(st.ffM->name) : "--");
log_debug("postAdd: %s\n", st.postAdd ? design->twines.unescaped_str(st.postAdd->name) : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? design->twines.unescaped_str(st.postAddMux->name) : "--");
log_debug("ffP: %s\n", st.ffP ? design->twines.unescaped_str(st.ffP->name) : "--");
log_debug("overflow: %s\n", st.overflow ? design->twines.unescaped_str(st.overflow->name) : "--");
Cell *cell = st.dsp;
if (st.preAdd || st.preSub) {
Cell* preAdder = st.preAdd ? st.preAdd : st.preSub;
log(" preadder %s (%s)\n", preAdder, preAdder->type.unescape());
log(" preadder %s (%s)\n", preAdder, design->twines.unescaped_str(preAdder->type));
bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool();
bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool();
if (st.sigA == preAdder->getPort(TW::B))
@ -334,13 +334,13 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
st.sigD.extend_u0(25, D_SIGNED);
cell->setPort(TW::A, st.sigA);
cell->setPort(TW::D, st.sigD);
if (preAdder->type == ID($add))
if (preAdder->type == TW($add))
cell->setPort(TW::INMODE, Const::from_string("00100"));
else
cell->setPort(TW::INMODE, Const::from_string("01100"));
if (st.ffAD) {
if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
if (st.ffAD->type.in(TW($dffe), TW($sdffe))) {
bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
SigSpec S = st.ffAD->getPort(TW::EN);
cell->setPort(TW::CEAD, pol ? S : pm.module->Not(NEW_TWINE, S));
@ -355,7 +355,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(preAdder);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
log(" postadder %s (%s)\n", st.postAdd, design->twines.unescaped_str(st.postAdd->type));
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) {
@ -381,12 +381,12 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(st.postAdd);
}
if (st.overflow) {
log(" overflow %s (%s)\n", st.overflow, st.overflow->type.unescape());
log(" overflow %s (%s)\n", st.overflow, design->twines.unescaped_str(st.overflow->type));
cell->setParam(ID(USE_PATTERN_DETECT), Const("PATDET"));
cell->setParam(ID(SEL_PATTERN), Const("PATTERN"));
cell->setParam(ID(SEL_MASK), Const("MASK"));
if (st.overflow->type == ID($ge)) {
if (st.overflow->type == TW($ge)) {
Const B = st.overflow->getPort(TW::B).as_const();
log_assert(std::count(B.begin(), B.end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1
@ -419,7 +419,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@ -427,7 +427,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setPort(rstport, State::S0);
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
if (ff->type.in(TW($dffe), TW($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
@ -538,23 +538,23 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
log_debug("ffA1: %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
log_debug("ffA0: %s\n", st.ffA0 ? st.ffA0->name.unescape() : "--");
log_debug("ffB1: %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
log_debug("ffB0: %s\n", st.ffB0 ? st.ffB0->name.unescape() : "--");
log_debug("ffD: %s\n", st.ffD ? st.ffD->name.unescape() : "--");
log_debug("dsp: %s\n", st.dsp ? st.dsp->name.unescape() : "--");
log_debug("ffM: %s\n", st.ffM ? st.ffM->name.unescape() : "--");
log_debug("postAdd: %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
log_debug("ffP: %s\n", st.ffP ? st.ffP->name.unescape() : "--");
log_debug("preAdd: %s\n", st.preAdd ? design->twines.unescaped_str(st.preAdd->name) : "--");
log_debug("ffA1: %s\n", st.ffA1 ? design->twines.unescaped_str(st.ffA1->name) : "--");
log_debug("ffA0: %s\n", st.ffA0 ? design->twines.unescaped_str(st.ffA0->name) : "--");
log_debug("ffB1: %s\n", st.ffB1 ? design->twines.unescaped_str(st.ffB1->name) : "--");
log_debug("ffB0: %s\n", st.ffB0 ? design->twines.unescaped_str(st.ffB0->name) : "--");
log_debug("ffD: %s\n", st.ffD ? design->twines.unescaped_str(st.ffD->name) : "--");
log_debug("dsp: %s\n", st.dsp ? design->twines.unescaped_str(st.dsp->name) : "--");
log_debug("ffM: %s\n", st.ffM ? design->twines.unescaped_str(st.ffM->name) : "--");
log_debug("postAdd: %s\n", st.postAdd ? design->twines.unescaped_str(st.postAdd->name) : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? design->twines.unescaped_str(st.postAddMux->name) : "--");
log_debug("ffP: %s\n", st.ffP ? design->twines.unescaped_str(st.ffP->name) : "--");
Cell *cell = st.dsp;
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.preAdd) {
log(" preadder %s (%s)\n", st.preAdd, st.preAdd->type.unescape());
log(" preadder %s (%s)\n", st.preAdd, design->twines.unescaped_str(st.preAdd->type));
bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -562,9 +562,9 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setPort(TW::B, st.sigB);
cell->setPort(TW::D, st.sigD);
opmode[4] = State::S1;
if (st.preAdd->type == ID($add))
if (st.preAdd->type == TW($add))
opmode[6] = State::S0;
else if (st.preAdd->type == ID($sub))
else if (st.preAdd->type == TW($sub))
opmode[6] = State::S1;
else
log_assert(!"strange pre-adder type");
@ -572,7 +572,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
pm.autoremove(st.preAdd);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
log(" postadder %s (%s)\n", st.postAdd, design->twines.unescaped_str(st.postAdd->type));
if (st.postAddMux) {
log_assert(st.ffP);
@ -606,7 +606,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@ -614,7 +614,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setPort(rstport, State::S0);
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
if (ff->type.in(TW($dffe), TW($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
@ -715,7 +715,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
auto &st = pm.st_xilinx_dsp_packC;
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", st.ffC ? st.ffC->name.unescape() : "--");
log_debug("ffC: %s\n", st.ffC ? design->twines.unescaped_str(st.ffC->name) : "--");
Cell *cell = st.dsp;
@ -729,7 +729,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (ff->type.in(ID($sdff), ID($sdffe))) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
@ -737,7 +737,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
cell->setPort(rstport, State::S0);
}
}
if (ff->type.in(ID($dffe), ID($sdffe))) {
if (ff->type.in(TW($dffe), TW($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));

54
techlibs/xilinx/xilinx_srl.cc
View file

@ -30,12 +30,12 @@ void run_fixed(xilinx_srl_pm &pm)
{
auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed;
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), design->twines.unescaped_str(st.first->type));
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_))) {
SigBit Q = cell->getPort(TW::Q);
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
@ -59,15 +59,15 @@ void run_fixed(xilinx_srl_pm &pm)
auto first_cell = ud.longest_chain.back();
auto last_cell = ud.longest_chain.front();
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
c->setParam(ID::INIT, initval.as_const());
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setParam(ID(CLKPOL), 1);
else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_), ID(FDRE_1)))
c->setParam(ID(CLKPOL), 0);
else if (first_cell->type.in(ID(FDRE))) {
if (!first_cell->getParam(ID(IS_C_INVERTED)).as_bool())
@ -77,9 +77,9 @@ void run_fixed(xilinx_srl_pm &pm)
}
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
c->setParam(ID(ENPOL), 1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
c->setParam(ID(ENPOL), 0);
else
c->setParam(ID(ENPOL), 2);
@ -88,9 +88,9 @@ void run_fixed(xilinx_srl_pm &pm)
c->setPort(TW::D, first_cell->getPort(TW::D));
c->setPort(TW::Q, last_cell->getPort(TW::Q));
c->setPort(TW::L, GetSize(ud.longest_chain)-1);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
c->setPort(TW::E, first_cell->getPort(TW::CE));
@ -100,7 +100,7 @@ void run_fixed(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, c->type.unescape());
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
}
void run_variable(xilinx_srl_pm &pm)
@ -108,14 +108,14 @@ void run_variable(xilinx_srl_pm &pm)
auto &st = pm.st_variable;
auto &ud = pm.ud_variable;
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), st.first->type.unescape());
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), design->twines.unescaped_str(st.first->type));
SigSpec initval;
for (const auto &i : ud.chain) {
auto cell = i.first;
auto slice = i.second;
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
SigBit Q = cell->getPort(TW::Q)[slice];
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
@ -134,46 +134,46 @@ void run_variable(xilinx_srl_pm &pm)
auto first_cell = ud.chain.back().first;
auto first_slice = ud.chain.back().second;
Cell *c = pm.module->addCell(NEW_TWINE, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEW_TWINE, TW($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_), TW($dff), TW($dffe))) {
c->setParam(ID::DEPTH, GetSize(ud.chain));
c->setParam(ID::INIT, initval.as_const());
Const clkpol, enpol;
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_P_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
clkpol = 1;
else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
else if (first_cell->type.in(TW($_DFF_N_), TW($_DFFE_NN_), TW($_DFFE_NP_)))
clkpol = 0;
else if (first_cell->type.in(ID($dff), ID($dffe)))
else if (first_cell->type.in(TW($dff), TW($dffe)))
clkpol = first_cell->getParam(ID::CLK_POLARITY);
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFFE_NP_), TW($_DFFE_PP_)))
enpol = 1;
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_PN_)))
enpol = 0;
else if (first_cell->type.in(ID($dffe)))
else if (first_cell->type.in(TW($dffe)))
enpol = first_cell->getParam(ID::EN_POLARITY);
else
enpol = 2;
c->setParam(ID(CLKPOL), clkpol);
c->setParam(ID(ENPOL), enpol);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::C, first_cell->getPort(TW::C));
else if (first_cell->type.in(ID($dff), ID($dffe)))
else if (first_cell->type.in(TW($dff), TW($dffe)))
c->setPort(TW::C, first_cell->getPort(TW::CLK));
else
log_abort();
c->setPort(TW::D, first_cell->getPort(TW::D)[first_slice]);
c->setPort(TW::Q, st.shiftx->getPort(TW::Y));
c->setPort(TW::L, st.shiftx->getPort(TW::B));
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
if (first_cell->type.in(TW($_DFF_N_), TW($_DFF_P_), TW($dff)))
c->setPort(TW::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
else if (first_cell->type.in(TW($_DFFE_NN_), TW($_DFFE_NP_), TW($_DFFE_PN_), TW($_DFFE_PP_)))
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID($dffe)))
else if (first_cell->type.in(TW($dffe)))
c->setPort(TW::E, first_cell->getPort(TW::EN));
else
log_abort();
@ -181,7 +181,7 @@ void run_variable(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, c->type.unescape());
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
}
struct XilinxSrlPass : public Pass {