mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-18 21:25:47 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -45,10 +45,10 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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RTLIL::Cell *cell = module->addCell(design->twines.add(Twine{ID(UUT).str()}), cell_type);
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RTLIL::Wire *wire;
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if (cell_type.in(ID($mux), ID($pmux)))
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if (cell_type.in(TW($mux), TW($pmux)))
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{
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int width = 1 + xorshift32(8 * bloat_factor);
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int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8);
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int swidth = cell_type == TW($mux) ? 1 : 1 + xorshift32(8);
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wire = module->addWire(TW::A);
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wire->width = width;
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@ -71,7 +71,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type.in(ID($_MUX_), ID($_NMUX_)))
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if (cell_type.in(TW($_MUX_), TW($_NMUX_)))
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{
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wire = module->addWire(TW::A);
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wire->width = 1;
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@ -94,7 +94,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type == ID($bmux))
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if (cell_type == TW($bmux))
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{
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int width = 1 + xorshift32(8 * bloat_factor);
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int swidth = 1 + xorshift32(4 * bloat_factor);
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@ -115,7 +115,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type == ID($demux))
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if (cell_type == TW($demux))
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{
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int width = 1 + xorshift32(8 * bloat_factor);
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int swidth = 1 + xorshift32(6 * bloat_factor);
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@ -136,7 +136,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type == ID($fa))
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if (cell_type == TW($fa))
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{
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int width = 1 + xorshift32(8 * bloat_factor);
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@ -166,7 +166,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type == ID($lcu))
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if (cell_type == TW($lcu))
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{
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int width = 1 + xorshift32(8 * bloat_factor);
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@ -190,7 +190,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::CO, wire);
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}
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if (cell_type == ID($macc_v2))
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if (cell_type == TW($macc_v2))
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{
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Macc macc;
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int width = 1 + xorshift32(8 * bloat_factor);
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@ -234,7 +234,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type == ID($lut))
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if (cell_type == TW($lut))
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{
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int width = 1 + xorshift32(6 * bloat_factor);
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@ -254,7 +254,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setParam(ID::LUT, config.as_const());
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}
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if (cell_type == ID($sop))
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if (cell_type == TW($sop))
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{
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int width = 1 + xorshift32(8 * bloat_factor);
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int depth = 1 + xorshift32(8 * bloat_factor);
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@ -355,22 +355,22 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type.in(ID($shiftx))) {
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if (cell_type.in(TW($shiftx))) {
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cell->parameters[ID::A_SIGNED] = false;
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}
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if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
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if (cell_type.in(TW($shl), TW($shr), TW($sshl), TW($sshr))) {
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cell->parameters[ID::B_SIGNED] = false;
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}
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if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
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if (muxdiv && cell_type.in(TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
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auto b_not_zero = module->ReduceBool(NEW_TWINE, cell->getPort(TW::B));
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auto div_out = module->addWire(NEW_TWINE, GetSize(cell->getPort(TW::Y)));
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module->addMux(NEW_TWINE, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(TW::Y));
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cell->setPort(TW::Y, div_out);
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}
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if (cell_type == ID($alu))
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if (cell_type == TW($alu))
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{
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wire = module->addWire(TW::CI);
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wire->port_input = true;
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@ -391,7 +391,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::CO, wire);
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}
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if (cell_type == ID($slice))
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if (cell_type == TW($slice))
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{
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int a_size = GetSize(cell->getPort(TW::A));
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int y_size = 1;
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@ -407,7 +407,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setParam(ID::OFFSET, 0);
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}
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if (cell_type == ID($concat))
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if (cell_type == TW($concat))
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{
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wire = module->addWire(TW::Y);
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wire->width = GetSize(cell->getPort(TW::A)) + GetSize(cell->getPort(TW::B));
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@ -415,7 +415,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type == ID($buf))
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if (cell_type == TW($buf))
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{
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wire = module->addWire(TW::Y);
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wire->width = GetSize(cell->getPort(TW::A));
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@ -423,14 +423,14 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(TW::Y, wire);
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}
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if (cell_type.in(ID($bwmux), ID($bweqx)))
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if (cell_type.in(TW($bwmux), TW($bweqx)))
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{
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int a_size = GetSize(cell->getPort(TW::A));
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wire = module->addWire(TW::B);
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wire->width = a_size;
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wire->port_input = true;
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cell->setPort(TW::B, wire);
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if (cell_type == ID($bwmux))
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if (cell_type == TW($bwmux))
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{
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wire = module->addWire(TW::S);
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wire->width = a_size;
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@ -984,101 +984,101 @@ struct TestCellPass : public Pass {
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std::map<IdString, std::string> cell_types;
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std::vector<IdString> selected_cell_types;
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cell_types[ID($not)] = "ASY";
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cell_types[ID($pos)] = "ASY";
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cell_types[ID($neg)] = "ASY";
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cell_types[TW($not)] = "ASY";
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cell_types[TW($pos)] = "ASY";
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cell_types[TW($neg)] = "ASY";
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// $buf is unsupported with techmap -assert
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if (techmap_cmd.compare("techmap -assert") != 0)
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cell_types[ID($buf)] = "A";
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cell_types[TW($buf)] = "A";
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cell_types[ID($and)] = "ABSY";
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cell_types[ID($or)] = "ABSY";
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cell_types[ID($xor)] = "ABSY";
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cell_types[ID($xnor)] = "ABSY";
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cell_types[TW($and)] = "ABSY";
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cell_types[TW($or)] = "ABSY";
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cell_types[TW($xor)] = "ABSY";
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cell_types[TW($xnor)] = "ABSY";
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cell_types[ID($reduce_and)] = "ASY";
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cell_types[ID($reduce_or)] = "ASY";
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cell_types[ID($reduce_xor)] = "ASY";
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cell_types[ID($reduce_xnor)] = "ASY";
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cell_types[ID($reduce_bool)] = "ASY";
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cell_types[TW($reduce_and)] = "ASY";
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cell_types[TW($reduce_or)] = "ASY";
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cell_types[TW($reduce_xor)] = "ASY";
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cell_types[TW($reduce_xnor)] = "ASY";
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cell_types[TW($reduce_bool)] = "ASY";
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cell_types[ID($shl)] = "ABshY";
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cell_types[ID($shr)] = "ABshY";
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cell_types[ID($sshl)] = "ABshY";
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cell_types[ID($sshr)] = "ABshY";
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cell_types[ID($shift)] = "ABshY";
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cell_types[ID($shiftx)] = "ABshY";
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cell_types[TW($shl)] = "ABshY";
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cell_types[TW($shr)] = "ABshY";
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cell_types[TW($sshl)] = "ABshY";
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cell_types[TW($sshr)] = "ABshY";
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cell_types[TW($shift)] = "ABshY";
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cell_types[TW($shiftx)] = "ABshY";
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cell_types[ID($lt)] = "ABSY";
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cell_types[ID($le)] = "ABSY";
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cell_types[ID($eq)] = "ABSY";
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cell_types[ID($ne)] = "ABSY";
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cell_types[TW($lt)] = "ABSY";
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cell_types[TW($le)] = "ABSY";
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cell_types[TW($eq)] = "ABSY";
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cell_types[TW($ne)] = "ABSY";
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// $eqx, $nex, and $bweqx don't work in sat, and are unsupported with
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// 'techmap -assert'
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if (nosat && techmap_cmd.compare("techmap -assert") != 0)
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{
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cell_types[ID($eqx)] = "ABSY";
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cell_types[ID($nex)] = "ABSY";
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cell_types[ID($bweqx)] = "A";
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cell_types[TW($eqx)] = "ABSY";
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cell_types[TW($nex)] = "ABSY";
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cell_types[TW($bweqx)] = "A";
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}
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cell_types[ID($ge)] = "ABSY";
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cell_types[ID($gt)] = "ABSY";
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cell_types[TW($ge)] = "ABSY";
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cell_types[TW($gt)] = "ABSY";
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cell_types[ID($add)] = "ABSY";
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cell_types[ID($sub)] = "ABSY";
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cell_types[ID($mul)] = "ABSY";
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cell_types[ID($div)] = "ABSY";
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cell_types[ID($mod)] = "ABSY";
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cell_types[ID($divfloor)] = "ABSY";
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cell_types[ID($modfloor)] = "ABSY";
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cell_types[TW($add)] = "ABSY";
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cell_types[TW($sub)] = "ABSY";
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cell_types[TW($mul)] = "ABSY";
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cell_types[TW($div)] = "ABSY";
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cell_types[TW($mod)] = "ABSY";
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cell_types[TW($divfloor)] = "ABSY";
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cell_types[TW($modfloor)] = "ABSY";
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// $pow doesnt work in sat, not supported with 'techmap -assert', and only
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// only partially supported with '-simlib'
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if (nosat && techmap_cmd.compare("aigmap") == 0)
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cell_types[ID($pow)] = "ABsY";
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cell_types[TW($pow)] = "ABsY";
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cell_types[ID($logic_not)] = "ASY";
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cell_types[ID($logic_and)] = "ABSY";
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cell_types[ID($logic_or)] = "ABSY";
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cell_types[TW($logic_not)] = "ASY";
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cell_types[TW($logic_and)] = "ABSY";
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cell_types[TW($logic_or)] = "ABSY";
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cell_types[ID($mux)] = "*";
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cell_types[ID($bmux)] = "*";
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cell_types[ID($demux)] = "*";
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cell_types[TW($mux)] = "*";
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cell_types[TW($bmux)] = "*";
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cell_types[TW($demux)] = "*";
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// $pmux doesn't work in sat, and is not supported with 'techmap -assert' or
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// '-simlib'
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if (nosat && techmap_cmd.compare("aigmap") == 0)
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cell_types[ID($pmux)] = "*";
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cell_types[ID($bwmux)] = "A";
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cell_types[TW($pmux)] = "*";
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cell_types[TW($bwmux)] = "A";
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cell_types[ID($slice)] = "A";
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cell_types[ID($concat)] = "AB";
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cell_types[TW($slice)] = "A";
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cell_types[TW($concat)] = "AB";
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cell_types[ID($lut)] = "*";
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cell_types[ID($sop)] = "*";
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cell_types[ID($alu)] = "ABSY";
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cell_types[ID($lcu)] = "*";
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cell_types[ID($macc_v2)] = "*";
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cell_types[ID($fa)] = "*";
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cell_types[TW($lut)] = "*";
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cell_types[TW($sop)] = "*";
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cell_types[TW($alu)] = "ABSY";
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cell_types[TW($lcu)] = "*";
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cell_types[TW($macc_v2)] = "*";
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cell_types[TW($fa)] = "*";
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cell_types[ID($_BUF_)] = "AYb";
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cell_types[ID($_NOT_)] = "AYb";
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cell_types[ID($_AND_)] = "ABYb";
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cell_types[ID($_NAND_)] = "ABYb";
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cell_types[ID($_OR_)] = "ABYb";
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cell_types[ID($_NOR_)] = "ABYb";
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cell_types[ID($_XOR_)] = "ABYb";
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cell_types[ID($_XNOR_)] = "ABYb";
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cell_types[ID($_ANDNOT_)] = "ABYb";
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cell_types[ID($_ORNOT_)] = "ABYb";
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cell_types[ID($_MUX_)] = "*";
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cell_types[ID($_NMUX_)] = "*";
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cell_types[TW($_BUF_)] = "AYb";
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cell_types[TW($_NOT_)] = "AYb";
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cell_types[TW($_AND_)] = "ABYb";
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cell_types[TW($_NAND_)] = "ABYb";
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cell_types[TW($_OR_)] = "ABYb";
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cell_types[TW($_NOR_)] = "ABYb";
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cell_types[TW($_XOR_)] = "ABYb";
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cell_types[TW($_XNOR_)] = "ABYb";
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cell_types[TW($_ANDNOT_)] = "ABYb";
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cell_types[TW($_ORNOT_)] = "ABYb";
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cell_types[TW($_MUX_)] = "*";
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cell_types[TW($_NMUX_)] = "*";
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// wide $_MUX_ cells are not yet implemented
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// cell_types[ID($_MUX4_)] = "*";
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// cell_types[ID($_MUX8_)] = "*";
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// cell_types[ID($_MUX16_)] = "*";
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cell_types[ID($_AOI3_)] = "ABCYb";
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cell_types[ID($_OAI3_)] = "ABCYb";
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cell_types[ID($_AOI4_)] = "ABCDYb";
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cell_types[ID($_OAI4_)] = "ABCDYb";
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// cell_types[TW($_MUX4_)] = "*";
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// cell_types[TW($_MUX8_)] = "*";
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// cell_types[TW($_MUX16_)] = "*";
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cell_types[TW($_AOI3_)] = "ABCYb";
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cell_types[TW($_OAI3_)] = "ABCYb";
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cell_types[TW($_AOI4_)] = "ABCDYb";
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cell_types[TW($_OAI4_)] = "ABCDYb";
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for (; argidx < GetSize(args); argidx++)
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{
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@ -1106,10 +1106,10 @@ struct TestCellPass : public Pass {
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int charcount = 100;
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for (auto &it : cell_types) {
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if (charcount > 60) {
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cell_type_list += stringf("\n%s", it.first.unescape());
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cell_type_list += stringf("\n%s", design->twines.unescaped_str(it.first));
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charcount = 0;
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} else
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cell_type_list += stringf(" %s", it.first.unescape());
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cell_type_list += stringf(" %s", design->twines.unescaped_str(it.first));
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charcount += GetSize(it.first);
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}
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log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
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