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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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82
passes/techmap/techmap.cc
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@ -93,17 +93,17 @@ struct TechmapWorker
RTLIL::SigBit bit = sigmap(conn.second[i]);
if (bit.wire == nullptr) {
if (verbose)
log(" Constant input on bit %d of port %s: %s\n", i, conn.first.unescape(), log_signal(bit));
constmap_info += stringf("|%s %d %d", conn.first.unescape(), i, bit.data);
log(" Constant input on bit %d of port %s: %s\n", i, design->twines.unescaped_str(conn.first), log_signal(bit));
constmap_info += stringf("|%s %d %d", design->twines.unescaped_str(conn.first), i, bit.data);
} else if (connbits_map.count(bit)) {
if (verbose)
log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, conn.first.unescape(),
connbits_map.at(bit).second, connbits_map.at(bit).first.unescape());
constmap_info += stringf("|%s %d %s %d", conn.first.unescape(), i,
log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, design->twines.unescaped_str(conn.first),
connbits_map.at(bit).second, design->twines.unescaped_str(connbits_map.at(bit).first));
constmap_info += stringf("|%s %d %s %d", design->twines.unescaped_str(conn.first), i,
connbits_map.at(bit).first.unescape(), connbits_map.at(bit).second);
} else {
connbits_map.emplace(bit, std::make_pair(conn.first, i));
constmap_info += stringf("|%s %d", conn.first.unescape(), i);
constmap_info += stringf("|%s %d", design->twines.unescaped_str(conn.first), i);
}
}
@ -146,7 +146,7 @@ struct TechmapWorker
if (tpl->processes.size() != 0) {
log("Technology map yielded processes:");
for (auto &it : tpl->processes)
log(" %s",it.first.unescape());
log(" design->twines.unescaped_str(%s",it.first));
log("\n");
if (autoproc_mode) {
Pass::call_on_module(tpl->design, tpl, "proc");
@ -440,7 +440,7 @@ struct TechmapWorker
if (celltypeMap.count(cell->type) == 0) {
if (assert_mode && !cell->type.ends_with("_"))
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", cell->type.unescape());
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", cell->type.unescaped());
continue;
}
@ -503,10 +503,10 @@ struct TechmapWorker
{
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{
std::string m_name = stringf("$extern:%s:%s", extmapper_name, cell->type.unescape());
std::string m_name = stringf("$extern:%s:%s", extmapper_name, cell->type.unescaped());
for (auto &c : cell->parameters)
m_name += stringf(":%s=%s", c.first.unescape(), log_signal(c.second));
m_name += stringf(":%s=%s", design->twines.unescaped_str(c.first), log_signal(c.second));
if (extmapper_name == "wrap")
m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
@ -539,15 +539,15 @@ struct TechmapWorker
if (extmapper_name == "simplemap") {
log("Creating %s with simplemap.\n", extmapper_module);
if (simplemap_mappers.count(extmapper_cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", extmapper_cell->type.unescape());
log_error("No simplemap mapper for cell type %s found!\n", design->twines.unescaped_str(extmapper_cell->type));
simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell);
}
if (extmapper_name == "maccmap") {
log("Creating %s with maccmap.\n", extmapper_module);
if (!extmapper_cell->type.in(ID($macc), ID($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", extmapper_cell->type.unescape());
if (!extmapper_cell->type.in(TW($macc), TW($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", design->twines.unescaped_str(extmapper_cell->type));
maccmap(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell);
}
@ -570,31 +570,31 @@ struct TechmapWorker
goto use_wrapper_tpl;
}
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_module, cell->type.unescape());
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_module, cell->type.unescaped());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_module);
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), extmapper_module);
}
else
{
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, cell->type.unescape());
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, cell->type.unescaped());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_name);
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), extmapper_name);
if (extmapper_name == "simplemap") {
if (simplemap_mappers.count(cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", cell->type.unescape());
log_error("No simplemap mapper for cell type %s found!\n", cell->type.unescaped());
simplemap_mappers.at(cell->type)(module, cell);
}
if (extmapper_name == "maccmap") {
if (!cell->type.in(ID($macc), ID($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", cell->type.unescape());
if (!cell->type.in(TW($macc), TW($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", cell->type.unescaped());
maccmap(module, cell);
}
@ -623,26 +623,26 @@ struct TechmapWorker
}
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescape());
parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescaped());
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0)
parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->module->design->twines.str(cell->meta_->name));
for (auto &conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", design->twines.unescaped_str(conn.first))) != 0) {
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
for (auto &bit : v)
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", design->twines.unescaped_str(conn.first)), RTLIL::SigSpec(v).as_const());
}
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", design->twines.unescaped_str(conn.first))) != 0) {
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
for (auto &bit : v)
if (bit.wire != nullptr)
bit = RTLIL::SigBit(RTLIL::State::Sx);
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", design->twines.unescaped_str(conn.first)), RTLIL::SigSpec(v).as_const());
}
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape())) != 0) {
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape()), initvals(conn.second));
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", design->twines.unescaped_str(conn.first))) != 0) {
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", design->twines.unescaped_str(conn.first)), initvals(conn.second));
}
}
@ -655,7 +655,7 @@ struct TechmapWorker
unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first))) != 0) {
for (auto &bit : sigmap(conn.second))
if (unique_bit_id.count(bit) == 0)
unique_bit_id[bit] = unique_bit_id_counter++;
@ -672,7 +672,7 @@ struct TechmapWorker
parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first))) != 0) {
SigSpec sm = sigmap(conn.second);
RTLIL::Const::Builder builder(GetSize(sm) * bits);
for (auto &bit : sm) {
@ -682,7 +682,7 @@ struct TechmapWorker
val = val >> 1;
}
}
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape()), builder.build());
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first)), builder.build());
}
}
@ -731,7 +731,7 @@ struct TechmapWorker
RTLIL::SigSpec value = elem.value;
if (value.is_fully_const() && value.as_bool()) {
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
derived_name.c_str(), elem.wire->name.unescape(), log_signal(value));
derived_name.c_str(), design->twines.unescaped_str(elem.wire->name), log_signal(value));
techmap_do_cache[tpl] = false;
}
}
@ -748,7 +748,7 @@ struct TechmapWorker
auto &data = it.second.front();
if (!data.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", data.wire->name.unescape(), log_signal(data.value));
log_error("Techmap yielded config wire %s with non-const value %s.\n", design->twines.unescaped_str(data.wire->name), log_signal(data.value));
techmap_wire_names.erase(it.first);
@ -765,7 +765,7 @@ struct TechmapWorker
log("Analyzing pattern of constant bits for this cell:\n");
IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
log("Creating constmapped module `%s'.\n", new_tpl_name.unescape());
log("Creating constmapped module `%s'.\n", design->twines.unescaped_str(new_tpl_name));
log_assert(map->module(new_tpl_name) == nullptr);
RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
@ -873,16 +873,16 @@ struct TechmapWorker
TechmapWires twd = techmap_find_special_wires(tpl);
for (auto &it : twd) {
if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_"))
log_error("Techmap yielded unknown config wire %s.\n", it.first.unescape());
log_error("Techmap yielded unknown config wire %s.\n", design->twines.unescaped_str(it.first));
if (techmap_do_cache[tpl])
for (auto &it2 : it.second)
if (!it2.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", it2.wire->name.unescape(), log_signal(it2.value));
log_error("Techmap yielded config wire %s with non-const value %s.\n", design->twines.unescaped_str(it2.wire->name), log_signal(it2.value));
techmap_wire_names.erase(it.first);
}
for (auto &it : techmap_wire_names)
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", it.unescape());
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", design->twines.unescaped_str(it));
if (recursive_mode) {
if (log_continue) {
@ -938,12 +938,12 @@ struct TechmapWorker
}
else
{
auto msg = stringf("Using template %s for cells of type %s.", tpl, cell->type.unescape());
auto msg = stringf("Using template %s for cells of type %s.", tpl, cell->type.unescaped());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), tpl);
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), tpl);
techmap_module_worker(design, module, cell, tpl);
cell = nullptr;
}
@ -953,7 +953,7 @@ struct TechmapWorker
}
if (assert_mode && !mapped_cell)
log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", module, cell, cell->type.unescape());
log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
handled_cells.insert(cell);
}
@ -1275,8 +1275,8 @@ struct TechmapPass : public Pass {
i.second.sort(RTLIL::sort_by_id_str());
std::string maps = "";
for (auto &map : i.second)
maps += stringf(" %s", map.unescape());
log_debug(" %s:%s\n", i.first.unescape(), maps);
maps += stringf(" %s", design->twines.unescaped_str(map));
log_debug(" %s:%s\n", design->twines.unescaped_str(i.first), maps);
}
log_debug("\n");