3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-18 21:25:47 +00:00
This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions

View file

@ -82,7 +82,7 @@ struct NlutmapWorker
for (auto cell : module->cells())
{
if (cell->type != ID($lut) || mapped_cells.count(cell))
if (cell->type != TW($lut) || mapped_cells.count(cell))
continue;
if (GetSize(cell->getPort(TW::A)) == lut_size || lut_size == 2)
@ -119,7 +119,7 @@ struct NlutmapWorker
if (config.assert_mode) {
for (auto cell : module->cells())
if (cell->type == ID($lut) && !mapped_cells.count(cell))
if (cell->type == TW($lut) && !mapped_cells.count(cell))
log_error("Insufficient number of LUTs to map all logic cells!\n");
}