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WIP
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afdae7b87e
commit
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229 changed files with 3902 additions and 3835 deletions
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@ -58,9 +58,9 @@ struct ExtractReducePass : public Pass
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inline bool IsRightType(Cell* cell, GateType gt)
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{
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return (cell->type == ID($_AND_) && gt == GateType::And) ||
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(cell->type == ID($_OR_) && gt == GateType::Or) ||
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(cell->type == ID($_XOR_) && gt == GateType::Xor);
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return (cell->type == TW($_AND_) && gt == GateType::And) ||
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(cell->type == TW($_OR_) && gt == GateType::Or) ||
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(cell->type == TW($_XOR_) && gt == GateType::Xor);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -124,11 +124,11 @@ struct ExtractReducePass : public Pass
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GateType gt;
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if (cell->type == ID($_AND_))
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if (cell->type == TW($_AND_))
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gt = GateType::And;
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else if (cell->type == ID($_OR_))
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else if (cell->type == TW($_OR_))
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gt = GateType::Or;
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else if (cell->type == ID($_XOR_))
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else if (cell->type == TW($_XOR_))
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gt = GateType::Xor;
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else
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continue;
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@ -261,7 +261,7 @@ struct ExtractReducePass : public Pass
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SigSpec input;
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for (auto it : sources) {
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bool cond;
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if (head_cell->type == ID($_XOR_))
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if (head_cell->type == TW($_XOR_))
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cond = it.second & 1;
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else
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cond = it.second != 0;
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@ -269,11 +269,11 @@ struct ExtractReducePass : public Pass
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input.append(it.first);
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}
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if (head_cell->type == ID($_AND_)) {
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if (head_cell->type == TW($_AND_)) {
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module->addReduceAnd(NEW_TWINE, input, output);
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} else if (head_cell->type == ID($_OR_)) {
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} else if (head_cell->type == TW($_OR_)) {
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module->addReduceOr(NEW_TWINE, input, output);
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} else if (head_cell->type == ID($_XOR_)) {
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} else if (head_cell->type == TW($_XOR_)) {
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module->addReduceXor(NEW_TWINE, input, output);
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} else {
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log_assert(false);
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