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https://github.com/YosysHQ/yosys
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WIP
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parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -258,7 +258,7 @@ int counter_tryextract(
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return 9;
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Cell* count_mux = *y_loads.begin();
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extract.count_mux = count_mux;
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if(count_mux->type != ID($mux))
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if(count_mux->type != TW($mux))
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return 10;
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if(!is_full_bus(aluy, index, cell, ID::Y, count_mux, ID::A))
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return 11;
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@ -287,9 +287,9 @@ int counter_tryextract(
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Cell* overflow_cell = NULL;
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for(auto c : muxsel_conns)
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{
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if(extract.count_is_up && c->type != ID($eq))
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if(extract.count_is_up && c->type != TW($eq))
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continue;
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if(!extract.count_is_up && c->type != ID($logic_not))
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if(!extract.count_is_up && c->type != TW($logic_not))
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continue;
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if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID::S, true))
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continue;
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@ -311,7 +311,7 @@ int counter_tryextract(
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Cell* count_reg = muxload;
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Cell* cemux = NULL;
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RTLIL::SigSpec cey;
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if(muxload->type == ID($mux))
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if(muxload->type == TW($mux))
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{
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//This mux is probably a clock enable mux.
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//Find our count register (should be our only load)
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@ -349,9 +349,9 @@ int counter_tryextract(
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extract.has_ce = false;
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extract.count_reg = count_reg;
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if(count_reg->type == ID($dff))
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if(count_reg->type == TW($dff))
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extract.has_reset = false;
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else if(count_reg->type == ID($adff))
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else if(count_reg->type == TW($adff))
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{
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if (!settings.allow_arst)
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return 25;
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@ -517,7 +517,7 @@ void counter_worker(
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SigMap& sigmap = index.sigmap;
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//Core of the counter must be an ALU
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if (cell->type != ID($alu))
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if (cell->type != TW($alu))
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return;
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//A input is the count value. Check if it has COUNT_EXTRACT set.
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@ -611,7 +611,7 @@ void counter_worker(
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}
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//Get new cell name
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string countname = string("$COUNTx$") + extract.rwire->name.unescape();
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string countname = string("$COUNTx$") + design->twines.unescaped_str(extract.rwire->name);
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//Wipe all of the old connections to the ALU
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cell->unsetPort(TW::A);
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@ -697,7 +697,7 @@ void counter_worker(
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//Hook up any parallel outputs
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for(auto load : extract.pouts)
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{
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log(" Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), load.port.unescape());
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log(" Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(load.port));
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}
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if(extract.has_pout)
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{
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