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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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86
passes/techmap/abc.cc
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@ -474,7 +474,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
return true;
}
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
if (cell->type.in(TW($_BUF_), TW($_NOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
@ -482,13 +482,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
assign_map.apply(sig_a);
assign_map.apply(sig_y);
map_signal(assign_map, sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(assign_map, sig_a));
map_signal(assign_map, sig_y, cell->type == TW($_BUF_) ? G(BUF) : G(NOT), map_signal(assign_map, sig_a));
module->remove(cell);
return true;
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -501,21 +501,21 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_a = map_signal(assign_map, sig_a);
int mapped_b = map_signal(assign_map, sig_b);
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
map_signal(assign_map, sig_y, G(AND), mapped_a, mapped_b);
else if (cell->type == ID($_NAND_))
else if (cell->type == TW($_NAND_))
map_signal(assign_map, sig_y, G(NAND), mapped_a, mapped_b);
else if (cell->type == ID($_OR_))
else if (cell->type == TW($_OR_))
map_signal(assign_map, sig_y, G(OR), mapped_a, mapped_b);
else if (cell->type == ID($_NOR_))
else if (cell->type == TW($_NOR_))
map_signal(assign_map, sig_y, G(NOR), mapped_a, mapped_b);
else if (cell->type == ID($_XOR_))
else if (cell->type == TW($_XOR_))
map_signal(assign_map, sig_y, G(XOR), mapped_a, mapped_b);
else if (cell->type == ID($_XNOR_))
else if (cell->type == TW($_XNOR_))
map_signal(assign_map, sig_y, G(XNOR), mapped_a, mapped_b);
else if (cell->type == ID($_ANDNOT_))
else if (cell->type == TW($_ANDNOT_))
map_signal(assign_map, sig_y, G(ANDNOT), mapped_a, mapped_b);
else if (cell->type == ID($_ORNOT_))
else if (cell->type == TW($_ORNOT_))
map_signal(assign_map, sig_y, G(ORNOT), mapped_a, mapped_b);
else
log_abort();
@ -524,7 +524,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
return true;
}
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
if (cell->type.in(TW($_MUX_), TW($_NMUX_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -540,13 +540,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_b = map_signal(assign_map, sig_b);
int mapped_s = map_signal(assign_map, sig_s);
map_signal(assign_map, sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
map_signal(assign_map, sig_y, cell->type == TW($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
module->remove(cell);
return true;
}
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
if (cell->type.in(TW($_AOI3_), TW($_OAI3_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -562,13 +562,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_b = map_signal(assign_map, sig_b);
int mapped_c = map_signal(assign_map, sig_c);
map_signal(assign_map, sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
map_signal(assign_map, sig_y, cell->type == TW($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
module->remove(cell);
return true;
}
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
if (cell->type.in(TW($_AOI4_), TW($_OAI4_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -587,7 +587,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_c = map_signal(assign_map, sig_c);
int mapped_d = map_signal(assign_map, sig_d);
map_signal(assign_map, sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
map_signal(assign_map, sig_y, cell->type == TW($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
module->remove(cell);
return true;
@ -1481,42 +1481,42 @@ void emit_global_input_files(const AbcConfig &config)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(TW($_BUF_)));
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_NOT_)));
if (config.enabled_gates.count("AND"))
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(TW($_AND_)));
if (config.enabled_gates.count("NAND"))
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_NAND_)));
if (config.enabled_gates.count("OR"))
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(TW($_OR_)));
if (config.enabled_gates.count("NOR"))
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_NOR_)));
if (config.enabled_gates.count("XOR"))
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_XOR_)));
if (config.enabled_gates.count("XNOR"))
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_XNOR_)));
if (config.enabled_gates.count("ANDNOT"))
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_ANDNOT_)));
if (config.enabled_gates.count("ORNOT"))
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_ORNOT_)));
if (config.enabled_gates.count("AOI3"))
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_AOI3_)));
if (config.enabled_gates.count("OAI3"))
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_OAI3_)));
if (config.enabled_gates.count("AOI4"))
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_AOI4_)));
if (config.enabled_gates.count("OAI4"))
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_OAI4_)));
if (config.enabled_gates.count("MUX"))
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_MUX_)));
if (config.enabled_gates.count("NMUX"))
fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_NMUX_)));
if (config.map_mux4)
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(TW($_MUX_)));
if (config.map_mux8)
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(TW($_MUX_)));
if (config.map_mux16)
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(TW($_MUX_)));
fclose(f);
}
}
@ -1584,7 +1584,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_NOT_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@ -1614,7 +1614,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX4_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@ -1624,7 +1624,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX8_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@ -1634,7 +1634,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX16_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
@ -1754,7 +1754,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
if (c->type == TW($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(TW::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(TW::Y).as_wire()->name));
connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
@ -2503,11 +2503,11 @@ struct AbcPass : public Pass {
if (bit.wire != nullptr) {
cell_to_bit[cell].insert(bit);
bit_to_cell[bit].insert(cell);
if (ct.cell_input(cell->type, conn.first)) {
if (ct.cell_input(cell->type_impl, conn.first)) {
cell_to_bit_up[cell].insert(bit);
bit_to_cell_down[bit].insert(cell);
}
if (ct.cell_output(cell->type, conn.first)) {
if (ct.cell_output(cell->type_impl, conn.first)) {
cell_to_bit_down[cell].insert(bit);
bit_to_cell_up[bit].insert(cell);
}