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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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86
passes/techmap/abc.cc
View file

@ -474,7 +474,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
return true;
}
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
if (cell->type.in(TW($_BUF_), TW($_NOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
@ -482,13 +482,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
assign_map.apply(sig_a);
assign_map.apply(sig_y);
map_signal(assign_map, sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(assign_map, sig_a));
map_signal(assign_map, sig_y, cell->type == TW($_BUF_) ? G(BUF) : G(NOT), map_signal(assign_map, sig_a));
module->remove(cell);
return true;
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -501,21 +501,21 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_a = map_signal(assign_map, sig_a);
int mapped_b = map_signal(assign_map, sig_b);
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
map_signal(assign_map, sig_y, G(AND), mapped_a, mapped_b);
else if (cell->type == ID($_NAND_))
else if (cell->type == TW($_NAND_))
map_signal(assign_map, sig_y, G(NAND), mapped_a, mapped_b);
else if (cell->type == ID($_OR_))
else if (cell->type == TW($_OR_))
map_signal(assign_map, sig_y, G(OR), mapped_a, mapped_b);
else if (cell->type == ID($_NOR_))
else if (cell->type == TW($_NOR_))
map_signal(assign_map, sig_y, G(NOR), mapped_a, mapped_b);
else if (cell->type == ID($_XOR_))
else if (cell->type == TW($_XOR_))
map_signal(assign_map, sig_y, G(XOR), mapped_a, mapped_b);
else if (cell->type == ID($_XNOR_))
else if (cell->type == TW($_XNOR_))
map_signal(assign_map, sig_y, G(XNOR), mapped_a, mapped_b);
else if (cell->type == ID($_ANDNOT_))
else if (cell->type == TW($_ANDNOT_))
map_signal(assign_map, sig_y, G(ANDNOT), mapped_a, mapped_b);
else if (cell->type == ID($_ORNOT_))
else if (cell->type == TW($_ORNOT_))
map_signal(assign_map, sig_y, G(ORNOT), mapped_a, mapped_b);
else
log_abort();
@ -524,7 +524,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
return true;
}
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
if (cell->type.in(TW($_MUX_), TW($_NMUX_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -540,13 +540,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_b = map_signal(assign_map, sig_b);
int mapped_s = map_signal(assign_map, sig_s);
map_signal(assign_map, sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
map_signal(assign_map, sig_y, cell->type == TW($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
module->remove(cell);
return true;
}
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
if (cell->type.in(TW($_AOI3_), TW($_OAI3_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -562,13 +562,13 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_b = map_signal(assign_map, sig_b);
int mapped_c = map_signal(assign_map, sig_c);
map_signal(assign_map, sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
map_signal(assign_map, sig_y, cell->type == TW($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
module->remove(cell);
return true;
}
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
if (cell->type.in(TW($_AOI4_), TW($_OAI4_)))
{
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
@ -587,7 +587,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
int mapped_c = map_signal(assign_map, sig_c);
int mapped_d = map_signal(assign_map, sig_d);
map_signal(assign_map, sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
map_signal(assign_map, sig_y, cell->type == TW($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
module->remove(cell);
return true;
@ -1481,42 +1481,42 @@ void emit_global_input_files(const AbcConfig &config)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(TW($_BUF_)));
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_NOT_)));
if (config.enabled_gates.count("AND"))
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(TW($_AND_)));
if (config.enabled_gates.count("NAND"))
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_NAND_)));
if (config.enabled_gates.count("OR"))
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(TW($_OR_)));
if (config.enabled_gates.count("NOR"))
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_NOR_)));
if (config.enabled_gates.count("XOR"))
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_XOR_)));
if (config.enabled_gates.count("XNOR"))
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_XNOR_)));
if (config.enabled_gates.count("ANDNOT"))
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_ANDNOT_)));
if (config.enabled_gates.count("ORNOT"))
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_ORNOT_)));
if (config.enabled_gates.count("AOI3"))
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_AOI3_)));
if (config.enabled_gates.count("OAI3"))
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_OAI3_)));
if (config.enabled_gates.count("AOI4"))
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_AOI4_)));
if (config.enabled_gates.count("OAI4"))
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(TW($_OAI4_)));
if (config.enabled_gates.count("MUX"))
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_MUX_)));
if (config.enabled_gates.count("NMUX"))
fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(TW($_NMUX_)));
if (config.map_mux4)
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(TW($_MUX_)));
if (config.map_mux8)
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(TW($_MUX_)));
if (config.map_mux16)
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(TW($_MUX_)));
fclose(f);
}
}
@ -1584,7 +1584,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_NOT_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@ -1614,7 +1614,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX4_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@ -1624,7 +1624,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX8_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
@ -1634,7 +1634,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX16_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
@ -1754,7 +1754,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
continue;
}
if (c->type == ID($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
if (c->type == TW($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(TW::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(TW::Y).as_wire()->name));
connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
@ -2503,11 +2503,11 @@ struct AbcPass : public Pass {
if (bit.wire != nullptr) {
cell_to_bit[cell].insert(bit);
bit_to_cell[bit].insert(cell);
if (ct.cell_input(cell->type, conn.first)) {
if (ct.cell_input(cell->type_impl, conn.first)) {
cell_to_bit_up[cell].insert(bit);
bit_to_cell_down[bit].insert(cell);
}
if (ct.cell_output(cell->type, conn.first)) {
if (ct.cell_output(cell->type_impl, conn.first)) {
cell_to_bit_down[cell].insert(bit);
bit_to_cell_up[bit].insert(cell);
}

110
passes/techmap/abc9_ops.cc
View file

@ -48,7 +48,7 @@ void check(RTLIL::Design *design, bool dff_mode)
auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), RTLIL::IdString(m->name)));
if (!r.second)
log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
m, id, r.first->second.unescape());
m, id, design->twines.unescaped_str(r.first->second));
}
// Make carry in the last PI, and carry out the last PO
@ -89,13 +89,13 @@ void check(RTLIL::Design *design, bool dff_mode)
if (dff_mode) {
static pool<IdString> unsupported{
ID($adff), ID($dlatch), ID($dlatchsr), ID($sr),
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
ID($_DLATCH_N_), ID($_DLATCH_P_),
ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
TW($adff), TW($dlatch), TW($dlatchsr), TW($sr),
TW($_DFF_NN0_), TW($_DFF_NN1_), TW($_DFF_NP0_), TW($_DFF_NP1_),
TW($_DFF_PN0_), TW($_DFF_PN1_), TW($_DFF_PP0_), TW($_DFF_PP1_),
TW($_DLATCH_N_), TW($_DLATCH_P_),
TW($_DLATCHSR_NNN_), TW($_DLATCHSR_NNP_), TW($_DLATCHSR_NPN_), TW($_DLATCHSR_NPP_),
TW($_DLATCHSR_PNN_), TW($_DLATCHSR_PNP_), TW($_DLATCHSR_PPN_), TW($_DLATCHSR_PPP_),
TW($_SR_NN_), TW($_SR_NP_), TW($_SR_PN_), TW($_SR_PP_)
};
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
@ -120,14 +120,14 @@ void check(RTLIL::Design *design, bool dff_mode)
if (!derived_module->get_bool_attribute(ID::abc9_flop))
continue;
if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", derived_type.unescape());
log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", design->twines.unescaped_str(derived_type));
if (derived_module->has_processes())
Pass::call_on_module(design, derived_module, "proc -noopt");
bool found = false;
for (auto derived_cell : derived_module->cells()) {
if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
if (derived_cell->type.in(TW($dff), TW($_DFF_N_), TW($_DFF_P_))) {
if (found)
log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", derived_module);
found = true;
@ -136,13 +136,13 @@ void check(RTLIL::Design *design, bool dff_mode)
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", derived_module, derived_cell->type.unescape());
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
}
else if (unsupported.count(derived_cell->type))
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", derived_module, derived_cell->type.unescape());
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
}
}
}
@ -182,7 +182,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
else {
bool has_timing = false;
for (auto derived_cell : derived_module->cells()) {
if (derived_cell->type.in(ID($specify2), ID($specify3), ID($specrule))) {
if (derived_cell->type.in(TW($specify2), TW($specify3), TW($specrule))) {
// If the module contains timing; then we potentially care about deriving its content too,
// as timings (or associated port widths) could be dependent on parameters.
has_timing = true;
@ -208,7 +208,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
if (derived_module->get_bool_attribute(ID::abc9_flop)) {
for (auto derived_cell : derived_module->cells())
if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
if (derived_cell->type.in(TW($dff), TW($_DFF_N_), TW($_DFF_P_))) {
SigBit Q = derived_cell->getPort(TW::Q);
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
@ -216,7 +216,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
// Block sequential synthesis on cells with (* init *) != 1'b0
// because ABC9 doesn't support them
if (init != State::S0) {
log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", derived_module, derived_cell->type.unescape());
log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
derived_module->set_bool_attribute(ID::abc9_flop, false);
}
break;
@ -344,7 +344,7 @@ void prep_bypass(RTLIL::Design *design)
// For these new input ports driven by the replaced
// cell, then create a new simple-path specify entry:
// (input => output) = 0
auto specify = bypass_module->addCell(NEW_TWINE, ID($specify2));
auto specify = bypass_module->addCell(NEW_TWINE, TW($specify2));
specify->setPort(TW::EN, State::S1);
specify->setPort(TW::SRC, src);
specify->setPort(TW::DST, dst);
@ -369,7 +369,7 @@ void prep_bypass(RTLIL::Design *design)
// module ports; create new input port if one doesn't
// already exist
for (auto cell : inst_module->cells()) {
if (cell->type != ID($specify2))
if (cell->type != TW($specify2))
continue;
auto EN = cell->getPort(TW::EN).as_bit();
SigBit newEN;
@ -454,7 +454,7 @@ void prep_bypass(RTLIL::Design *design)
void prep_dff(RTLIL::Design *design)
{
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection::EmptySelection(design)));
auto r = design->selection_vars.insert(std::make_pair(TW($abc9_flops), RTLIL::Selection::EmptySelection(design)));
auto &modules_sel = r.first->second;
for (auto module : design->selected_modules())
@ -473,7 +473,7 @@ void prep_dff(RTLIL::Design *design)
// be instantiating the derived module which will have had any parameters constant-propagated.
// This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
// Please file a bug report!
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
}
modules_sel.select(inst_module);
}
@ -490,13 +490,13 @@ void prep_dff_submod(RTLIL::Design *design)
continue;
for (auto cell : module->cells())
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_))) {
log_assert(!dff_cell);
dff_cell = cell;
Q = cell->getPort(TW::Q);
log_assert(GetSize(Q.wire) == 1);
}
else if (cell->type.in(ID($specify3), ID($specrule)))
else if (cell->type.in(TW($specify3), TW($specrule)))
specify_cells.emplace_back(cell);
log_assert(dff_cell);
@ -603,7 +603,7 @@ void break_scc(RTLIL::Module *module)
if (!I.empty())
{
auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEW_TWINE, TW($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(TW::I, std::move(I));
@ -625,7 +625,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
}
for (auto cell : module->cells()) {
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($_DFF_N_), ID($_DFF_P_)))
if (cell->type.in(TW($_AND_), TW($_NOT_), TW($_DFF_N_), TW($_DFF_P_)))
continue;
log_assert(!cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
@ -657,7 +657,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
// Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
// (or bypassed white-boxes with required times)
dict<int, IdString> box_cache;
Module *delay_module = design->module(ID($__ABC9_DELAY));
Module *delay_module = design->module(TW($__ABC9_DELAY));
log_assert(delay_module);
for (auto cell : cells) {
auto module = cell->module;
@ -668,7 +668,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto port_wire = inst_module->wire(i.first.name);
if (!port_wire)
log_error("Port %s in cell %s (type %s) from module %s does not actually exist",
i.first.name.unescape(), cell, cell->type.unescape(), module);
i.first.name.unescape(), cell, cell->type.unescaped(), module);
log_assert(port_wire->port_input);
auto d = i.second.first;
@ -687,7 +687,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
if (ys_debug(1)) {
static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
if (seen.emplace(cell->type, i.first).second) log("%s.%s[%d] abc9_required = %d\n",
cell->type.unescape(), i.first.name.unescape(), offset, d);
cell->type.unescape(), design->twines.unescaped_str(i.first.name), offset, d);
}
#endif
auto r = box_cache.insert(d);
@ -714,7 +714,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
dict<IdString, std::vector<IdString>> box_ports;
for (auto cell : module->cells()) {
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
continue;
if (cell->has_keep_attr())
continue;
@ -759,7 +759,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
for (auto cell : module->cells()) {
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
continue;
if (cell->has_keep_attr())
continue;
@ -768,7 +768,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
if (!(inst_module && inst_module->get_bool_attribute(ID::abc9_box)) && !yosys_celltypes.cell_known(cell->type))
if (!(inst_module && inst_module->get_bool_attribute(ID::abc9_box)) && !yosys_celltypes.cell_known(cell->type_impl))
continue;
// TODO: Speed up toposort -- we care about box ordering only
@ -828,7 +828,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
if (!I.empty()) {
auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEW_TWINE, TW($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(TW::I, std::move(I));
@ -847,7 +847,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto cell_name : it) {
auto cell = module->cell(cell_name);
log_assert(cell);
log("\t%s (%s @ %s)\n", cell, cell->type.unescape(), cell->get_src_attribute());
log("\t%s (%s @ %s)\n", cell, cell->type.unescaped(), cell->get_src_attribute());
}
}
}
@ -881,7 +881,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
// be instantiating the derived module which will have had any parameters constant-propagated.
// This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
// Please file a bug report!
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", cell_name.unescape(), cell->type.unescape());
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", design->twines.unescaped_str(cell_name), cell->type.unescaped());
}
log_assert(box_module->get_blackbox_attribute());
@ -916,7 +916,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
}
else if (w->port_output)
conn = holes_module->addWire(stringf("%s.%s", cell->type, port_name.unescape()), GetSize(w));
conn = holes_module->addWire(stringf("%s.%s", cell->type, design->twines.unescaped_str(port_name)), GetSize(w));
}
}
else // box_module is a blackbox
@ -928,7 +928,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(w);
if (!w->port_output)
continue;
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, port_name.unescape()), GetSize(w));
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, design->twines.unescaped_str(port_name)), GetSize(w));
holes_wire->port_output = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
@ -980,9 +980,9 @@ void prep_lut(RTLIL::Design *design, int maxlut)
auto r = table.emplace(K, entry);
if (!r.second) {
if (r.first->second.area != entry.area)
log_error("Modules '%s' and '%s' have conflicting (* abc9_lut *) values.\n", module, r.first->second.name.unescape());
log_error("Modules '%s' and '%s' have conflicting (* abc9_lut *) values.\n", module, design->twines.unescaped_str(r.first->second.name));
if (r.first->second.delays != entry.delays)
log_error("Modules '%s' and '%s' have conflicting specify entries.\n", module, r.first->second.name.unescape());
log_error("Modules '%s' and '%s' have conflicting specify entries.\n", module, design->twines.unescaped_str(r.first->second.name));
}
}
@ -1001,7 +1001,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
ss << std::endl;
}
for (const auto &i : table) {
ss << "# " << i.second.name.unescape() << std::endl;
ss << "# " << design->twines.unescaped_str(i.second.name) << std::endl;
ss << i.first << " " << i.second.area;
for (const auto &j : i.second.delays)
ss << " " << j;
@ -1045,7 +1045,7 @@ void prep_box(RTLIL::Design *design)
}
log_assert(num_outputs == 1);
ss << module->name.unescape() << " " << r.first->second.as_int();
ss << design->twines.unescaped_str(module->name) << " " << r.first->second.as_int();
log_assert(module->get_bool_attribute(ID::whitebox));
ss << " " << "1";
ss << " " << num_inputs << " " << num_outputs << std::endl;
@ -1060,7 +1060,7 @@ void prep_box(RTLIL::Design *design)
first = false;
else
ss << " ";
ss << wire->name.unescape();
ss << design->twines.unescaped_str(wire->name);
}
ss << std::endl;
@ -1134,7 +1134,7 @@ void prep_box(RTLIL::Design *design)
outputs.emplace_back(wire, i);
}
ss << module->name.unescape() << " " << module->attributes.at(ID::abc9_box_id).as_int();
ss << design->twines.unescaped_str(module->name) << " " << module->attributes.at(ID::abc9_box_id).as_int();
bool has_model = module->get_bool_attribute(ID::whitebox) || !module->get_bool_attribute(ID::blackbox);
ss << " " << (has_model ? "1" : "0");
ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
@ -1147,9 +1147,9 @@ void prep_box(RTLIL::Design *design)
else
ss << " ";
if (GetSize(i.wire) == 1)
ss << i.wire->name.unescape();
ss << design->twines.unescaped_str(i.wire->name);
else
ss << i.wire->name.unescape() << "[" << i.offset << "]";
ss << design->twines.unescaped_str(i.wire->name) << "[" << i.offset << "]";
}
ss << std::endl;
@ -1173,9 +1173,9 @@ void prep_box(RTLIL::Design *design)
}
ss << " # ";
if (GetSize(o.wire) == 1)
ss << o.wire->name.unescape();
ss << design->twines.unescaped_str(o.wire->name);
else
ss << o.wire->name.unescape() << "[" << o.offset << "]";
ss << design->twines.unescaped_str(o.wire->name) << "[" << o.offset << "]";
ss << std::endl;
}
ss << std::endl;
@ -1269,7 +1269,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Short out (so that existing name can be preserved) and remove
// $_DFF_[NP]_ cells since flop box already has all the information
// we need to reconstruct them
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
if (dff_mode && cell->type.in(TW($_DFF_N_), TW($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
SigBit Q = cell->getPort(TW::Q);
module->connect(Q, cell->getPort(TW::D));
module->remove(cell);
@ -1278,7 +1278,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
if (it != Qi.wire->attributes.end())
it->second.set(Qi.offset, State::Sx);
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))
else if (cell->type.in(TW($_AND_), TW($_NOT_)))
module->remove(cell);
else if (cell->attributes.erase(ID::abc9_box_seq))
boxes.emplace_back(cell);
@ -1294,7 +1294,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
{
// Short out $_FF_ cells since the flop box already has
// all the information we need to reconstruct cell
if (dff_mode && mapped_cell->type == ID($_FF_)) {
if (dff_mode && mapped_cell->type == TW($_FF_)) {
SigBit D = mapped_cell->getPort(TW::D);
SigBit Q = mapped_cell->getPort(TW::Q);
if (D.wire)
@ -1307,7 +1307,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// TODO: Speed up toposort -- we care about NOT ordering only
toposort.node(mapped_cell->name);
if (mapped_cell->type == ID($_NOT_)) {
if (mapped_cell->type == TW($_NOT_)) {
RTLIL::SigBit a_bit = mapped_cell->getPort(TW::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(TW::Y);
bit_users[a_bit].insert(mapped_cell->name);
@ -1345,7 +1345,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::SigBit(module->wire(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(TW::A)].push_back(cell);
cell_stats[ID($lut)]++;
cell_stats[TW($lut)]++;
}
else
not2drivers[mapped_cell] = driver_lut;
@ -1353,7 +1353,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
continue;
}
if (mapped_cell->type == ID($lut)) {
if (mapped_cell->type == TW($lut)) {
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = mapped_cell->parameters;
cell->attributes = mapped_cell->attributes;
@ -1554,7 +1554,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
log_assert(not_cell);
if (not_cell->type != ID($_NOT_))
if (not_cell->type != TW($_NOT_))
continue;
auto it = not2drivers.find(not_cell);
if (it == not2drivers.end())
@ -1572,7 +1572,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
goto clone_lut;
for (auto sink_cell : jt->second)
if (sink_cell->type != ID($lut))
if (sink_cell->type != TW($lut))
goto clone_lut;
// Push downstream LUTs past inverter
@ -1634,7 +1634,7 @@ static void replace_zbufs(Design *design)
for (auto mod : design->modules()) {
zbufs.clear();
for (auto cell : mod->cells()) {
if (cell->type != ID($buf))
if (cell->type != TW($buf))
continue;
auto &sig = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig); ++i) {
@ -1650,7 +1650,7 @@ static void replace_zbufs(Design *design)
for (int i = 0; i < GetSize(sig); ++i) {
if (sig[i] == State::Sz) {
Wire *w = mod->addWire(NEW_TWINE);
Cell *ud = mod->addCell(NEW_TWINE, ID($tribuf));
Cell *ud = mod->addCell(NEW_TWINE, TW($tribuf));
ud->set_bool_attribute(ID::aiger2_zbuf);
ud->setParam(ID::WIDTH, 1);
ud->setPort(TW::Y, w);
@ -1676,7 +1676,7 @@ static void restore_zbufs(Design *design)
for (auto mod : design->modules()) {
to_remove.clear();
for (auto cell : mod->cells())
if (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf)))
if (cell->type == TW($tribuf) && cell->has_attribute(ID(aiger2_zbuf)))
to_remove.push_back(cell);
for (auto cell : to_remove) {

8
passes/techmap/aigmap.cc
View file

@ -77,10 +77,10 @@ struct AigmapPass : public Pass {
{
Aig aig(cell);
if (cell->type.in(ID($_AND_), ID($_NOT_)))
if (cell->type.in(TW($_AND_), TW($_NOT_)))
aig.name.clear();
if (nand_mode && cell->type == ID($_NAND_))
if (nand_mode && cell->type == TW($_NAND_))
aig.name.clear();
if (aig.name.empty()) {
@ -157,14 +157,14 @@ struct AigmapPass : public Pass {
stat_replaced.sort();
log(" replaced %d cell types:\n", GetSize(stat_replaced));
for (auto &it : stat_replaced)
log("%8d %s\n", it.second, it.first.unescape());
log("%8d %s\n", it.second, design->twines.unescaped_str(it.first));
}
if (!stat_not_replaced.empty()) {
stat_not_replaced.sort();
log(" not replaced %d cell types:\n", GetSize(stat_not_replaced));
for (auto &it : stat_not_replaced)
log("%8d %s\n", it.second, it.first.unescape());
log("%8d %s\n", it.second, design->twines.unescaped_str(it.first));
}
for (auto cell : replaced_cells)

32
passes/techmap/alumacc.cc
View file

@ -153,10 +153,10 @@ struct AlumaccWorker
{
for (auto cell : module->selected_cells())
{
if (!cell->type.in(ID($pos), ID($neg), ID($add), ID($sub), ID($mul)))
if (!cell->type.in(TW($pos), TW($neg), TW($add), TW($sub), TW($mul)))
continue;
log(" creating $macc model for %s (%s).\n", cell, cell->type.unescape());
log(" creating $macc model for %s (%s).\n", cell, cell->type.unescaped());
maccnode_t *n = new maccnode_t;
Macc::term_t new_term;
@ -168,15 +168,15 @@ struct AlumaccWorker
for (auto bit : n->y)
n->users = max(n->users, bit_users.at(bit) - 1);
if (cell->type.in(ID($pos), ID($neg)))
if (cell->type.in(TW($pos), TW($neg)))
{
new_term.in_a = sigmap(cell->getPort(TW::A));
new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_term.do_subtract = cell->type == ID($neg);
new_term.do_subtract = cell->type == TW($neg);
n->macc.terms.push_back(new_term);
}
if (cell->type.in(ID($add), ID($sub)))
if (cell->type.in(TW($add), TW($sub)))
{
new_term.in_a = sigmap(cell->getPort(TW::A));
new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
@ -185,11 +185,11 @@ struct AlumaccWorker
new_term.in_a = sigmap(cell->getPort(TW::B));
new_term.is_signed = cell->getParam(ID::B_SIGNED).as_bool();
new_term.do_subtract = cell->type == ID($sub);
new_term.do_subtract = cell->type == TW($sub);
n->macc.terms.push_back(new_term);
}
if (cell->type.in(ID($mul)))
if (cell->type.in(TW($mul)))
{
new_term.in_a = sigmap(cell->getPort(TW::A));
new_term.in_b = sigmap(cell->getPort(TW::B));
@ -379,7 +379,7 @@ struct AlumaccWorker
for (auto &it : sig_macc)
{
auto n = it.second;
auto cell = module->addCell(NEW_TWINE, ID($macc));
auto cell = module->addCell(NEW_TWINE, TW($macc));
macc_counter++;
@ -404,18 +404,18 @@ struct AlumaccWorker
for (auto cell : module->selected_cells())
{
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt)))
if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt)))
lge_cells.push_back(cell);
if (cell->type.in(ID($eq), ID($eqx), ID($ne), ID($nex)))
if (cell->type.in(TW($eq), TW($eqx), TW($ne), TW($nex)))
eq_cells.push_back(cell);
}
for (auto cell : lge_cells)
{
log(" creating $alu model for %s (%s):", cell, cell->type.unescape());
log(" creating $alu model for %s (%s):", cell, cell->type.unescaped());
bool cmp_less = cell->type.in(ID($lt), ID($le));
bool cmp_equal = cell->type.in(ID($le), ID($ge));
bool cmp_less = cell->type.in(TW($lt), TW($le));
bool cmp_equal = cell->type.in(TW($le), TW($ge));
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(TW::A));
@ -460,7 +460,7 @@ struct AlumaccWorker
for (auto cell : eq_cells)
{
bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
bool cmp_equal = cell->type.in(TW($eq), TW($eqx));
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(TW::A));
@ -484,7 +484,7 @@ struct AlumaccWorker
}
if (n != nullptr) {
log(" creating $alu model for %s (%s): merged with %s.\n", cell, cell->type.unescape(), n->cells.front());
log(" creating $alu model for %s (%s): merged with %s.\n", cell, cell->type.unescaped(), n->cells.front());
n->cells.push_back(cell);
n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, false, Y));
}
@ -509,7 +509,7 @@ struct AlumaccWorker
goto delete_node;
}
n->alu_cell = module->addCell(NEW_TWINE, ID($alu));
n->alu_cell = module->addCell(NEW_TWINE, TW($alu));
alu_counter++;
log(" creating $alu cell for ");

12
passes/techmap/arith_tree.cc
View file

@ -30,7 +30,7 @@ struct Traversal {
Traversal(Module *module) : sigmap(module)
{
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
continue;
for (auto &conn : cell->connections())
if (cell->input(conn.first))
@ -53,11 +53,11 @@ struct Cells {
pool<Cell *> alu;
pool<Cell *> macc;
static bool is_addsub(Cell *cell) { return cell->type == ID($add) || cell->type == ID($sub); }
static bool is_addsub(Cell *cell) { return cell->type == TW($add) || cell->type == TW($sub); }
static bool is_alu(Cell *cell) { return cell->type == ID($alu); }
static bool is_alu(Cell *cell) { return cell->type == TW($alu); }
static bool is_macc(Cell *cell) { return cell->type == ID($macc) || cell->type == ID($macc_v2); }
static bool is_macc(Cell *cell) { return cell->type == TW($macc) || cell->type == TW($macc_v2); }
bool empty() { return addsub.empty() && alu.empty() && macc.empty(); }
@ -196,7 +196,7 @@ struct Rewriter {
bool feeds_subtracted_port(Cell *child, Cell *parent)
{
bool parent_subtracts;
if (parent->type == ID($sub))
if (parent->type == TW($sub))
parent_subtracts = true;
else if (cells.is_alu(parent))
parent_subtracts = alu_info.is_subtract(parent);
@ -251,7 +251,7 @@ struct Rewriter {
SigSpec b = traversal.sigmap(cell->getPort(TW::B));
bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
bool b_sub = (cell->type == TW($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
// Only add operands not produced by other chain cells
if (!overlaps(a, chain_bits)) {

4
passes/techmap/attrmap.cc
View file

@ -131,13 +131,13 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
if (new_attr != attr)
log("Changed attribute on %s: %s=%s -> %s=%s\n", objname,
attr.first.unescape(), log_const(attr.second), new_attr.first.unescape(), log_const(new_attr.second));
attr.first.unescape(), log_const(attr.second), design->twines.unescaped_str(new_attr.first), log_const(new_attr.second));
new_attributes[new_attr.first] = new_attr.second;
if (0)
delete_this_attr:
log("Removed attribute on %s: %s=%s\n", objname, attr.first.unescape(), log_const(attr.second));
log("Removed attribute on %s: %s=%s\n", objname, design->twines.unescaped_str(attr.first), log_const(attr.second));
}
attributes.swap(new_attributes);

2
passes/techmap/attrmvcp.cc
View file

@ -121,7 +121,7 @@ struct AttrmvcpPass : public Pass {
for (auto bit : sigmap(wire))
if (net2cells.count(bit))
for (auto cell : net2cells.at(bit)) {
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", attr.first.unescape(), log_const(attr.second),
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", design->twines.unescaped_str(attr.first), log_const(attr.second),
module, wire, module, cell);
cell->attributes[attr.first] = attr.second;
did_something = true;

2
passes/techmap/bmuxmap.cc
View file

@ -56,7 +56,7 @@ struct BmuxmapPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
{
if (cell->type != ID($bmux))
if (cell->type != TW($bmux))
continue;
SigSpec sel = cell->getPort(TW::S);

4
passes/techmap/booth.cc
View file

@ -212,14 +212,14 @@ struct BoothPassWorker {
SigSpec A, B, Y;
bool is_signed;
if (cell->type == ID($mul)) {
if (cell->type == TW($mul)) {
A = cell->getPort(TW::A);
B = cell->getPort(TW::B);
Y = cell->getPort(TW::Y);
log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
is_signed = cell->getParam(ID::A_SIGNED).as_bool();
} else if (cell->type.in(ID($macc), ID($macc_v2))) {
} else if (cell->type.in(TW($macc), TW($macc_v2))) {
Macc macc;
macc.from_cell(cell);

14
passes/techmap/bufnorm.cc
View file

@ -277,7 +277,7 @@ struct BufnormPass : public Pass {
vector<Cell*> old_dup_buffers;
for (auto cell : module->cells())
{
if (!cell->type.in(ID($buf), ID($_BUF_)))
if (!cell->type.in(TW($buf), TW($_BUF_)))
continue;
SigSpec insig = cell->getPort(TW::A);
@ -380,7 +380,7 @@ struct BufnormPass : public Pass {
for (auto cell : module->cells())
{
if (cell->type.in(ID($buf), ID($_BUF_)))
if (cell->type.in(TW($buf), TW($_BUF_)))
continue;
for (auto &conn : cell->connections())
@ -409,7 +409,7 @@ struct BufnormPass : public Pass {
if (w->name.isPublic())
log(" directly driven by cell %s port %s: %s\n",
cell, conn.first.unescape(), w);
cell, design->twines.unescaped_str(conn.first), w);
for (auto bit : SigSpec(w))
mapped_bits[sigmap(bit)] = bit;
@ -488,12 +488,12 @@ struct BufnormPass : public Pass {
}
} else {
if (bits_mode) {
IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) : ID($_BUF_);
IdString celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) : TW($_BUF_);
for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
make_buffer_f(celltype, insig[i], outsig[i]);
} else {
IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) :
GetSize(outsig) == 1 ? ID($_BUF_) : ID($buf);
IdString celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) :
GetSize(outsig) == 1 ? TW($_BUF_) : TW($buf);
make_buffer_f(celltype, insig, outsig);
}
}
@ -519,7 +519,7 @@ struct BufnormPass : public Pass {
if (conn.second != newsig) {
log(" fixing input signal on cell %s port %s: %s\n",
cell, conn.first.unescape(), log_signal(newsig));
cell, design->twines.unescaped_str(conn.first), log_signal(newsig));
cell->setPort(conn.first, newsig);
count_updated_cellports++;
}

2
passes/techmap/bwmuxmap.cc
View file

@ -50,7 +50,7 @@ struct BwmuxmapPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
{
if (cell->type != ID($bwmux))
if (cell->type != TW($bwmux))
continue;
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);

2
passes/techmap/cellmatch.cc
View file

@ -95,7 +95,7 @@ bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
CellTypes ff_types;
ff_types.setup_stdcells_mem();
for (auto cell : m->cells()) {
if (ff_types.cell_known(cell->type)) {
if (ff_types.cell_known(cell->type_impl)) {
log("Ignoring module '%s' which isn't purely combinational.\n", m);
return false;
}

4
passes/techmap/deminout.cc
View file

@ -83,9 +83,9 @@ struct DeminoutPass : public Pass {
for (auto bit : sigmap(conn.second))
bits_used.insert(bit);
if (conn.first == ID::Y && cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_TBUF_), ID($tribuf)))
if (conn.first == ID::Y && cell->type.in(TW($mux), TW($pmux), TW($_MUX_), TW($_TBUF_), TW($tribuf)))
{
bool tribuf = cell->type.in(ID($_TBUF_), ID($tribuf));
bool tribuf = cell->type.in(TW($_TBUF_), TW($tribuf));
if (!tribuf) {
for (auto &c : cell->connections()) {

2
passes/techmap/demuxmap.cc
View file

@ -47,7 +47,7 @@ struct DemuxmapPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
{
if (cell->type != ID($demux))
if (cell->type != TW($demux))
continue;
SigSpec sel = cell->getPort(TW::S);

6
passes/techmap/dffinit.cc
View file

@ -123,14 +123,14 @@ struct DffinitPass : public Pass {
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
module, cell, it.second.unescape());
module, cell, design->twines.unescaped_str(it.second));
value.set(i, initval[i]);
}
if (highlow_mode && GetSize(value) != 0) {
if (GetSize(value) != 1)
log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
module, cell, it.second.unescape());
module, cell, design->twines.unescaped_str(it.second));
if (value[0] == State::S1)
value = Const(high_string);
else
@ -138,7 +138,7 @@ struct DffinitPass : public Pass {
}
if (value.size() != 0) {
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, it.second.unescape(),
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, design->twines.unescaped_str(it.second),
it.first.unescape(), log_signal(sig), log_signal(value));
cell->setParam(it.second, value);
}

8
passes/techmap/dfflegalize.cc
View file

@ -263,7 +263,7 @@ struct DffLegalizePass : public Pass {
}
void fail_ff(const FfData &ff, const char *reason) {
log_error("FF %s.%s (type %s) cannot be legalized: %s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name), ff.cell->type.unescape(), reason);
log_error("FF %s.%s (type %s) cannot be legalized: %s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(ff.cell->type), reason);
}
bool try_flip(FfData &ff, int supported_mask) {
@ -381,7 +381,7 @@ struct DffLegalizePass : public Pass {
if (ff.has_ce && !supported_cells[FF_ADFFE])
ff.unmap_ce();
log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name));
log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
log_assert(ff.width == 1);
ff.remove();
@ -600,7 +600,7 @@ struct DffLegalizePass : public Pass {
ff.unmap_ce();
if (ff.cell)
log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name));
log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
emulate_split_init_arst(ff);
return;
}
@ -752,7 +752,7 @@ struct DffLegalizePass : public Pass {
// The only hope left is breaking down to adlatch + dlatch + dlatch + mux.
if (ff.cell)
log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name));
log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
ff.remove();
emulate_split_init_arst(ff);

90
passes/techmap/dfflibmap.cc
View file

@ -55,31 +55,31 @@ static void logmap(IdString dff)
static void logmap_all()
{
logmap(ID($_DFF_N_));
logmap(ID($_DFF_P_));
logmap(TW($_DFF_N_));
logmap(TW($_DFF_P_));
logmap(ID($_DFF_NN0_));
logmap(ID($_DFF_NN1_));
logmap(ID($_DFF_NP0_));
logmap(ID($_DFF_NP1_));
logmap(ID($_DFF_PN0_));
logmap(ID($_DFF_PN1_));
logmap(ID($_DFF_PP0_));
logmap(ID($_DFF_PP1_));
logmap(TW($_DFF_NN0_));
logmap(TW($_DFF_NN1_));
logmap(TW($_DFF_NP0_));
logmap(TW($_DFF_NP1_));
logmap(TW($_DFF_PN0_));
logmap(TW($_DFF_PN1_));
logmap(TW($_DFF_PP0_));
logmap(TW($_DFF_PP1_));
logmap(ID($_DFFE_NN_));
logmap(ID($_DFFE_NP_));
logmap(ID($_DFFE_PN_));
logmap(ID($_DFFE_PP_));
logmap(TW($_DFFE_NN_));
logmap(TW($_DFFE_NP_));
logmap(TW($_DFFE_PN_));
logmap(TW($_DFFE_PP_));
logmap(ID($_DFFSR_NNN_));
logmap(ID($_DFFSR_NNP_));
logmap(ID($_DFFSR_NPN_));
logmap(ID($_DFFSR_NPP_));
logmap(ID($_DFFSR_PNN_));
logmap(ID($_DFFSR_PNP_));
logmap(ID($_DFFSR_PPN_));
logmap(ID($_DFFSR_PPP_));
logmap(TW($_DFFSR_NNN_));
logmap(TW($_DFFSR_NNP_));
logmap(TW($_DFFSR_NPN_));
logmap(TW($_DFFSR_NPP_));
logmap(TW($_DFFSR_PNN_));
logmap(TW($_DFFSR_PNP_));
logmap(TW($_DFFSR_PPN_));
logmap(TW($_DFFSR_PPP_));
}
static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std::string &data_name, bool &data_not_inverted, std::string &enable_name, bool &enable_not_inverted)
@ -504,7 +504,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
for (auto cell : module->cells()) {
if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0)
cell_list.push_back(cell);
if (cell->type == ID($_NOT_))
if (cell->type == TW($_NOT_))
notmap[sigmap(cell->getPort(TW::A))].insert(cell);
}
@ -660,31 +660,31 @@ struct DfflibmapPass : public Pass {
delete f;
}
find_cell(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
find_cell(merged.cells, TW($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
find_cell(merged.cells, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
find_cell(merged.cells, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
find_cell(merged.cells, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
find_cell(merged.cells, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
find_cell(merged.cells, TW($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
find_cell(merged.cells, TW($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
find_cell(merged.cells, TW($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
find_cell(merged.cells, TW($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
find_cell_sr(merged.cells, TW($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
log(" final dff cell mappings:\n");
logmap_all();

18
passes/techmap/extract.cc
View file

@ -155,12 +155,12 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
if (sel && !sel->selected(mod)) {
log(" Skipping module %s as it is not selected.\n", mod->name.unescape());
log(" Skipping module %s as it is not selected.\n", design->twines.unescaped_str(mod->name));
return false;
}
if (mod->processes.size() > 0) {
log(" Skipping module %s as it contains unprocessed processes.\n", mod->name.unescape());
log(" Skipping module %s as it contains unprocessed processes.\n", design->twines.unescaped_str(mod->name));
return false;
}
@ -626,7 +626,7 @@ struct ExtractPass : public Pass {
if (!mine_mode)
for (auto module : map->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + module->name.unescape();
std::string graph_name = "needle_" + design->twines.unescaped_str(module->name);
log("Creating needle graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports)) {
solver.addGraph(graph_name, mod_graph);
@ -637,7 +637,7 @@ struct ExtractPass : public Pass {
for (auto module : design->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "haystack_" + module->name.unescape();
std::string graph_name = "haystack_" + design->twines.unescaped_str(module->name);
log("Creating haystack graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) {
solver.addGraph(graph_name, mod_graph);
@ -654,8 +654,8 @@ struct ExtractPass : public Pass {
for (auto needle : needle_list)
for (auto &haystack_it : haystack_map) {
log("Solving for %s in %s.\n", ("needle_" + needle->name.unescape()), haystack_it.first);
solver.solve(results, "needle_" + needle->name.unescape(), haystack_it.first, false);
log("Solving for %s in %s.\n", ("needle_" + design->twines.unescaped_str(needle->name)), haystack_it.first);
solver.solve(results, "needle_" + design->twines.unescaped_str(needle->name), haystack_it.first, false);
}
log("Found %d matches.\n", GetSize(results));
@ -691,12 +691,12 @@ struct ExtractPass : public Pass {
for (auto &result: results)
{
log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
log(" primary match in %s:", haystack_map.at(result.graphId)->name.unescape());
log(" primary match in %s:", design->twines.unescaped_str(haystack_map.at(result.graphId)->name));
for (auto &node : result.nodes)
log(" %s", RTLIL::unescape_id(node.nodeId));
log("\n");
for (auto &it : result.matchesPerGraph)
log(" matches in %s: %d\n", haystack_map.at(it.first)->name.unescape(), it.second);
log(" matches in %s: %d\n", design->twines.unescaped_str(haystack_map.at(it.first)->name), it.second);
RTLIL::Module *mod = haystack_map.at(result.graphId);
std::set<RTLIL::Cell*> cells;
@ -717,7 +717,7 @@ struct ExtractPass : public Pass {
RTLIL::Module *newMod = new RTLIL::Module;
newMod->design = map;
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, haystack_map.at(result.graphId)->name.unescape(), result.totalMatchesAfterLimits);
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, design->twines.unescaped_str(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
map->add(newMod);
for (auto wire : wires) {

18
passes/techmap/extract_counter.cc
View file

@ -258,7 +258,7 @@ int counter_tryextract(
return 9;
Cell* count_mux = *y_loads.begin();
extract.count_mux = count_mux;
if(count_mux->type != ID($mux))
if(count_mux->type != TW($mux))
return 10;
if(!is_full_bus(aluy, index, cell, ID::Y, count_mux, ID::A))
return 11;
@ -287,9 +287,9 @@ int counter_tryextract(
Cell* overflow_cell = NULL;
for(auto c : muxsel_conns)
{
if(extract.count_is_up && c->type != ID($eq))
if(extract.count_is_up && c->type != TW($eq))
continue;
if(!extract.count_is_up && c->type != ID($logic_not))
if(!extract.count_is_up && c->type != TW($logic_not))
continue;
if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID::S, true))
continue;
@ -311,7 +311,7 @@ int counter_tryextract(
Cell* count_reg = muxload;
Cell* cemux = NULL;
RTLIL::SigSpec cey;
if(muxload->type == ID($mux))
if(muxload->type == TW($mux))
{
//This mux is probably a clock enable mux.
//Find our count register (should be our only load)
@ -349,9 +349,9 @@ int counter_tryextract(
extract.has_ce = false;
extract.count_reg = count_reg;
if(count_reg->type == ID($dff))
if(count_reg->type == TW($dff))
extract.has_reset = false;
else if(count_reg->type == ID($adff))
else if(count_reg->type == TW($adff))
{
if (!settings.allow_arst)
return 25;
@ -517,7 +517,7 @@ void counter_worker(
SigMap& sigmap = index.sigmap;
//Core of the counter must be an ALU
if (cell->type != ID($alu))
if (cell->type != TW($alu))
return;
//A input is the count value. Check if it has COUNT_EXTRACT set.
@ -611,7 +611,7 @@ void counter_worker(
}
//Get new cell name
string countname = string("$COUNTx$") + extract.rwire->name.unescape();
string countname = string("$COUNTx$") + design->twines.unescaped_str(extract.rwire->name);
//Wipe all of the old connections to the ALU
cell->unsetPort(TW::A);
@ -697,7 +697,7 @@ void counter_worker(
//Hook up any parallel outputs
for(auto load : extract.pouts)
{
log(" Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), load.port.unescape());
log(" Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(load.port));
}
if(extract.has_pout)
{

12
passes/techmap/extract_fa.cc
View file

@ -85,9 +85,9 @@ struct ExtractFaWorker
{
for (auto cell : module->selected_cells())
{
if (cell->type.in( ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
if (cell->type.in( TW($_BUF_), TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_),
TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_), TW($_MUX_), TW($_NMUX_),
TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)))
{
SigBit y = sigmap(SigBit(cell->getPort(TW::Y)));
log_assert(driver.count(y) == 0);
@ -293,7 +293,7 @@ struct ExtractFaWorker
for (auto it : driver)
{
if (it.second->type.in(ID($_BUF_), ID($_NOT_)))
if (it.second->type.in(TW($_BUF_), TW($_NOT_)))
continue;
SigBit root = it.first;
@ -394,7 +394,7 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_TWINE, ID($fa));
Cell *cell = module->addCell(NEW_TWINE, TW($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);
@ -501,7 +501,7 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_TWINE, ID($fa));
Cell *cell = module->addCell(NEW_TWINE, TW($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);

20
passes/techmap/extract_reduce.cc
View file

@ -58,9 +58,9 @@ struct ExtractReducePass : public Pass
inline bool IsRightType(Cell* cell, GateType gt)
{
return (cell->type == ID($_AND_) && gt == GateType::And) ||
(cell->type == ID($_OR_) && gt == GateType::Or) ||
(cell->type == ID($_XOR_) && gt == GateType::Xor);
return (cell->type == TW($_AND_) && gt == GateType::And) ||
(cell->type == TW($_OR_) && gt == GateType::Or) ||
(cell->type == TW($_XOR_) && gt == GateType::Xor);
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -124,11 +124,11 @@ struct ExtractReducePass : public Pass
GateType gt;
if (cell->type == ID($_AND_))
if (cell->type == TW($_AND_))
gt = GateType::And;
else if (cell->type == ID($_OR_))
else if (cell->type == TW($_OR_))
gt = GateType::Or;
else if (cell->type == ID($_XOR_))
else if (cell->type == TW($_XOR_))
gt = GateType::Xor;
else
continue;
@ -261,7 +261,7 @@ struct ExtractReducePass : public Pass
SigSpec input;
for (auto it : sources) {
bool cond;
if (head_cell->type == ID($_XOR_))
if (head_cell->type == TW($_XOR_))
cond = it.second & 1;
else
cond = it.second != 0;
@ -269,11 +269,11 @@ struct ExtractReducePass : public Pass
input.append(it.first);
}
if (head_cell->type == ID($_AND_)) {
if (head_cell->type == TW($_AND_)) {
module->addReduceAnd(NEW_TWINE, input, output);
} else if (head_cell->type == ID($_OR_)) {
} else if (head_cell->type == TW($_OR_)) {
module->addReduceOr(NEW_TWINE, input, output);
} else if (head_cell->type == ID($_XOR_)) {
} else if (head_cell->type == TW($_XOR_)) {
module->addReduceXor(NEW_TWINE, input, output);
} else {
log_assert(false);

4
passes/techmap/extractinv.cc
View file

@ -100,7 +100,7 @@ struct ExtractinvPass : public Pass {
continue;
SigSpec sig = port.second;
if (it2->second.size() != sig.size())
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", module->name.unescape(), cell->type.unescape(), port.first.unescape(), param_name.unescape());
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", design->twines.unescaped_str(module->name), cell->type.unescaped(), design->twines.unescaped_str(port.first), design->twines.unescaped_str(param_name));
RTLIL::Const invmask = it2->second;
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
@ -111,7 +111,7 @@ struct ExtractinvPass : public Pass {
RTLIL::Cell *icell = module->addCell(NEW_TWINE, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescape(), port.first.unescape(), i);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescaped(), design->twines.unescaped_str(port.first), i);
sig[i] = SigBit(iwire, i);
}
cell->setPort(port.first, sig);

6
passes/techmap/flowmap.cc
View file

@ -674,8 +674,8 @@ struct FlowmapWorker
labels[node] = -1;
for (auto input : inputs)
{
if (input.wire->attributes.count(ID($flowmap_level)))
labels[input] = input.wire->attributes[ID($flowmap_level)].as_int();
if (input.wire->attributes.count(TW($flowmap_level)))
labels[input] = input.wire->attributes[TW($flowmap_level)].as_int();
else
labels[input] = 0;
}
@ -1590,7 +1590,7 @@ struct FlowmapPass : public Pass {
}
else
{
cell_types = {ID($_NOT_), ID($_AND_), ID($_OR_), ID($_XOR_), ID($_MUX_)};
cell_types = {TW($_NOT_), TW($_AND_), TW($_OR_), TW($_XOR_), TW($_MUX_)};
}
const char *algo_r = relax ? "-r" : "";

2
passes/techmap/insbuf.cc
View file

@ -44,7 +44,7 @@ struct InsbufPass : public Pass {
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
IdString celltype = TW($_BUF_), in_portname = ID::A, out_portname = ID::Y;
bool chain_mode = false;
size_t argidx;

8
passes/techmap/iopadmap.cc
View file

@ -253,7 +253,7 @@ struct IopadmapPass : public Pass {
// Gather tristate buffers and always-on drivers.
for (auto cell : module->cells())
if (cell->type == ID($_TBUF_)) {
if (cell->type == TW($_TBUF_)) {
SigBit bit = cell->getPort(TW::Y).as_bit();
tbuf_bits[bit] = cell;
} else {
@ -436,7 +436,7 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
module->uniquify(stringf("$iopadmap$%s.%s", design->twines.unescaped_str(module->name), design->twines.unescaped_str(wire->name))),
RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
@ -452,7 +452,7 @@ struct IopadmapPass : public Pass {
else
{
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
module->uniquify(stringf("$iopadmap$%s.%s", design->twines.unescaped_str(module->name), design->twines.unescaped_str(wire->name))),
RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
@ -468,7 +468,7 @@ struct IopadmapPass : public Pass {
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(wire->name.unescape());
cell->parameters[RTLIL::escape_id(nameparam)] = design->twines.unescaped_str(RTLIL::Const(wire->name));
cell->attributes[ID::keep] = RTLIL::Const(1);
}

2
passes/techmap/lut2bmux.cc
View file

@ -43,7 +43,7 @@ struct Lut2BmuxPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) {
if (cell->type == ID($lut)) {
if (cell->type == TW($lut)) {
cell->type_impl = TW::$bmux;
cell->setPort(TW::S, cell->getPort(TW::A));
cell->setPort(TW::A, cell->getParam(ID::LUT));

4
passes/techmap/lut2mux.cc
View file

@ -94,10 +94,10 @@ struct Lut2muxPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) {
if (cell->type == ID($lut)) {
if (cell->type == TW($lut)) {
IdString cell_name = cell->name;
int count = lut2mux(cell, word_mode);
log("Converted %s.%s to %d MUX cells.\n", module, cell_name.unescape(), count);
log("Converted %s.%s to %d MUX cells.\n", module, design->twines.unescaped_str(cell_name), count);
}
}
}

8
passes/techmap/maccmap.cc
View file

@ -111,7 +111,7 @@ struct MaccmapWorker
RTLIL::Wire *w1 = module->addWire(NEW_TWINE, width);
RTLIL::Wire *w2 = module->addWire(NEW_TWINE, width);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($fa));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW($fa));
cell->setParam(ID::WIDTH, width);
cell->setPort(TW::A, in1);
cell->setPort(TW::B, in2);
@ -237,7 +237,7 @@ struct MaccmapWorker
}
RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($alu));
RTLIL::Cell *c = module->addCell(NEW_TWINE, TW($alu));
c->setPort(TW::A, summands.front());
c->setPort(TW::B, summands.back());
c->setPort(TW::CI, State::S0);
@ -403,8 +403,8 @@ struct MaccmapPass : public Pass {
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
if (cell->type.in(ID($macc), ID($macc_v2))) {
log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescape());
if (cell->type.in(TW($macc), TW($macc_v2))) {
log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescaped());
maccmap(mod, cell, unmap_mode);
mod->remove(cell);
}

12
passes/techmap/muxcover.cc
View file

@ -116,12 +116,12 @@ struct MuxcoverWorker
if (!cell->input(conn.first))
continue;
for (auto bit : sigmap(conn.second)) {
if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID::S)
if (used_once.count(bit) || cell->type != TW($_MUX_) || conn.first == ID::S)
roots.insert(bit);
used_once.insert(bit);
}
}
if (cell->type == ID($_MUX_))
if (cell->type == TW($_MUX_))
sig_to_mux[sigmap(cell->getPort(TW::Y))] = cell;
}
@ -513,7 +513,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++;
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX_));
Cell *cell = module->addCell(NEW_TWINE, TW($_MUX_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::S, mux.selects[0]);
@ -523,7 +523,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++;
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX4_));
Cell *cell = module->addCell(NEW_TWINE, TW($_MUX4_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::C, mux.inputs[2]);
@ -536,7 +536,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++;
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX8_));
Cell *cell = module->addCell(NEW_TWINE, TW($_MUX8_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::C, mux.inputs[2]);
@ -554,7 +554,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++;
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX16_));
Cell *cell = module->addCell(NEW_TWINE, TW($_MUX16_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::C, mux.inputs[2]);

4
passes/techmap/nlutmap.cc
View file

@ -82,7 +82,7 @@ struct NlutmapWorker
for (auto cell : module->cells())
{
if (cell->type != ID($lut) || mapped_cells.count(cell))
if (cell->type != TW($lut) || mapped_cells.count(cell))
continue;
if (GetSize(cell->getPort(TW::A)) == lut_size || lut_size == 2)
@ -119,7 +119,7 @@ struct NlutmapWorker
if (config.assert_mode) {
for (auto cell : module->cells())
if (cell->type == ID($lut) && !mapped_cells.count(cell))
if (cell->type == TW($lut) && !mapped_cells.count(cell))
log_error("Insufficient number of LUTs to map all logic cells!\n");
}

2
passes/techmap/pmuxtree.cc
View file

@ -89,7 +89,7 @@ struct PmuxtreePass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
{
if (cell->type != ID($pmux))
if (cell->type != TW($pmux))
continue;
SigSpec sig_data = cell->getPort(TW::B);

24
passes/techmap/shregmap.cc
View file

@ -319,13 +319,13 @@ struct ShregmapWorker
int param_clkpol = -1;
int param_enpol = 2;
if (first_cell->type == ID($_DFF_N_)) param_clkpol = 0;
if (first_cell->type == ID($_DFF_P_)) param_clkpol = 1;
if (first_cell->type == TW($_DFF_N_)) param_clkpol = 0;
if (first_cell->type == TW($_DFF_P_)) param_clkpol = 1;
if (first_cell->type == ID($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
if (first_cell->type == ID($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
if (first_cell->type == ID($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
if (first_cell->type == TW($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
if (first_cell->type == TW($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
if (first_cell->type == TW($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
if (first_cell->type == TW($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
log_assert(param_clkpol >= 0);
first_cell->setParam(ID(CLKPOL), param_clkpol);
@ -519,19 +519,19 @@ struct ShregmapPass : public Pass {
bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
if (clk_pos && en_none)
opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_none)
opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_pos && en_pos)
opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_pos && en_neg)
opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_pos)
opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_neg)
opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (en_pos || en_neg)
opts.ffe = true;

154
passes/techmap/simplemap.cc
View file

@ -40,7 +40,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_NOT_));
transfer_src(gate, cell);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::Y, sig_y[i]);
@ -86,17 +86,17 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (cell->type != ID($bweqx)) {
if (cell->type != TW($bweqx)) {
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
}
IdString gate_type;
if (cell->type == ID($and)) gate_type = ID($_AND_);
if (cell->type == ID($or)) gate_type = ID($_OR_);
if (cell->type == ID($xor)) gate_type = ID($_XOR_);
if (cell->type == ID($xnor)) gate_type = ID($_XNOR_);
if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_);
if (cell->type == TW($and)) gate_type = TW($_AND_);
if (cell->type == TW($or)) gate_type = TW($_OR_);
if (cell->type == TW($xor)) gate_type = TW($_XOR_);
if (cell->type == TW($xnor)) gate_type = TW($_XNOR_);
if (cell->type == TW($bweqx)) gate_type = TW($_XNOR_);
log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) {
@ -117,11 +117,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
return;
if (sig_a.size() == 0) {
if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == TW($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == TW($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == TW($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == TW($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == TW($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
return;
}
@ -131,11 +131,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
IdString gate_type;
if (cell->type == ID($reduce_and)) gate_type = ID($_AND_);
if (cell->type == ID($reduce_or)) gate_type = ID($_OR_);
if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_);
if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_);
if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_);
if (cell->type == TW($reduce_and)) gate_type = TW($_AND_);
if (cell->type == TW($reduce_or)) gate_type = TW($_OR_);
if (cell->type == TW($reduce_xor)) gate_type = TW($_XOR_);
if (cell->type == TW($reduce_xnor)) gate_type = TW($_XOR_);
if (cell->type == TW($reduce_bool)) gate_type = TW($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *last_output_cell = NULL;
@ -162,9 +162,9 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
sig_a = sig_t;
}
if (cell->type == ID($reduce_xnor)) {
if (cell->type == TW($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_NOT_));
transfer_src(gate, cell);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::Y, sig_t);
@ -192,7 +192,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_OR_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_OR_));
transfer_src(gate, cell);
gate->setPort(TW::A, sig[i]);
gate->setPort(TW::B, sig[i+1]);
@ -221,7 +221,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1);
}
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_NOT_));
transfer_src(gate, cell);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::Y, sig_y);
@ -246,8 +246,8 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
}
IdString gate_type;
if (cell->type == ID($logic_and)) gate_type = ID($_AND_);
if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
if (cell->type == TW($logic_and)) gate_type = TW($_AND_);
if (cell->type == TW($logic_or)) gate_type = TW($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
@ -263,7 +263,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
bool is_ne = cell->type.in(TW($ne), TW($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_TWINE, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_TWINE, sig_a, sig_b, xor_out, is_signed);
@ -292,7 +292,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
transfer_src(gate, cell);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
@ -309,7 +309,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
transfer_src(gate, cell);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
@ -325,7 +325,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_TBUF_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_TBUF_));
transfer_src(gate, cell);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::E, sig_e);
@ -343,7 +343,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
transfer_src(gate, cell);
gate->setPort(TW::A, data[i*2+k]);
gate->setPort(TW::B, data[i*2+width+k]);
@ -366,7 +366,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec new_lut_data = module->addWire(NEW_TWINE, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, TW($_MUX_));
transfer_src(gate, cell);
gate->setPort(TW::A, lut_data[i]);
gate->setPort(TW::B, lut_data[i+1]);
@ -454,7 +454,7 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
// Implement: B_AND_BITS = B_AND_S[WIDTH*j+i]
for (int j = 0; j < s_width; j++) {
RTLIL::Cell *and_gate = module->addCell(NEW_TWINE, ID($_AND_));
RTLIL::Cell *and_gate = module->addCell(NEW_TWINE, TW($_AND_));
transfer_src(and_gate, cell);
and_gate->setPort(TW::A, sig_b[j * width + i]);
and_gate->setPort(TW::B, sig_s[j]);
@ -468,7 +468,7 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
logic_reduce(module, b_and_bits, cell);
// Implement: Y[i] = |S ? Y_B[i] : A[i]
RTLIL::Cell *mux_gate = module->addCell(NEW_TWINE, ID($_MUX_));
RTLIL::Cell *mux_gate = module->addCell(NEW_TWINE, TW($_MUX_));
transfer_src(mux_gate, cell);
mux_gate->setPort(TW::A, sig_a[i]);
mux_gate->setPort(TW::B, b_and_bits);
@ -479,51 +479,51 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
mappers[ID($not)] = simplemap_not;
mappers[ID($pos)] = simplemap_pos;
mappers[ID($buf)] = simplemap_buf;
mappers[ID($and)] = simplemap_bitop;
mappers[ID($or)] = simplemap_bitop;
mappers[ID($xor)] = simplemap_bitop;
mappers[ID($xnor)] = simplemap_bitop;
mappers[ID($bweqx)] = simplemap_bitop;
mappers[ID($reduce_and)] = simplemap_reduce;
mappers[ID($reduce_or)] = simplemap_reduce;
mappers[ID($reduce_xor)] = simplemap_reduce;
mappers[ID($reduce_xnor)] = simplemap_reduce;
mappers[ID($reduce_bool)] = simplemap_reduce;
mappers[ID($logic_not)] = simplemap_lognot;
mappers[ID($logic_and)] = simplemap_logbin;
mappers[ID($logic_or)] = simplemap_logbin;
mappers[ID($eq)] = simplemap_eqne;
mappers[ID($eqx)] = simplemap_eqne;
mappers[ID($ne)] = simplemap_eqne;
mappers[ID($nex)] = simplemap_eqne;
mappers[ID($mux)] = simplemap_mux;
mappers[ID($pmux)] = simplemap_pmux;
mappers[ID($bwmux)] = simplemap_bwmux;
mappers[ID($tribuf)] = simplemap_tribuf;
mappers[ID($bmux)] = simplemap_bmux;
mappers[ID($lut)] = simplemap_lut;
mappers[ID($sop)] = simplemap_sop;
mappers[ID($slice)] = simplemap_slice;
mappers[ID($concat)] = simplemap_concat;
mappers[ID($sr)] = simplemap_ff;
mappers[ID($ff)] = simplemap_ff;
mappers[ID($dff)] = simplemap_ff;
mappers[ID($dffe)] = simplemap_ff;
mappers[ID($dffsr)] = simplemap_ff;
mappers[ID($dffsre)] = simplemap_ff;
mappers[ID($adff)] = simplemap_ff;
mappers[ID($sdff)] = simplemap_ff;
mappers[ID($adffe)] = simplemap_ff;
mappers[ID($sdffe)] = simplemap_ff;
mappers[ID($sdffce)] = simplemap_ff;
mappers[ID($aldff)] = simplemap_ff;
mappers[ID($aldffe)] = simplemap_ff;
mappers[ID($dlatch)] = simplemap_ff;
mappers[ID($adlatch)] = simplemap_ff;
mappers[ID($dlatchsr)] = simplemap_ff;
mappers[TW($not)] = simplemap_not;
mappers[TW($pos)] = simplemap_pos;
mappers[TW($buf)] = simplemap_buf;
mappers[TW($and)] = simplemap_bitop;
mappers[TW($or)] = simplemap_bitop;
mappers[TW($xor)] = simplemap_bitop;
mappers[TW($xnor)] = simplemap_bitop;
mappers[TW($bweqx)] = simplemap_bitop;
mappers[TW($reduce_and)] = simplemap_reduce;
mappers[TW($reduce_or)] = simplemap_reduce;
mappers[TW($reduce_xor)] = simplemap_reduce;
mappers[TW($reduce_xnor)] = simplemap_reduce;
mappers[TW($reduce_bool)] = simplemap_reduce;
mappers[TW($logic_not)] = simplemap_lognot;
mappers[TW($logic_and)] = simplemap_logbin;
mappers[TW($logic_or)] = simplemap_logbin;
mappers[TW($eq)] = simplemap_eqne;
mappers[TW($eqx)] = simplemap_eqne;
mappers[TW($ne)] = simplemap_eqne;
mappers[TW($nex)] = simplemap_eqne;
mappers[TW($mux)] = simplemap_mux;
mappers[TW($pmux)] = simplemap_pmux;
mappers[TW($bwmux)] = simplemap_bwmux;
mappers[TW($tribuf)] = simplemap_tribuf;
mappers[TW($bmux)] = simplemap_bmux;
mappers[TW($lut)] = simplemap_lut;
mappers[TW($sop)] = simplemap_sop;
mappers[TW($slice)] = simplemap_slice;
mappers[TW($concat)] = simplemap_concat;
mappers[TW($sr)] = simplemap_ff;
mappers[TW($ff)] = simplemap_ff;
mappers[TW($dff)] = simplemap_ff;
mappers[TW($dffe)] = simplemap_ff;
mappers[TW($dffsr)] = simplemap_ff;
mappers[TW($dffsre)] = simplemap_ff;
mappers[TW($adff)] = simplemap_ff;
mappers[TW($sdff)] = simplemap_ff;
mappers[TW($adffe)] = simplemap_ff;
mappers[TW($sdffe)] = simplemap_ff;
mappers[TW($sdffce)] = simplemap_ff;
mappers[TW($aldff)] = simplemap_ff;
mappers[TW($aldffe)] = simplemap_ff;
mappers[TW($dlatch)] = simplemap_ff;
mappers[TW($adlatch)] = simplemap_ff;
mappers[TW($dlatchsr)] = simplemap_ff;
}
void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
@ -577,7 +577,7 @@ struct SimplemapPass : public Pass {
continue;
if (!design->selected(mod, cell))
continue;
log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescape());
log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescaped());
mappers.at(cell->type)(mod, cell);
mod->remove(cell);
}

82
passes/techmap/techmap.cc
View file

@ -93,17 +93,17 @@ struct TechmapWorker
RTLIL::SigBit bit = sigmap(conn.second[i]);
if (bit.wire == nullptr) {
if (verbose)
log(" Constant input on bit %d of port %s: %s\n", i, conn.first.unescape(), log_signal(bit));
constmap_info += stringf("|%s %d %d", conn.first.unescape(), i, bit.data);
log(" Constant input on bit %d of port %s: %s\n", i, design->twines.unescaped_str(conn.first), log_signal(bit));
constmap_info += stringf("|%s %d %d", design->twines.unescaped_str(conn.first), i, bit.data);
} else if (connbits_map.count(bit)) {
if (verbose)
log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, conn.first.unescape(),
connbits_map.at(bit).second, connbits_map.at(bit).first.unescape());
constmap_info += stringf("|%s %d %s %d", conn.first.unescape(), i,
log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, design->twines.unescaped_str(conn.first),
connbits_map.at(bit).second, design->twines.unescaped_str(connbits_map.at(bit).first));
constmap_info += stringf("|%s %d %s %d", design->twines.unescaped_str(conn.first), i,
connbits_map.at(bit).first.unescape(), connbits_map.at(bit).second);
} else {
connbits_map.emplace(bit, std::make_pair(conn.first, i));
constmap_info += stringf("|%s %d", conn.first.unescape(), i);
constmap_info += stringf("|%s %d", design->twines.unescaped_str(conn.first), i);
}
}
@ -146,7 +146,7 @@ struct TechmapWorker
if (tpl->processes.size() != 0) {
log("Technology map yielded processes:");
for (auto &it : tpl->processes)
log(" %s",it.first.unescape());
log(" design->twines.unescaped_str(%s",it.first));
log("\n");
if (autoproc_mode) {
Pass::call_on_module(tpl->design, tpl, "proc");
@ -440,7 +440,7 @@ struct TechmapWorker
if (celltypeMap.count(cell->type) == 0) {
if (assert_mode && !cell->type.ends_with("_"))
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", cell->type.unescape());
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", cell->type.unescaped());
continue;
}
@ -503,10 +503,10 @@ struct TechmapWorker
{
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{
std::string m_name = stringf("$extern:%s:%s", extmapper_name, cell->type.unescape());
std::string m_name = stringf("$extern:%s:%s", extmapper_name, cell->type.unescaped());
for (auto &c : cell->parameters)
m_name += stringf(":%s=%s", c.first.unescape(), log_signal(c.second));
m_name += stringf(":%s=%s", design->twines.unescaped_str(c.first), log_signal(c.second));
if (extmapper_name == "wrap")
m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
@ -539,15 +539,15 @@ struct TechmapWorker
if (extmapper_name == "simplemap") {
log("Creating %s with simplemap.\n", extmapper_module);
if (simplemap_mappers.count(extmapper_cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", extmapper_cell->type.unescape());
log_error("No simplemap mapper for cell type %s found!\n", design->twines.unescaped_str(extmapper_cell->type));
simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell);
}
if (extmapper_name == "maccmap") {
log("Creating %s with maccmap.\n", extmapper_module);
if (!extmapper_cell->type.in(ID($macc), ID($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", extmapper_cell->type.unescape());
if (!extmapper_cell->type.in(TW($macc), TW($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", design->twines.unescaped_str(extmapper_cell->type));
maccmap(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell);
}
@ -570,31 +570,31 @@ struct TechmapWorker
goto use_wrapper_tpl;
}
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_module, cell->type.unescape());
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_module, cell->type.unescaped());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_module);
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), extmapper_module);
}
else
{
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, cell->type.unescape());
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, cell->type.unescaped());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_name);
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), extmapper_name);
if (extmapper_name == "simplemap") {
if (simplemap_mappers.count(cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", cell->type.unescape());
log_error("No simplemap mapper for cell type %s found!\n", cell->type.unescaped());
simplemap_mappers.at(cell->type)(module, cell);
}
if (extmapper_name == "maccmap") {
if (!cell->type.in(ID($macc), ID($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", cell->type.unescape());
if (!cell->type.in(TW($macc), TW($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", cell->type.unescaped());
maccmap(module, cell);
}
@ -623,26 +623,26 @@ struct TechmapWorker
}
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescape());
parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescaped());
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0)
parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->module->design->twines.str(cell->meta_->name));
for (auto &conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", design->twines.unescaped_str(conn.first))) != 0) {
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
for (auto &bit : v)
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", design->twines.unescaped_str(conn.first)), RTLIL::SigSpec(v).as_const());
}
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", design->twines.unescaped_str(conn.first))) != 0) {
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
for (auto &bit : v)
if (bit.wire != nullptr)
bit = RTLIL::SigBit(RTLIL::State::Sx);
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", design->twines.unescaped_str(conn.first)), RTLIL::SigSpec(v).as_const());
}
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape())) != 0) {
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape()), initvals(conn.second));
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", design->twines.unescaped_str(conn.first))) != 0) {
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", design->twines.unescaped_str(conn.first)), initvals(conn.second));
}
}
@ -655,7 +655,7 @@ struct TechmapWorker
unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first))) != 0) {
for (auto &bit : sigmap(conn.second))
if (unique_bit_id.count(bit) == 0)
unique_bit_id[bit] = unique_bit_id_counter++;
@ -672,7 +672,7 @@ struct TechmapWorker
parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first))) != 0) {
SigSpec sm = sigmap(conn.second);
RTLIL::Const::Builder builder(GetSize(sm) * bits);
for (auto &bit : sm) {
@ -682,7 +682,7 @@ struct TechmapWorker
val = val >> 1;
}
}
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape()), builder.build());
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", design->twines.unescaped_str(conn.first)), builder.build());
}
}
@ -731,7 +731,7 @@ struct TechmapWorker
RTLIL::SigSpec value = elem.value;
if (value.is_fully_const() && value.as_bool()) {
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
derived_name.c_str(), elem.wire->name.unescape(), log_signal(value));
derived_name.c_str(), design->twines.unescaped_str(elem.wire->name), log_signal(value));
techmap_do_cache[tpl] = false;
}
}
@ -748,7 +748,7 @@ struct TechmapWorker
auto &data = it.second.front();
if (!data.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", data.wire->name.unescape(), log_signal(data.value));
log_error("Techmap yielded config wire %s with non-const value %s.\n", design->twines.unescaped_str(data.wire->name), log_signal(data.value));
techmap_wire_names.erase(it.first);
@ -765,7 +765,7 @@ struct TechmapWorker
log("Analyzing pattern of constant bits for this cell:\n");
IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
log("Creating constmapped module `%s'.\n", new_tpl_name.unescape());
log("Creating constmapped module `%s'.\n", design->twines.unescaped_str(new_tpl_name));
log_assert(map->module(new_tpl_name) == nullptr);
RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
@ -873,16 +873,16 @@ struct TechmapWorker
TechmapWires twd = techmap_find_special_wires(tpl);
for (auto &it : twd) {
if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_"))
log_error("Techmap yielded unknown config wire %s.\n", it.first.unescape());
log_error("Techmap yielded unknown config wire %s.\n", design->twines.unescaped_str(it.first));
if (techmap_do_cache[tpl])
for (auto &it2 : it.second)
if (!it2.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", it2.wire->name.unescape(), log_signal(it2.value));
log_error("Techmap yielded config wire %s with non-const value %s.\n", design->twines.unescaped_str(it2.wire->name), log_signal(it2.value));
techmap_wire_names.erase(it.first);
}
for (auto &it : techmap_wire_names)
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", it.unescape());
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", design->twines.unescaped_str(it));
if (recursive_mode) {
if (log_continue) {
@ -938,12 +938,12 @@ struct TechmapWorker
}
else
{
auto msg = stringf("Using template %s for cells of type %s.", tpl, cell->type.unescape());
auto msg = stringf("Using template %s for cells of type %s.", tpl, cell->type.unescaped());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), tpl);
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, module, cell, cell->type.unescaped(), tpl);
techmap_module_worker(design, module, cell, tpl);
cell = nullptr;
}
@ -953,7 +953,7 @@ struct TechmapWorker
}
if (assert_mode && !mapped_cell)
log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", module, cell, cell->type.unescape());
log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", module, cell, cell->type.unescaped());
handled_cells.insert(cell);
}
@ -1275,8 +1275,8 @@ struct TechmapPass : public Pass {
i.second.sort(RTLIL::sort_by_id_str());
std::string maps = "";
for (auto &map : i.second)
maps += stringf(" %s", map.unescape());
log_debug(" %s:%s\n", i.first.unescape(), maps);
maps += stringf(" %s", design->twines.unescaped_str(map));
log_debug(" %s:%s\n", design->twines.unescaped_str(i.first), maps);
}
log_debug("\n");

16
passes/techmap/tribuf.cc
View file

@ -65,16 +65,16 @@ struct TribufWorker {
for (auto cell : module->selected_cells())
{
if (cell->type == ID($tribuf))
if (cell->type == TW($tribuf))
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
if (cell->type == ID($_TBUF_))
if (cell->type == TW($_TBUF_))
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
if (cell->type.in(ID($mux), ID($_MUX_)))
if (cell->type.in(TW($mux), TW($_MUX_)))
{
IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E;
IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
IdString en_port = cell->type == TW($mux) ? ID::EN : ID::E;
IdString tri_type = cell->type == TW($mux) ? TW($tribuf) : TW($_TBUF_);
if (is_all_z(cell->getPort(TW::A)) && is_all_z(cell->getPort(TW::B))) {
module->remove(cell);
@ -130,13 +130,13 @@ struct TribufWorker {
for (auto other_cell : it.second) {
if (other_cell == cell)
continue;
else if (other_cell->type == ID($tribuf))
else if (other_cell->type == TW($tribuf))
others_s.append(other_cell->getPort(TW::EN));
else
others_s.append(other_cell->getPort(TW::E));
}
auto cell_s = cell->type == ID($tribuf) ? cell->getPort(TW::EN) : cell->getPort(TW::E);
auto cell_s = cell->type == TW($tribuf) ? cell->getPort(TW::EN) : cell->getPort(TW::E);
auto other_s = module->ReduceOr(NEW_TWINE, others_s);
@ -154,7 +154,7 @@ struct TribufWorker {
SigSpec pmux_b, pmux_s;
for (auto cell : it.second) {
if (cell->type == ID($tribuf))
if (cell->type == TW($tribuf))
pmux_s.append(cell->getPort(TW::EN));
else
pmux_s.append(cell->getPort(TW::E));

2
passes/techmap/zinit.cc
View file

@ -68,7 +68,7 @@ struct ZinitPass : public Pass {
FfData ff(&initvals, cell);
log("FF init value for cell %s (%s): %s = %s\n", cell, cell->type.unescape(),
log("FF init value for cell %s (%s): %s = %s\n", cell, cell->type.unescaped(),
log_signal(ff.sig_q), log_signal(ff.val_init));
pool<int> bits;