mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-25 00:22:34 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/sat/synthprop.cc
View file

@ -64,7 +64,7 @@ void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &traci
tracing_data[mod] = TrackingItem();
int cnt = 0;
for (auto cell : mod->cells()) {
if (cell->type == ID($assert)) {
if (cell->type == TW($assert)) {
log("%*sFound assert %s..\n", 2*(depth+1), "", cell);
tracing_data[mod].assertion_cells.emplace(cell);
if (!or_outputs) {
@ -93,7 +93,7 @@ void SynthPropWorker::run()
log_error("Module is not TOP module\n");
TrackingData tracing_data;
tracing(module, 0, tracing_data, module->name.unescape());
tracing(module, 0, tracing_data, design->twines.unescaped_str(module->name));
for (auto &data : tracing_data) {
if (data.second.names.size() == 0) continue;
@ -112,7 +112,7 @@ void SynthPropWorker::run()
}
pool<Wire*> connected;
for (auto cell : data.second.assertion_cells) {
if (cell->type == ID($assert)) {
if (cell->type == TW($assert)) {
RTLIL::Wire *neg_wire = data.first->addWire(NEW_TWINE);
RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE);
data.first->addNot(NEW_ID, cell->getPort(TW::A), neg_wire);