mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-23 15:42:32 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -250,7 +250,7 @@ struct SimInstance
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if (module->get_blackbox_attribute(true))
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log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
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module->name.unescape(), hiername().c_str());
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design->twines.unescaped_str(module->name), hiername().c_str());
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if (module->has_processes())
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log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
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@ -275,9 +275,9 @@ struct SimInstance
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}
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if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
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fstHandle id = shared->fst->getHandle(scope + "." + wire->name.unescape());
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fstHandle id = shared->fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
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if (id==0 && wire->name.isPublic())
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log_warning("Unable to find wire %s in input file.\n", (scope + "." + wire->name.unescape()));
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log_warning("Unable to find wire %s in input file.\n", (scope + "." + design->twines.unescaped_str(wire->name)));
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fst_handles[wire] = id;
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}
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@ -329,7 +329,7 @@ struct SimInstance
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}
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}
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if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
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if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
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FfData ff_data(nullptr, cell);
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ff_state_t ff;
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ff.past_d = Const(State::Sx, ff_data.width);
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@ -354,13 +354,13 @@ struct SimInstance
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fst_memories[name] = shared->fst->getMemoryHandles(scope + "." + RTLIL::unescape_id(name));
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}
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if (cell->type.in(ID($assert), ID($cover), ID($assume)))
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if (cell->type.in(TW($assert), TW($cover), TW($assume)))
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formal_database.insert(cell);
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if (cell->type == ID($initstate))
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if (cell->type == TW($initstate))
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initstate_database.insert(cell);
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if (cell->type == ID($print)) {
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if (cell->type == TW($print)) {
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print_database.emplace_back();
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auto &print = print_database.back();
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print.cell = cell;
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@ -413,7 +413,7 @@ struct SimInstance
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std::string hiername() const
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{
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if (instance != nullptr)
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return parent->hiername() + "." + instance->name.unescape();
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return parent->hiername() + "." + design->twines.unescaped_str(instance->name);
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return module->design->twines.str(module->meta_->name);
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}
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@ -520,7 +520,7 @@ struct SimInstance
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{
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auto &state = mem_database[memid];
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if (offset >= state.mem->size * state.mem->width)
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log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, memid.unescape());
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log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, design->twines.unescaped_str(memid));
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if (state.data[offset] != data) {
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state.data.set(offset, data);
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dirty_memories.insert(memid);
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@ -573,7 +573,7 @@ struct SimInstance
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if (has_y) sig_y = cell->getPort(TW::Y);
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if (shared->debug)
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log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescape());
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log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescaped());
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bool err = false;
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RTLIL::Const eval_state;
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@ -593,19 +593,19 @@ struct SimInstance
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err = true;
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if (err)
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log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
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log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
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else
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set_state(sig_y, eval_state);
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return;
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}
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if (cell->type == ID($print))
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if (cell->type == TW($print))
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return;
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if (cell->type.in(ID($input_port), ID($output_port), ID($public), ID($connect)))
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if (cell->type.in(TW($input_port), TW($output_port), TW($public), TW($connect)))
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return;
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log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
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log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
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}
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void update_memory(IdString id) {
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@ -619,7 +619,7 @@ struct SimInstance
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Const data = Const(State::Sx, mem.width << port.wide_log2);
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if (port.clk_enable)
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log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, mem.memid.unescape());
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log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, design->twines.unescaped_str(mem.memid));
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if (addr.is_fully_def()) {
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int addr_int = addr.as_int();
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@ -937,17 +937,17 @@ struct SimInstance
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State a = get_state(cell->getPort(TW::A))[0];
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State en = get_state(cell->getPort(TW::EN))[0];
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if (en == State::S1 && (cell->type == ID($cover) ? a == State::S1 : a != State::S1)) {
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if (en == State::S1 && (cell->type == TW($cover) ? a == State::S1 : a != State::S1)) {
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shared->triggered_assertions.emplace_back(shared->step, this, cell);
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}
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if (cell->type == ID($cover) && en == State::S1 && a == State::S1)
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if (cell->type == TW($cover) && en == State::S1 && a == State::S1)
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log("Cover %s.%s (%s) reached.\n", hiername(), cell, label);
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if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
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if (cell->type == TW($assume) && en == State::S1 && a != State::S1)
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log("Assumption %s.%s (%s) failed.\n", hiername(), cell, label);
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if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
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if (cell->type == TW($assert) && en == State::S1 && a != State::S1) {
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log_cell_w_hierarchy("Failed assertion", cell);
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if (shared->serious_asserts)
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log_error("Assertion %s.%s (%s) failed.\n", hiername(), cell, label);
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@ -1085,7 +1085,7 @@ struct SimInstance
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for (auto name : hdlname)
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enter_scope("\\" + name);
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} else {
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signal_name = memid.unescape();
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signal_name = design->twines.unescaped_str(memid);
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}
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for (auto &trace_index : trace_mem.second) {
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@ -1199,7 +1199,7 @@ struct SimInstance
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{
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($anyseq))) {
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if (cell->type.in(TW($anyseq))) {
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SigSpec sig_y = sigmap(cell->getPort(TW::Y));
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if (sig_y.is_wire()) {
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bool found = false;
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@ -1212,7 +1212,7 @@ struct SimInstance
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}
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}
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if (!found)
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + sig_y.as_wire()->name.unescape()));
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(sig_y.as_wire()->name)));
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}
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}
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}
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@ -1412,7 +1412,7 @@ struct SimWorker : SimShared
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Wire *w = top->module->wire(portname);
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if (w == nullptr)
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log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
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log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
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top->set_state(w, value);
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}
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@ -1495,24 +1495,24 @@ struct SimWorker : SimShared
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
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log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
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fstHandle id = fst->getHandle(scope + "." + portname.unescape());
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log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
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fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
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log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
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fst_clock.push_back(id);
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}
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for (auto portname : clockn)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
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log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
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fstHandle id = fst->getHandle(scope + "." + portname.unescape());
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log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
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fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
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log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
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fst_clock.push_back(id);
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}
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@ -1520,9 +1520,9 @@ struct SimWorker : SimShared
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for (auto wire : topmod->wires()) {
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if (wire->port_input) {
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fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
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fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
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if (id==0)
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
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top->fst_inputs[wire] = id;
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}
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}
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@ -1837,7 +1837,7 @@ struct SimWorker : SimShared
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Cell *c = topmod->cell(found);
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if (!c)
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log_warning("Wire/cell %s not present in module %s\n", unescaped_s, topmod);
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else if (c->type.in(ID($anyconst), ID($anyseq))) {
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else if (c->type.in(TW($anyconst), TW($anyseq))) {
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SigSpec sig_y= c->getPort(TW::Y);
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if ((int)parts[1].size() != GetSize(sig_y))
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log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y));
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@ -2084,13 +2084,13 @@ struct SimWorker : SimShared
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json.entry("version", "Yosys sim summary");
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json.entry("generator", yosys_maybe_version());
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json.entry("steps", step);
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json.entry("top", top->module->name.unescape());
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json.entry("top", design->twines.unescaped_str(top->module->name));
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json.name("assertions");
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json.begin_array();
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for (auto &assertion : triggered_assertions) {
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json.begin_object();
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json.entry("step", assertion.step);
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json.entry("type", assertion.cell->type.unescape());
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json.entry("type", design->twines.unescaped_str(assertion.cell->type));
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json.entry("path", assertion.instance->witness_full_path(assertion.cell));
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auto src = assertion.cell->get_src_attribute();
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if (!src.empty()) {
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@ -2155,12 +2155,12 @@ struct SimWorker : SimShared
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
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log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
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fstHandle id = fst->getHandle(scope + "." + portname.unescape());
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log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
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fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
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log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
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fst_clock.push_back(id);
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clocks[w] = id;
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}
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@ -2168,12 +2168,12 @@ struct SimWorker : SimShared
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
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log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
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fstHandle id = fst->getHandle(scope + "." + portname.unescape());
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log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
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fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
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log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
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fst_clock.push_back(id);
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clocks[w] = id;
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}
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@ -2183,9 +2183,9 @@ struct SimWorker : SimShared
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std::map<Wire*,fstHandle> outputs;
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for (auto wire : topmod->wires()) {
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fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
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fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
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if (id==0 && (wire->port_input || wire->port_output))
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
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if (wire->port_input)
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if (clocks.find(wire)==clocks.end())
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inputs[wire] = id;
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@ -2366,7 +2366,7 @@ struct VCDWriter : public OutputWriter
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vcdfile << stringf("$timescale %s $end\n", worker->timescale);
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worker->top->write_output_header(
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[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", name.unescape()); },
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[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", design->twines.unescaped_str(name)); },
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[this]() { vcdfile << stringf("$upscope $end\n");},
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[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
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if (!use_signal.at(id)) return;
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@ -2432,7 +2432,7 @@ struct FSTWriter : public OutputWriter
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fstWriterSetRepackOnClose(fstfile, 1);
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worker->top->write_output_header(
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[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); },
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[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, design->twines.unescaped_str(stringf("%s",name)).c_str(), nullptr); },
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[this]() { fstWriterSetUpscope(fstfile); },
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[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
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if (!use_signal.at(id)) return;
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@ -2495,7 +2495,7 @@ struct AIWWriter : public OutputWriter
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RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
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Wire *w = worker->top->module->wire(escaped_s);
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if (!w)
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log_error("Wire %s not present in module %s\n",escaped_s.unescape(),worker->top->module);
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log_error("Wire %s not present in module design->twines.unescaped_str(%s\n",escaped_s),worker->top->module);
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if (index < w->start_offset || index > w->start_offset + w->width)
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log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
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if (type == "input") {
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