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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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18
passes/sat/eval.cc
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@ -149,7 +149,7 @@ struct VlogHammerReporter
for (auto c : module->cells())
if (!satgen.importCell(c))
log_error("Failed to import cell %s (type %s) to SAT database.\n", c->name.unescape(), c->type.unescape());
log_error("Failed to import cell %s (type %s) to SAT database.\n", design->twines.unescaped_str(c->name), design->twines.unescaped_str(c->type));
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
@ -262,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", inputs[i].unescape());
log_error("Can't read back value for port %s!\n", design->twines.unescaped_str(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, inputs[i].unescape(), sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, design->twines.unescaped_str(inputs[i]), sig.as_const().as_string());
}
}
if (module->wire(ID(y)) == nullptr)
log_error("No output wire (y) found in module %s!\n", module->name.unescape());
log_error("No output wire (y) found in module %s!\n", design->twines.unescaped_str(module->name));
RTLIL::SigSpec sig(module->wire(ID(y)));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", module, log_signal(sig), log_signal(undef));
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), module->name.unescape());
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), design->twines.unescaped_str(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@ -288,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", module->name.unescape());
log_error("Output (y) has a different width in module %s compared to rtl!\n", design->twines.unescaped_str(module->name));
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@ -319,10 +319,10 @@ struct VlogHammerReporter
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
if (mod->wire(esc_name) == nullptr)
log_error("Can't find input %s in module %s!\n", name, mod->name.unescape());
log_error("Can't find input %s in module %s!\n", name, design->twines.unescaped_str(mod->name));
RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name, mod->name.unescape());
log_error("Wire %s in module %s is not an input!\n", name, design->twines.unescaped_str(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name);
width = port->width;
@ -443,7 +443,7 @@ struct EvalPass : public Pass {
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
module->name.unescape(), mod->name.unescape());
module->name.unescape(), design->twines.unescaped_str(mod->name));
module = mod;
}
if (module == NULL)