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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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6
passes/sat/assertpmux.cc
View file

@ -54,10 +54,10 @@ struct AssertpmuxWorker
for (auto cell : module->cells())
{
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->type.in(TW($mux), TW($pmux)))
{
int width = cell->getParam(ID::WIDTH).as_int();
int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
int numports = cell->type == TW($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
@ -234,7 +234,7 @@ struct AssertpmuxPass : public Pass {
vector<Cell*> pmux_cells;
for (auto cell : module->selected_cells())
if (cell->type == ID($pmux))
if (cell->type == TW($pmux))
pmux_cells.push_back(cell);
for (auto cell : pmux_cells)

12
passes/sat/async2sync.cc
View file

@ -79,9 +79,9 @@ struct Async2syncPass : public Pass {
for (auto cell : vector<Cell*>(module->selected_cells()))
{
if (cell->type.in(ID($print), ID($check)))
if (cell->type.in(TW($print), TW($check)))
{
if (cell->type == ID($check))
if (cell->type == TW($check))
have_check_cells = true;
bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
@ -111,7 +111,7 @@ struct Async2syncPass : public Pass {
module->addDff(NEW_TWINE, sig_trg, sig_args, sig_args_q, trg_polarity, cell->src_ref());
cell->setPort(TW::EN, sig_en_q);
cell->setPort(TW::ARGS, sig_args_q);
if (cell->type == ID($check)) {
if (cell->type == TW($check)) {
SigBit sig_a = cell->getPort(TW::A);
Wire *sig_a_q = module->addWire(NEW_TWINE);
sig_a_q->attributes.emplace(ID::init, State::S1);
@ -147,7 +147,7 @@ struct Async2syncPass : public Pass {
ff.unmap_ce_srst();
log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
module, cell, cell->type.unescape(),
module, cell, cell->type.unescaped(),
log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -245,7 +245,7 @@ struct Async2syncPass : public Pass {
ff.unmap_srst();
log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
module, cell, cell->type.unescape(),
module, cell, cell->type.unescaped(),
log_signal(ff.sig_arst), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -279,7 +279,7 @@ struct Async2syncPass : public Pass {
{
// Latch.
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
module, cell, cell->type.unescape(),
module, cell, cell->type.unescaped(),
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);

24
passes/sat/clk2fflogic.cc
View file

@ -173,7 +173,7 @@ struct Clk2fflogicPass : public Pass {
auto &port = mem.rd_ports[i];
if (port.clk_enable)
log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, mem.memid.unescape(), module);
"Call \"memory\" with -nordff to avoid this error.\n", i, design->twines.unescaped_str(mem.memid), module);
}
for (int i = 0; i < GetSize(mem.wr_ports); i++)
@ -184,10 +184,10 @@ struct Clk2fflogicPass : public Pass {
continue;
log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
i, module, mem.memid.unescape(), log_signal(port.clk),
i, module, design->twines.unescaped_str(mem.memid), log_signal(port.clk),
log_signal(port.addr), log_signal(port.data));
Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk))));
Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", design->twines.unescaped_str(mem.memid), i, log_signal(port.clk))));
past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
module->addFf(NEW_TWINE, port.clk, past_clk);
@ -203,13 +203,13 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge = module->Eqx(NEW_TWINE, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en));
SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.en));
module->addFf(NEW_TWINE, port.en, en_q);
SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr));
SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.addr));
module->addFf(NEW_TWINE, port.addr, addr_q);
SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data));
SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.data));
module->addFf(NEW_TWINE, port.data, data_q);
port.clk = State::S0;
@ -228,9 +228,9 @@ struct Clk2fflogicPass : public Pass {
for (auto cell : vector<Cell*>(module->selected_cells()))
{
if (cell->type.in(ID($print), ID($check)))
if (cell->type.in(TW($print), TW($check)))
{
if (cell->type == ID($check))
if (cell->type == TW($check))
have_check_cells = true;
bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
@ -262,7 +262,7 @@ struct Clk2fflogicPass : public Pass {
cell->setPort(TW::EN, module->And(NEW_TWINE, sig_en_sampled, sig_trg_combined));
cell->setPort(TW::ARGS, sig_args_sampled);
if (cell->type == ID($check)) {
if (cell->type == TW($check)) {
SigBit sig_a = cell->getPort(TW::A);
SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled;
cell->setPort(TW::A, sig_a_sampled);
@ -291,16 +291,16 @@ struct Clk2fflogicPass : public Pass {
if (ff.has_clk) {
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
module, cell, cell->type.unescape(),
module, cell, cell->type.unescaped(),
log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
} else if (ff.has_aload) {
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
module, cell, cell->type.unescape(),
module, cell, cell->type.unescaped(),
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
} else {
// $sr.
log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
module, cell, cell->type.unescape(),
module, cell, cell->type.unescaped(),
log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
}

10
passes/sat/cutpoint.cc
View file

@ -126,7 +126,7 @@ struct CutpointPass : public Pass {
wire_drivers.insert(bit);
for (auto cell : module->selected_cells()) {
if (cell->type == ID($anyseq))
if (cell->type == TW($anyseq))
continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", module, cell);
for (auto &conn : cell->connections()) {
@ -135,7 +135,7 @@ struct CutpointPass : public Pass {
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
if (wire_drivers.count(bit)) {
log_debug(" Treating inout port '%s' as input.\n", conn.first.unescape());
log_debug(" Treating inout port '%s' as input.\n", design->twines.unescaped_str(conn.first));
do_cut = false;
break;
}
@ -143,7 +143,7 @@ struct CutpointPass : public Pass {
if (do_cut) {
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_TWINE, GetSize(conn.second)));
if (cell->input(conn.first)) {
log_debug(" Treating inout port '%s' as output.\n", conn.first.unescape());
log_debug(" Treating inout port '%s' as output.\n", design->twines.unescaped_str(conn.first));
for (auto bit : sigmap(conn.second))
wire_drivers.insert(bit);
}
@ -154,7 +154,7 @@ struct CutpointPass : public Pass {
RTLIL::Cell *scopeinfo = nullptr;
RTLIL::IdString cell_name(cell->name);
if (flag_scopeinfo && cell_name.isPublic()) {
auto scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo));
auto scopeinfo = module->addCell(NEW_TWINE, TW($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
for (auto const &attr : cell->attributes)
@ -162,7 +162,7 @@ struct CutpointPass : public Pass {
if (attr.first == ID::hdlname)
scopeinfo->attributes.insert(attr);
else
scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second);
scopeinfo->attributes.emplace(stringf("\\cell_%s", design->twines.unescaped_str(attr.first)), attr.second);
}
}

18
passes/sat/eval.cc
View file

@ -149,7 +149,7 @@ struct VlogHammerReporter
for (auto c : module->cells())
if (!satgen.importCell(c))
log_error("Failed to import cell %s (type %s) to SAT database.\n", c->name.unescape(), c->type.unescape());
log_error("Failed to import cell %s (type %s) to SAT database.\n", design->twines.unescaped_str(c->name), design->twines.unescaped_str(c->type));
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
@ -262,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", inputs[i].unescape());
log_error("Can't read back value for port %s!\n", design->twines.unescaped_str(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, inputs[i].unescape(), sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, design->twines.unescaped_str(inputs[i]), sig.as_const().as_string());
}
}
if (module->wire(ID(y)) == nullptr)
log_error("No output wire (y) found in module %s!\n", module->name.unescape());
log_error("No output wire (y) found in module %s!\n", design->twines.unescaped_str(module->name));
RTLIL::SigSpec sig(module->wire(ID(y)));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", module, log_signal(sig), log_signal(undef));
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), module->name.unescape());
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), design->twines.unescaped_str(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@ -288,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", module->name.unescape());
log_error("Output (y) has a different width in module %s compared to rtl!\n", design->twines.unescaped_str(module->name));
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@ -319,10 +319,10 @@ struct VlogHammerReporter
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
if (mod->wire(esc_name) == nullptr)
log_error("Can't find input %s in module %s!\n", name, mod->name.unescape());
log_error("Can't find input %s in module %s!\n", name, design->twines.unescaped_str(mod->name));
RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name, mod->name.unescape());
log_error("Wire %s in module %s is not an input!\n", name, design->twines.unescaped_str(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name);
width = port->width;
@ -443,7 +443,7 @@ struct EvalPass : public Pass {
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
module->name.unescape(), mod->name.unescape());
module->name.unescape(), design->twines.unescaped_str(mod->name));
module = mod;
}
if (module == NULL)

38
passes/sat/expose.cc
View file

@ -85,7 +85,7 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
SigPool dffsignals;
for (auto cell : module->cells()) {
if (ct.cell_known(cell->type) && cell->hasPort(TW::Q))
if (ct.cell_known(cell->type_impl) && cell->hasPort(TW::Q))
dffsignals.add(sigmap(cell->getPort(TW::Q)));
}
@ -111,7 +111,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
info.arst_value = RTLIL::State::Sm;
info.cell = cell;
if (info.cell->type == ID($dff)) {
if (info.cell->type == TW($dff)) {
info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit();
info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(TW::D)).to_sigbit_vector();
@ -123,7 +123,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
continue;
}
if (info.cell->type == ID($adff)) {
if (info.cell->type == TW($adff)) {
info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit();
info.bit_arst = sigmap(info.cell->getPort(TW::ARST)).as_bit();
info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
@ -139,9 +139,9 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
continue;
}
if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
if (info.cell->type.in(TW($_DFF_N_), TW($_DFF_P_))) {
info.bit_clk = sigmap(info.cell->getPort(TW::C)).as_bit();
info.clk_polarity = info.cell->type == ID($_DFF_P_);
info.clk_polarity = info.cell->type == TW($_DFF_P_);
info.bit_d = sigmap(info.cell->getPort(TW::D)).as_bit();
bit_info[sigmap(info.cell->getPort(TW::Q)).as_bit()] = info;
continue;
@ -210,7 +210,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
{
if (module->count_id(name))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", name.unescape());
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", design->twines.unescaped_str(name));
return module->addWire(name, width);
}
@ -497,10 +497,10 @@ struct ExposePass : public Pass {
}
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
if (!ct.cell_known(cell->type_impl))
continue;
for (auto &conn : cell->connections_)
if (ct.cell_output(cell->type, conn.first))
if (ct.cell_output(cell->type_impl, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@ -518,10 +518,10 @@ struct ExposePass : public Pass {
}
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
if (!ct.cell_known(cell->type_impl))
continue;
for (auto &conn : cell->connections_)
if (ct.cell_input(cell->type, conn.first))
if (ct.cell_input(cell->type_impl, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@ -578,7 +578,7 @@ struct ExposePass : public Pass {
if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not));
RTLIL::Cell *c = module->addCell(NEW_TWINE, TW($not));
c->parameters[ID::A_SIGNED] = 0;
c->parameters[ID::A_WIDTH] = 1;
c->parameters[ID::Y_WIDTH] = 1;
@ -594,7 +594,7 @@ struct ExposePass : public Pass {
if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not));
RTLIL::Cell *c = module->addCell(NEW_TWINE, TW($not));
c->parameters[ID::A_SIGNED] = 0;
c->parameters[ID::A_WIDTH] = 1;
c->parameters[ID::Y_WIDTH] = 1;
@ -632,13 +632,13 @@ struct ExposePass : public Pass {
if (!p->port_input && !p->port_output)
continue;
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + p->name.unescape(), p->width);
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + design->twines.unescaped_str(p->name), p->width);
if (p->port_input)
w->port_output = true;
if (p->port_output)
w->port_input = true;
log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape());
log("New module port: %s/%s (%s)\n", module, w, cell->type.unescaped());
RTLIL::SigSpec sig;
if (cell->hasPort(p->name))
@ -654,13 +654,13 @@ struct ExposePass : public Pass {
{
for (auto &it : cell->connections())
{
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + it.first.unescape(), it.second.size());
if (ct.cell_input(cell->type, it.first))
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + design->twines.unescaped_str(it.first), it.second.size());
if (ct.cell_input(cell->type_impl, it.first))
w->port_output = true;
if (ct.cell_output(cell->type, it.first))
if (ct.cell_output(cell->type_impl, it.first))
w->port_input = true;
log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape());
log("New module port: %s/%s (%s)\n", module, w, cell->type.unescaped());
if (w->port_input)
module->connect(RTLIL::SigSig(it.second, w));
@ -673,7 +673,7 @@ struct ExposePass : public Pass {
}
for (auto cell : delete_cells) {
log("Removing cell: %s/%s (%s)\n", module, cell, cell->type.unescape());
log("Removing cell: %s/%s (%s)\n", module, cell, cell->type.unescaped());
module->remove(cell);
}
}

16
passes/sat/fmcombine.cc
View file

@ -95,11 +95,11 @@ struct FmcombineWorker
void generate()
{
if (design->module(combined_type)) {
// log("Combined module %s already exists.\n", combined_type.unescape());
// log("Combined module %s already exists.\n", design->twines.unescaped_str(combined_type));
return;
}
log("Generating combined module %s from module %s.\n", combined_type.unescape(), orig_type.unescape());
log("Generating combined module %s from module %s.\n", design->twines.unescaped_str(combined_type), design->twines.unescaped_str(orig_type));
module = design->addModule(combined_type);
for (auto wire : original->wires()) {
@ -110,7 +110,7 @@ struct FmcombineWorker
for (auto cell : original->cells()) {
if (design->module(cell->type) == nullptr) {
if (opts.anyeq && cell->type.in(ID($anyseq), ID($anyconst))) {
if (opts.anyeq && cell->type.in(TW($anyseq), TW($anyconst))) {
Cell *gold = import_prim_cell(cell, "_gold");
for (auto &conn : cell->connections())
module->connect(import_sig(conn.second, "_gate"), gold->getPort(conn.first));
@ -153,7 +153,7 @@ struct FmcombineWorker
for (auto cell : original->cells())
{
if (!ct.cell_known(cell->type))
if (!ct.cell_known(cell->type_impl))
continue;
for (auto &conn : cell->connections())
@ -174,7 +174,7 @@ struct FmcombineWorker
for (auto cell : original->cells())
{
if (!ct.cell_known(cell->type))
if (!ct.cell_known(cell->type_impl))
continue;
bool skip_cell = !cell_to_eq_nets.count(cell);
@ -332,15 +332,15 @@ struct FmcombinePass : public Pass {
module = design->module(module_name);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", module_name.unescape());
log_cmd_error("Module %s not found.\n", design->twines.unescaped_str(module_name));
gold_cell = module->cell(gold_name);
if (gold_cell == nullptr)
log_cmd_error("Gold cell %s not found in module %s.\n", gold_name.unescape(), module);
log_cmd_error("Gold cell %s not found in module %s.\n", design->twines.unescaped_str(gold_name), module);
gate_cell = module->cell(gate_name);
if (gate_cell == nullptr)
log_cmd_error("Gate cell %s not found in module %s.\n", gate_name.unescape(), module);
log_cmd_error("Gate cell %s not found in module %s.\n", design->twines.unescaped_str(gate_name), module);
}
else
{

50
passes/sat/formalff.cc
View file

@ -110,9 +110,9 @@ struct InitValWorker
return ff.val_init[portbit.offset];
}
if (cell->type.in(ID($mux), ID($and), ID($or), ID($eq), ID($eqx), ID($initstate)))
if (cell->type.in(TW($mux), TW($and), TW($or), TW($eq), TW($eqx), TW($initstate)))
{
if (cell->type == ID($mux))
if (cell->type == TW($mux))
{
SigBit sig_s = sigmap(cell->getPort(TW::S));
State init_s = initconst(sig_s);
@ -131,16 +131,16 @@ struct InitValWorker
return init_y;
}
if (cell->type.in(ID($and), ID($or)))
if (cell->type.in(TW($and), TW($or)))
{
State init_a = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, portbit.offset));
State init_b = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, portbit.offset));
State init_y;
if (init_a == init_b)
init_y = init_a;
else if (cell->type == ID($and) && (init_a == State::S0 || init_b == State::S0))
else if (cell->type == TW($and) && (init_a == State::S0 || init_b == State::S0))
init_y = State::S0;
else if (cell->type == ID($or) && (init_a == State::S1 || init_b == State::S1))
else if (cell->type == TW($or) && (init_a == State::S1 || init_b == State::S1))
init_y = State::S1;
else
init_y = State::Sx;
@ -149,7 +149,7 @@ struct InitValWorker
return init_y;
}
if (cell->type.in(ID($eq), ID($eqx))) // Treats $eqx as $eq
if (cell->type.in(TW($eq), TW($eqx))) // Treats $eqx as $eq
{
if (portbit.offset > 0) {
initconst_bits[bit] = State::S0;
@ -178,7 +178,7 @@ struct InitValWorker
return init_y;
}
if (cell->type == ID($initstate))
if (cell->type == TW($initstate))
{
initconst_bits[bit] = State::S1;
return State::S1;
@ -224,7 +224,7 @@ struct InitValWorker
for (auto portbit : portbits) {
RTLIL::Cell *cell = portbit.cell;
if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !cell->is_builtin_ff()) {
if (!cell->type.in(TW($mux), TW($and), TW($or), TW($mem_v2)) && !cell->is_builtin_ff()) {
return true;
}
}
@ -244,7 +244,7 @@ struct InitValWorker
return true;
}
else if (cell->type == ID($mux))
else if (cell->type == TW($mux))
{
State init_s = initconst(cell->getPort(TW::S).as_bit());
if (init_s == State::S0 && portbit.port == ID::B)
@ -256,14 +256,14 @@ struct InitValWorker
if (is_initval_used(sig_y[portbit.offset]))
return true;
}
else if (cell->type.in(ID($and), ID($or)))
else if (cell->type.in(TW($and), TW($or)))
{
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
auto sig_y = cell->getPort(TW::Y);
if (GetSize(sig_y) != GetSize(sig_a) || GetSize(sig_y) != GetSize(sig_b))
return true; // TODO handle more of this
State absorbing = cell->type == ID($and) ? State::S0 : State::S1;
State absorbing = cell->type == TW($and) ? State::S0 : State::S1;
if (portbit.port == ID::A && initconst(sig_b[portbit.offset]) == absorbing)
continue;
if (portbit.port == ID::B && initconst(sig_a[portbit.offset]) == absorbing)
@ -272,7 +272,7 @@ struct InitValWorker
if (is_initval_used(sig_y[portbit.offset]))
return true;
}
else if (cell->type == ID($mem_v2))
else if (cell->type == TW($mem_v2))
{
// TODO Use mem.h instead to uniformily cover all cases, most
// likely requires processing all memories when initializing
@ -368,7 +368,7 @@ struct PropagateWorker
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].at(0) == State::S1, false);
for (auto cell : module->cells()) {
if (cell->type.in(ID($not), ID($_NOT_))) {
if (cell->type.in(TW($not), TW($_NOT_))) {
auto sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
sig_a.extend_u0(GetSize(sig_y), cell->hasParam(ID::A_SIGNED) && cell->parameters.at(ID::A_SIGNED).as_bool());
@ -393,7 +393,7 @@ struct PropagateWorker
}
for (auto cell : module->cells()) {
if (cell->type.in(ID($not), ID($_NOT_)))
if (cell->type.in(TW($not), TW($_NOT_)))
continue;
for (auto &conn : cell->connections()) {
if (!cell->output(conn.first))
@ -402,7 +402,7 @@ struct PropagateWorker
sigmap.apply(bit);
if (replaced_clk_bits.count(bit))
log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n",
log_signal(bit), cell->module->design->twines.str(cell->meta_->name), cell->type.unescape(), module);
log_signal(bit), cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped(), module);
}
}
}
@ -647,7 +647,7 @@ struct FormalFfPass : public Pass {
continue;
SigBit clk = sigmap(ff.sig_clk);
clk_bits[{clk, ff.pol_clk}].push_back(cell);
} else if (cell->type == ID($mem_v2)) {
} else if (cell->type == TW($mem_v2)) {
auto const &mem = memories.at(cell->name);
for (auto &rd_port : mem.rd_ports)
if (rd_port.clk_enable)
@ -708,11 +708,11 @@ struct FormalFfPass : public Pass {
auto driver = *found->second.begin();
bool is_gate =
pol_clk ? driver.cell->type.in(ID($and), ID($_AND_)) : driver.cell->type.in(ID($or), ID($_OR_));
pol_clk ? driver.cell->type.in(TW($and), TW($_AND_)) : driver.cell->type.in(TW($or), TW($_OR_));
if (!is_gate) {
log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", module,
driver.cell, driver.cell->type.unescape(), pol_clk ? "posedge" : "negedge",
driver.cell, design->twines.unescaped_str(driver.cell->type), pol_clk ? "posedge" : "negedge",
module, log_signal(SigSpec(clk)));
continue;
@ -754,7 +754,7 @@ struct FormalFfPass : public Pass {
log_debug(
"FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible type: %s\n",
module, log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)),
gate_driver.cell->type.unescape());
design->twines.unescaped_str(gate_driver.cell->type));
continue;
}
@ -782,7 +782,7 @@ struct FormalFfPass : public Pass {
for (auto clocked_cell : clocked_cells) {
log_debug("rewriting cell %s.%s (%s)\n", module, clocked_cell,
clocked_cell->type.unescape());
design->twines.unescaped_str(clocked_cell->type));
if (clocked_cell->is_builtin_ff()) {
@ -794,7 +794,7 @@ struct FormalFfPass : public Pass {
ff.has_ce = true;
ff.sig_clk = gate_clock;
ff.emit();
} else if (clocked_cell->type == ID($mem_v2)) {
} else if (clocked_cell->type == TW($mem_v2)) {
auto &mem = memories.at(clocked_cell->name);
bool changed = false;
for (auto &rd_port : mem.rd_ports) {
@ -855,7 +855,7 @@ struct FormalFfPass : public Pass {
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
module, cell, cell->type.unescape(),
module, cell, cell->type.unescaped(),
log_const(before), log_const(ff.val_init));
worker.initvals.set_init(ff.sig_q, ff.val_init);
}
@ -868,7 +868,7 @@ struct FormalFfPass : public Pass {
for (auto cell : module->selected_cells())
{
if (flag_anyinit2ff && cell->type == ID($anyinit))
if (flag_anyinit2ff && cell->type == TW($anyinit))
{
FfData ff(&initvals, cell);
ff.remove();
@ -895,7 +895,7 @@ struct FormalFfPass : public Pass {
cell, cell->type, module);
if (ff.has_aload || ff.has_arst || ff.has_sr)
log_error("Async inputs on %s (%s) from module %s, run async2sync first.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr;
@ -912,7 +912,7 @@ struct FormalFfPass : public Pass {
if (!attr.empty() && attr != clk_polarity)
log_error("CLK %s on %s (%s) from module %s also used with opposite polarity, run clk2fflogic instead.\n",
clk_wire, cell, cell->type.unescape(), module);
clk_wire, cell, cell->type.unescaped(), module);
attr = clk_polarity;
clk_wire->set_bool_attribute(ID::keep);

14
passes/sat/freduce.cc
View file

@ -139,7 +139,7 @@ struct FindReducedInputs
if (ez_cells.count(drv.first) == 0) {
satgen.setContext(&sigmap, "A");
if (!satgen.importCell(drv.first))
log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape());
log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, design->twines.unescaped_str(drv.first->type));
satgen.setContext(&sigmap, "B");
if (!satgen.importCell(drv.first))
log_abort();
@ -256,7 +256,7 @@ struct PerformReduction
std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
if (celldone.count(drv.first) == 0) {
if (!satgen.importCell(drv.first))
log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape());
log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, design->twines.unescaped_str(drv.first->type));
celldone.insert(drv.first);
}
int max_child_depth = 0;
@ -616,11 +616,11 @@ struct FreduceWorker
bits_full_total += w->width;
}
for (auto cell : module->cells()) {
if (ct.cell_known(cell->type)) {
if (ct.cell_known(cell->type_impl)) {
std::set<RTLIL::SigBit> inputs, outputs;
for (auto &port : cell->connections()) {
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
if (ct.cell_output(cell->type, port.first))
if (ct.cell_output(cell->type_impl, port.first))
outputs.insert(bits.begin(), bits.end());
else
inputs.insert(bits.begin(), bits.end());
@ -631,7 +631,7 @@ struct FreduceWorker
batches.push_back(outputs);
bits_full_total += outputs.size();
}
if (inv_mode && cell->type == ID($_NOT_))
if (inv_mode && cell->type == TW($_NOT_))
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(TW::A)), sigmap(cell->getPort(TW::Y))));
}
@ -718,7 +718,7 @@ struct FreduceWorker
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE);
for (auto &port : drv->connections_)
if (ct.cell_output(drv->type, port.first))
if (ct.cell_output(drv->type_impl, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
if (grp[i].inverted)
@ -727,7 +727,7 @@ struct FreduceWorker
{
inv_sig = module->addWire(NEW_TWINE);
RTLIL::Cell *inv_cell = module->addCell(NEW_TWINE, ID($_NOT_));
RTLIL::Cell *inv_cell = module->addCell(NEW_TWINE, TW($_NOT_));
inv_cell->setPort(TW::A, grp[0].bit);
inv_cell->setPort(TW::Y, inv_sig);
}

22
passes/sat/miter.cc
View file

@ -128,7 +128,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
log_cmd_error("No matching port in gold module was found for %s!\n", design->twines.str(gate_wire->meta_->name).c_str());
}
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", miter_name.unescape(), gold_name.unescape(), gate_name.unescape());
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", design->twines.unescaped_str(miter_name), design->twines.unescaped_str(gold_name), design->twines.unescaped_str(gate_name));
RTLIL::Module *miter_module = new RTLIL::Module;
miter_module->design = design;
@ -184,7 +184,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
{
RTLIL::SigSpec gold_x = miter_module->addWire(NEW_TWINE, GetSize(w_gold));
for (int i = 0; i < GetSize(w_gold); i++) {
RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_TWINE, TW($eqx));
eqx_cell->parameters[ID::A_WIDTH] = 1;
eqx_cell->parameters[ID::B_WIDTH] = 1;
eqx_cell->parameters[ID::Y_WIDTH] = 1;
@ -198,7 +198,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_TWINE, w_gold->width);
RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_TWINE, w_gate->width);
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_TWINE, ID($or));
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_TWINE, TW($or));
or_gold_cell->parameters[ID::A_WIDTH] = GetSize(w_gold);
or_gold_cell->parameters[ID::B_WIDTH] = GetSize(w_gold);
or_gold_cell->parameters[ID::Y_WIDTH] = GetSize(w_gold);
@ -208,7 +208,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
or_gold_cell->setPort(TW::B, gold_x);
or_gold_cell->setPort(TW::Y, gold_masked);
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_TWINE, ID($or));
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_TWINE, TW($or));
or_gate_cell->parameters[ID::A_WIDTH] = GetSize(w_gate);
or_gate_cell->parameters[ID::B_WIDTH] = GetSize(w_gate);
or_gate_cell->parameters[ID::Y_WIDTH] = GetSize(w_gate);
@ -218,7 +218,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
or_gate_cell->setPort(TW::B, gold_x);
or_gate_cell->setPort(TW::Y, gate_masked);
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, TW($eqx));
eq_cell->parameters[ID::A_WIDTH] = GetSize(w_gold);
eq_cell->parameters[ID::B_WIDTH] = GetSize(w_gate);
eq_cell->parameters[ID::Y_WIDTH] = 1;
@ -231,7 +231,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
}
else
{
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, TW($eqx));
eq_cell->parameters[ID::A_WIDTH] = GetSize(w_gold);
eq_cell->parameters[ID::B_WIDTH] = GetSize(w_gate);
eq_cell->parameters[ID::Y_WIDTH] = 1;
@ -261,7 +261,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
}
if (all_conditions.size() != 1) {
RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_TWINE, ID($reduce_and));
RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_TWINE, TW($reduce_and));
reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size();
reduce_cell->parameters[ID::Y_WIDTH] = 1;
reduce_cell->parameters[ID::A_SIGNED] = 0;
@ -271,7 +271,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
}
if (flag_make_assert) {
RTLIL::Cell *assert_cell = miter_module->addCell(NEW_TWINE, ID($assert));
RTLIL::Cell *assert_cell = miter_module->addCell(NEW_TWINE, TW($assert));
assert_cell->setPort(TW::A, all_conditions);
assert_cell->setPort(TW::EN, State::S1);
}
@ -279,7 +279,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::Wire *w_trigger = miter_module->addWire(TW::trigger);
w_trigger->port_output = true;
RTLIL::Cell *not_cell = miter_module->addCell(NEW_TWINE, ID($not));
RTLIL::Cell *not_cell = miter_module->addCell(NEW_TWINE, TW($not));
not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
not_cell->parameters[ID::Y_WIDTH] = w_trigger->width;
@ -353,13 +353,13 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
vector<Cell*> cell_list = module->cells();
for (auto cell : cell_list)
{
if (!cell->type.in(ID($assert), ID($assume)))
if (!cell->type.in(TW($assert), TW($assume)))
continue;
SigBit is_active = module->Nex(NEW_TWINE, cell->getPort(TW::A), State::S1);
SigBit is_enabled = module->Eqx(NEW_TWINE, cell->getPort(TW::EN), State::S1);
if (cell->type == ID($assert)) {
if (cell->type == TW($assert)) {
assert_signals.append(module->And(NEW_TWINE, is_active, is_enabled));
} else {
assume_signals.append(module->And(NEW_TWINE, is_active, is_enabled));

36
passes/sat/mutate.cc
View file

@ -558,7 +558,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (opts.none) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += " -mode none";
if (filename.empty())
log("%s\n", str);
@ -569,20 +569,20 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto &entry : database) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -mode %s", entry.mode);
if (!entry.module.empty())
str += stringf(" -module %s", entry.module.unescape());
str += stringf(" -module %s", design->twines.unescaped_str(entry.module));
if (!entry.cell.empty())
str += stringf(" -cell %s", entry.cell.unescape());
str += stringf(" -cell %s", design->twines.unescaped_str(entry.cell));
if (!entry.port.empty())
str += stringf(" -port %s", entry.port.unescape());
str += stringf(" -port %s", design->twines.unescaped_str(entry.port));
if (entry.portbit >= 0)
str += stringf(" -portbit %d", entry.portbit);
if (entry.ctrlbit >= 0)
str += stringf(" -ctrlbit %d", entry.ctrlbit);
if (!entry.wire.empty())
str += stringf(" -wire %s", entry.wire.unescape());
str += stringf(" -wire %s", design->twines.unescaped_str(entry.wire));
if (entry.wirebit >= 0)
str += stringf(" -wirebit %d", entry.wirebit);
for (auto &s : entry.src)
@ -600,7 +600,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
if (ctrl_wire == nullptr)
{
log("Adding ctrl port %s to module %s.\n", name.unescape(), module);
log("Adding ctrl port %s to module %s.\n", design->twines.unescaped_str(name), module);
ctrl_wire = module->addWire(name, width);
ctrl_wire->port_input = true;
@ -652,13 +652,13 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
if (cell->input(opts.port))
{
log("Add input inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
log("Add input inverter at %s.%s.%s[%d].\n", module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
SigBit outbit = module->Not(NEW_TWINE, bit);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
log("Add output inverter at %s.%s.%s[%d].\n", module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
SigBit inbit = module->addWire(NEW_TWINE);
SigBit outbit = module->Not(NEW_TWINE, inbit);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -680,13 +680,13 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
SigBit outbit = one ? State::S1 : State::S0;
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit);
SigBit inbit = module->addWire(NEW_TWINE);
SigBit outbit = one ? State::S1 : State::S0;
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -709,13 +709,13 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit, opts.ctrlbit);
SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_TWINE, bit, ctrl);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit, opts.ctrlbit);
SigBit inbit = module->addWire(NEW_TWINE);
SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_TWINE, inbit, ctrl);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -947,26 +947,26 @@ struct MutatePass : public Pass {
Module *module = design->module(opts.module);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", opts.module.unescape());
log_cmd_error("Module %s not found.\n", design->twines.unescaped_str(opts.module));
if (opts.cell.empty())
log_cmd_error("Missing -cell argument.\n");
Cell *cell = module->cell(opts.cell);
if (cell == nullptr)
log_cmd_error("Cell %s not found in module %s.\n", opts.cell.unescape(), opts.module.unescape());
log_cmd_error("Cell %s not found in module %s.\n", design->twines.unescaped_str(opts.cell), design->twines.unescaped_str(opts.module));
if (opts.port.empty())
log_cmd_error("Missing -port argument.\n");
if (!cell->hasPort(opts.port))
log_cmd_error("Port %s not found on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
log_cmd_error("Port %s not found on cell %s.%s.\n", design->twines.unescaped_str(opts.port), design->twines.unescaped_str(opts.module), design->twines.unescaped_str(opts.cell));
if (opts.portbit < 0)
log_cmd_error("Missing -portbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.portbit)
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", design->twines.unescaped_str(opts.port), design->twines.unescaped_str(opts.module), design->twines.unescaped_str(opts.cell));
if (opts.mode == "inv") {
mutate_inv(design, opts);
@ -982,7 +982,7 @@ struct MutatePass : public Pass {
log_cmd_error("Missing -ctrlbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.ctrlbit)
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", design->twines.unescaped_str(opts.port), design->twines.unescaped_str(opts.module), design->twines.unescaped_str(opts.cell));
if (opts.mode == "cnot0" || opts.mode == "cnot1") {
mutate_cnot(design, opts, opts.mode == "cnot1");

4
passes/sat/recover_names.cc
View file

@ -641,8 +641,8 @@ struct RecoverNamesWorker {
for (auto gate_bit : gate_bits) {
if (solved_gate.count(gate_bit.bit))
continue;
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", gold_bit.name.unescape(), gold_bit.bit,
gate_bit.inverted ? "" : "!", gate_bit.bit.name.unescape(), gate_bit.bit.bit);
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", design->twines.unescaped_str(gold_bit.name), gold_bit.bit,
gate_bit.inverted ? "" : "!", design->twines.unescaped_str(gate_bit.bit.name), gate_bit.bit.bit);
if (!prove_equiv(gold_worker, gate_worker, gold_anchors, gate_anchors, gold_bit, gate_bit.bit, gate_bit.inverted))
continue;
log_debug(" success!\n");

8
passes/sat/sat.cc
View file

@ -245,7 +245,7 @@ struct SatHelper
if (design->selected(module, cell)) {
if (satgen.importCell(cell, timestep)) {
for (auto &p : cell->connections())
if (ct.cell_output(cell->type, p.first))
if (ct.cell_output(cell->type_impl, p.first))
show_drivers.insert(sigmap(p.second), cell);
import_cell_counter++;
} else report_missing_model(ignore_unknown_cells, cell);
@ -267,7 +267,7 @@ struct SatHelper
// Check for $anyinit cells that are forced to be defined
if (set_init_undef && satgen.def_formal)
for (auto cell : module->cells())
if (cell->type == ID($anyinit))
if (cell->type == TW($anyinit))
forced_def.append(sigmap(cell->getPort(TW::Q)));
for (auto wire : module->wires())
@ -533,7 +533,7 @@ struct SatHelper
} else {
for (auto &d : drivers)
for (auto &p : d->connections()) {
if (d->type == ID($dff) && p.first == TW::CLK)
if (d->type == TW($dff) && p.first == TW::CLK)
continue;
if (d->type.begins_with("$_DFF_") && p.first == TW::C)
continue;
@ -1408,7 +1408,7 @@ struct SatPass : public Pass {
if (show_regs) {
pool<Wire*> reg_wires;
for (auto cell : module->cells()) {
if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_"))
if (cell->type == TW($dff) || cell->type.begins_with("$_DFF_"))
for (auto bit : cell->getPort(TW::Q))
if (bit.wire)
reg_wires.insert(bit.wire);

98
passes/sat/sim.cc
View file

@ -250,7 +250,7 @@ struct SimInstance
if (module->get_blackbox_attribute(true))
log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
module->name.unescape(), hiername().c_str());
design->twines.unescaped_str(module->name), hiername().c_str());
if (module->has_processes())
log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
@ -275,9 +275,9 @@ struct SimInstance
}
if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
fstHandle id = shared->fst->getHandle(scope + "." + wire->name.unescape());
fstHandle id = shared->fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
if (id==0 && wire->name.isPublic())
log_warning("Unable to find wire %s in input file.\n", (scope + "." + wire->name.unescape()));
log_warning("Unable to find wire %s in input file.\n", (scope + "." + design->twines.unescaped_str(wire->name)));
fst_handles[wire] = id;
}
@ -329,7 +329,7 @@ struct SimInstance
}
}
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
if (cell->is_builtin_ff() || cell->type == TW($anyinit)) {
FfData ff_data(nullptr, cell);
ff_state_t ff;
ff.past_d = Const(State::Sx, ff_data.width);
@ -354,13 +354,13 @@ struct SimInstance
fst_memories[name] = shared->fst->getMemoryHandles(scope + "." + RTLIL::unescape_id(name));
}
if (cell->type.in(ID($assert), ID($cover), ID($assume)))
if (cell->type.in(TW($assert), TW($cover), TW($assume)))
formal_database.insert(cell);
if (cell->type == ID($initstate))
if (cell->type == TW($initstate))
initstate_database.insert(cell);
if (cell->type == ID($print)) {
if (cell->type == TW($print)) {
print_database.emplace_back();
auto &print = print_database.back();
print.cell = cell;
@ -413,7 +413,7 @@ struct SimInstance
std::string hiername() const
{
if (instance != nullptr)
return parent->hiername() + "." + instance->name.unescape();
return parent->hiername() + "." + design->twines.unescaped_str(instance->name);
return module->design->twines.str(module->meta_->name);
}
@ -520,7 +520,7 @@ struct SimInstance
{
auto &state = mem_database[memid];
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, memid.unescape());
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, design->twines.unescaped_str(memid));
if (state.data[offset] != data) {
state.data.set(offset, data);
dirty_memories.insert(memid);
@ -573,7 +573,7 @@ struct SimInstance
if (has_y) sig_y = cell->getPort(TW::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescape());
log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescaped());
bool err = false;
RTLIL::Const eval_state;
@ -593,19 +593,19 @@ struct SimInstance
err = true;
if (err)
log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
else
set_state(sig_y, eval_state);
return;
}
if (cell->type == ID($print))
if (cell->type == TW($print))
return;
if (cell->type.in(ID($input_port), ID($output_port), ID($public), ID($connect)))
if (cell->type.in(TW($input_port), TW($output_port), TW($public), TW($connect)))
return;
log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescaped(), module, cell);
}
void update_memory(IdString id) {
@ -619,7 +619,7 @@ struct SimInstance
Const data = Const(State::Sx, mem.width << port.wide_log2);
if (port.clk_enable)
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, mem.memid.unescape());
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, design->twines.unescaped_str(mem.memid));
if (addr.is_fully_def()) {
int addr_int = addr.as_int();
@ -937,17 +937,17 @@ struct SimInstance
State a = get_state(cell->getPort(TW::A))[0];
State en = get_state(cell->getPort(TW::EN))[0];
if (en == State::S1 && (cell->type == ID($cover) ? a == State::S1 : a != State::S1)) {
if (en == State::S1 && (cell->type == TW($cover) ? a == State::S1 : a != State::S1)) {
shared->triggered_assertions.emplace_back(shared->step, this, cell);
}
if (cell->type == ID($cover) && en == State::S1 && a == State::S1)
if (cell->type == TW($cover) && en == State::S1 && a == State::S1)
log("Cover %s.%s (%s) reached.\n", hiername(), cell, label);
if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
if (cell->type == TW($assume) && en == State::S1 && a != State::S1)
log("Assumption %s.%s (%s) failed.\n", hiername(), cell, label);
if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
if (cell->type == TW($assert) && en == State::S1 && a != State::S1) {
log_cell_w_hierarchy("Failed assertion", cell);
if (shared->serious_asserts)
log_error("Assertion %s.%s (%s) failed.\n", hiername(), cell, label);
@ -1085,7 +1085,7 @@ struct SimInstance
for (auto name : hdlname)
enter_scope("\\" + name);
} else {
signal_name = memid.unescape();
signal_name = design->twines.unescaped_str(memid);
}
for (auto &trace_index : trace_mem.second) {
@ -1199,7 +1199,7 @@ struct SimInstance
{
for (auto cell : module->cells())
{
if (cell->type.in(ID($anyseq))) {
if (cell->type.in(TW($anyseq))) {
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
if (sig_y.is_wire()) {
bool found = false;
@ -1212,7 +1212,7 @@ struct SimInstance
}
}
if (!found)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + sig_y.as_wire()->name.unescape()));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(sig_y.as_wire()->name)));
}
}
}
@ -1412,7 +1412,7 @@ struct SimWorker : SimShared
Wire *w = top->module->wire(portname);
if (w == nullptr)
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
top->set_state(w, value);
}
@ -1495,24 +1495,24 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
fst_clock.push_back(id);
}
for (auto portname : clockn)
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
fst_clock.push_back(id);
}
@ -1520,9 +1520,9 @@ struct SimWorker : SimShared
for (auto wire : topmod->wires()) {
if (wire->port_input) {
fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
if (id==0)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
top->fst_inputs[wire] = id;
}
}
@ -1837,7 +1837,7 @@ struct SimWorker : SimShared
Cell *c = topmod->cell(found);
if (!c)
log_warning("Wire/cell %s not present in module %s\n", unescaped_s, topmod);
else if (c->type.in(ID($anyconst), ID($anyseq))) {
else if (c->type.in(TW($anyconst), TW($anyseq))) {
SigSpec sig_y= c->getPort(TW::Y);
if ((int)parts[1].size() != GetSize(sig_y))
log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y));
@ -2084,13 +2084,13 @@ struct SimWorker : SimShared
json.entry("version", "Yosys sim summary");
json.entry("generator", yosys_maybe_version());
json.entry("steps", step);
json.entry("top", top->module->name.unescape());
json.entry("top", design->twines.unescaped_str(top->module->name));
json.name("assertions");
json.begin_array();
for (auto &assertion : triggered_assertions) {
json.begin_object();
json.entry("step", assertion.step);
json.entry("type", assertion.cell->type.unescape());
json.entry("type", design->twines.unescaped_str(assertion.cell->type));
json.entry("path", assertion.instance->witness_full_path(assertion.cell));
auto src = assertion.cell->get_src_attribute();
if (!src.empty()) {
@ -2155,12 +2155,12 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2168,12 +2168,12 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2183,9 +2183,9 @@ struct SimWorker : SimShared
std::map<Wire*,fstHandle> outputs;
for (auto wire : topmod->wires()) {
fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
if (id==0 && (wire->port_input || wire->port_output))
log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
if (wire->port_input)
if (clocks.find(wire)==clocks.end())
inputs[wire] = id;
@ -2366,7 +2366,7 @@ struct VCDWriter : public OutputWriter
vcdfile << stringf("$timescale %s $end\n", worker->timescale);
worker->top->write_output_header(
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", name.unescape()); },
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", design->twines.unescaped_str(name)); },
[this]() { vcdfile << stringf("$upscope $end\n");},
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2432,7 +2432,7 @@ struct FSTWriter : public OutputWriter
fstWriterSetRepackOnClose(fstfile, 1);
worker->top->write_output_header(
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); },
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, design->twines.unescaped_str(stringf("%s",name)).c_str(), nullptr); },
[this]() { fstWriterSetUpscope(fstfile); },
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2495,7 +2495,7 @@ struct AIWWriter : public OutputWriter
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
Wire *w = worker->top->module->wire(escaped_s);
if (!w)
log_error("Wire %s not present in module %s\n",escaped_s.unescape(),worker->top->module);
log_error("Wire %s not present in module design->twines.unescaped_str(%s\n",escaped_s),worker->top->module);
if (index < w->start_offset || index > w->start_offset + w->width)
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
if (type == "input") {

6
passes/sat/synthprop.cc
View file

@ -64,7 +64,7 @@ void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &traci
tracing_data[mod] = TrackingItem();
int cnt = 0;
for (auto cell : mod->cells()) {
if (cell->type == ID($assert)) {
if (cell->type == TW($assert)) {
log("%*sFound assert %s..\n", 2*(depth+1), "", cell);
tracing_data[mod].assertion_cells.emplace(cell);
if (!or_outputs) {
@ -93,7 +93,7 @@ void SynthPropWorker::run()
log_error("Module is not TOP module\n");
TrackingData tracing_data;
tracing(module, 0, tracing_data, module->name.unescape());
tracing(module, 0, tracing_data, design->twines.unescaped_str(module->name));
for (auto &data : tracing_data) {
if (data.second.names.size() == 0) continue;
@ -112,7 +112,7 @@ void SynthPropWorker::run()
}
pool<Wire*> connected;
for (auto cell : data.second.assertion_cells) {
if (cell->type == ID($assert)) {
if (cell->type == TW($assert)) {
RTLIL::Wire *neg_wire = data.first->addWire(NEW_TWINE);
RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE);
data.first->addNot(NEW_ID, cell->getPort(TW::A), neg_wire);