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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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14
passes/proc/proc_arst.cc
View file

@ -39,23 +39,23 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
for (auto cell : mod->cells())
{
if (cell->type == ID($reduce_or) && cell->getPort(TW::Y) == signal)
if (cell->type == TW($reduce_or) && cell->getPort(TW::Y) == signal)
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
if (cell->type == ID($reduce_bool) && cell->getPort(TW::Y) == signal)
if (cell->type == TW($reduce_bool) && cell->getPort(TW::Y) == signal)
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
if (cell->type == ID($logic_not) && cell->getPort(TW::Y) == signal) {
if (cell->type == TW($logic_not) && cell->getPort(TW::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
if (cell->type == ID($not) && cell->getPort(TW::Y) == signal) {
if (cell->type == TW($not) && cell->getPort(TW::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(TW::Y) == signal) {
if (cell->type.in(TW($eq), TW($eqx)) && cell->getPort(TW::Y) == signal) {
if (cell->getPort(TW::A).is_fully_const()) {
if (!cell->getPort(TW::A).as_bool())
polarity = !polarity;
@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
}
}
if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(TW::Y) == signal) {
if (cell->type.in(TW($ne), TW($nex)) && cell->getPort(TW::Y) == signal) {
if (cell->getPort(TW::A).is_fully_const()) {
if (cell->getPort(TW::A).as_bool())
polarity = !polarity;
@ -215,7 +215,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
RTLIL::SigSpec en = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.enable, memwr.enable);
if (!en.is_fully_zero()) {
log_error("Async reset %s causes memory write to %s.\n",
log_signal(sync->signal), memwr.memid.unescape());
log_signal(sync->signal), design->twines.unescaped_str(memwr.memid));
}
apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.address, memwr.address);
apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.data, memwr.data);

4
passes/proc/proc_dff.cc
View file

@ -94,7 +94,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, ID($aldff));
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, TW($aldff));
cell->attributes = proc->attributes;
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
@ -116,7 +116,7 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? TW($ff) : arst ? TW($adff) : TW($dff));
cell->attributes = proc->attributes;
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());

10
passes/proc/proc_dlatch.cc
View file

@ -46,7 +46,7 @@ struct proc_dlatch_db_t
for (auto cell : module->cells())
{
if (cell->type.in(ID($mux), ID($pmux), ID($bwmux)))
if (cell->type.in(TW($mux), TW($pmux), TW($bwmux)))
{
auto sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(sig_y); i++)
@ -185,8 +185,8 @@ struct proc_dlatch_db_t
Cell *cell = it->second.first;
int index = it->second.second;
log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux)));
bool is_bwmux = (cell->type == ID($bwmux));
log_assert(cell->type.in(TW($mux), TW($pmux), TW($bwmux)));
bool is_bwmux = (cell->type == TW($bwmux));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
@ -328,7 +328,7 @@ struct proc_dlatch_db_t
pool<Cell*> next_queue;
for (auto cell : queue) {
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->type.in(TW($mux), TW($pmux)))
fixup_mux(cell);
for (auto bit : upstream_cell2net[cell])
for (auto cell : upstream_net2cell[bit])
@ -338,7 +338,7 @@ struct proc_dlatch_db_t
queue.clear();
for (auto cell : next_queue) {
if (!visited.count(cell) && ct.cell_known(cell->type))
if (!visited.count(cell) && ct.cell_known(cell->type_impl))
queue.insert(cell);
}
}

6
passes/proc/proc_memwr.cc
View file

@ -42,7 +42,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
priority_mask.set(prev_port_ids[i], State::S1);
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_TWINE, ID($memwr_v2));
RTLIL::Cell *cell = mod->addCell(NEW_TWINE, TW($memwr_v2));
cell->attributes = memwr.attributes;
cell->setParam(ID::MEMID, Const(memwr.memid.str()));
cell->setParam(ID::ABITS, GetSize(memwr.address));
@ -102,8 +102,8 @@ struct ProcMemWrPass : public Pass {
for (auto mod : design->all_selected_modules()) {
dict<IdString, int> next_port_id;
for (auto cell : mod->cells()) {
if (cell->type.in(ID($memwr), ID($memwr_v2))) {
bool is_compat = cell->type == ID($memwr);
if (cell->type.in(TW($memwr), TW($memwr_v2))) {
bool is_compat = cell->type == TW($memwr);
IdString memid = cell->parameters.at(ID::MEMID).decode_string();
int port_id = cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int();
if (port_id >= next_port_id[memid])

6
passes/proc/proc_mux.cc
View file

@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
else
{
// create compare cell
RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? ID($eqx) : ID($eq));
RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? TW($eqx) : TW($eq));
apply_attrs(eq_cell, sw, cs);
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
@ -204,7 +204,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
ctrl_wire = mod->addWire(Twine{sstr.str() + "_CTRL"});
// reduce cmp vector to one logic signal
RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, ID($reduce_or));
RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, TW($reduce_or));
apply_attrs(any_cell, sw, cs);
any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
@ -239,7 +239,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
RTLIL::Wire *result_wire = mod->addWire(Twine{sstr.str() + "_Y"}, when_signal.size());
// create the multiplexer itself
RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, ID($mux));
RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, TW($mux));
apply_attrs(mux_cell, sw, cs);
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());