mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-22 23:25:51 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
afdae7b87e
commit
c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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@ -74,7 +74,7 @@ struct ShareWorker
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queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
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for (auto &it : module->cells_)
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if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type)) {
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if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type_impl)) {
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pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
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queue_bits.insert(bits.begin(), bits.end());
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}
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@ -88,13 +88,13 @@ struct ShareWorker
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queue_bits.clear();
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for (auto &pbit : portbits) {
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if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && visited_cells.count(pbit.cell) == 0) {
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if ((pbit.cell->type == TW($mux) || pbit.cell->type == TW($pmux)) && visited_cells.count(pbit.cell) == 0) {
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pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(TW::S)).to_sigbit_pool();
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terminal_bits.insert(bits.begin(), bits.end());
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queue_bits.insert(bits.begin(), bits.end());
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visited_cells.insert(pbit.cell);
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}
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if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
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if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type_impl) && visited_cells.count(pbit.cell) == 0) {
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pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
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terminal_bits.insert(bits.begin(), bits.end());
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queue_bits.insert(bits.begin(), bits.end());
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@ -351,7 +351,7 @@ struct ShareWorker
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{
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for (auto cell : module->cells())
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{
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if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type))
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if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type_impl))
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continue;
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for (auto &bit : modwalker.cell_outputs[cell])
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@ -362,7 +362,7 @@ struct ShareWorker
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not_a_muxed_cell:
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continue;
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if (cell->type.in(ID($memrd), ID($memrd_v2))) {
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if (cell->type.in(TW($memrd), TW($memrd_v2))) {
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if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
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continue;
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if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(TW::ADDR)).is_fully_const())
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@ -370,19 +370,19 @@ struct ShareWorker
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continue;
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}
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if (cell->type.in(ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
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if (cell->type.in(TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor))) {
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if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4)
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
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if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr))) {
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if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 8)
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shareable_cells.insert(cell);
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continue;
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}
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if (generic_ops(cell->type)) {
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if (generic_ops(cell->type_impl)) {
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if (config.opt_aggressive)
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shareable_cells.insert(cell);
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continue;
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@ -395,7 +395,7 @@ struct ShareWorker
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if (c1->type != c2->type)
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return false;
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if (c1->type.in(ID($memrd), ID($memrd_v2)))
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if (c1->type.in(TW($memrd), TW($memrd_v2)))
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{
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if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string())
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return false;
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@ -406,7 +406,7 @@ struct ShareWorker
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return true;
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}
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if (config.generic_uni_ops(c1->type))
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if (config.generic_uni_ops(c1->type_impl))
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{
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if (!config.opt_aggressive)
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{
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@ -423,7 +423,7 @@ struct ShareWorker
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return true;
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}
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if (config.generic_bin_ops(c1->type) || c1->type == ID($alu))
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if (config.generic_bin_ops(c1->type_impl) || c1->type == TW($alu))
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{
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if (!config.opt_aggressive)
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{
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@ -443,7 +443,7 @@ struct ShareWorker
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return true;
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}
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if (config.generic_cbin_ops(c1->type))
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if (config.generic_cbin_ops(c1->type_impl))
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{
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if (!config.opt_aggressive)
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{
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@ -469,7 +469,7 @@ struct ShareWorker
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return true;
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}
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if (c1->type == ID($macc))
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if (c1->type == TW($macc))
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{
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if (!config.opt_aggressive)
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if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false;
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@ -505,7 +505,7 @@ struct ShareWorker
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{
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log_assert(c1->type == c2->type);
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if (config.generic_uni_ops(c1->type))
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if (config.generic_uni_ops(c1->type_impl))
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{
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if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
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{
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@ -540,7 +540,7 @@ struct ShareWorker
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RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
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RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
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RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
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supercell->parameters[ID::A_SIGNED] = a_signed;
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supercell->parameters[ID::A_WIDTH] = a_width;
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supercell->parameters[ID::Y_WIDTH] = y_width;
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@ -554,11 +554,11 @@ struct ShareWorker
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return supercell;
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}
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if (config.generic_bin_ops(c1->type) || config.generic_cbin_ops(c1->type) || c1->type == ID($alu))
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if (config.generic_bin_ops(c1->type_impl) || config.generic_cbin_ops(c1->type_impl) || c1->type_impl == TW($alu))
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{
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bool modified_src_cells = false;
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if (config.generic_cbin_ops(c1->type))
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if (config.generic_cbin_ops(c1->type_impl))
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{
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int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
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max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
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@ -616,7 +616,7 @@ struct ShareWorker
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log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
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log_assert(b_signed == c2->parameters.at(ID::B_SIGNED).as_bool());
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if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
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if (c1->type == TW($shl) || c1->type == TW($shr) || c1->type == TW($sshl) || c1->type == TW($sshr))
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b_signed = false;
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RTLIL::SigSpec a1 = c1->getPort(TW::A);
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@ -631,7 +631,7 @@ struct ShareWorker
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int b_width = max(b1.size(), b2.size());
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int y_width = max(y1.size(), y2.size());
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if (c1->type == ID($shr) && a_signed)
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if (c1->type == TW($shr) && a_signed)
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{
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a_width = max(y_width, a_width);
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@ -657,10 +657,10 @@ struct ShareWorker
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supercell_aux.insert(module->addMux(NEW_TWINE, b2, b1, act, b));
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RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
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RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
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RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
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RTLIL::Wire *x = c1->type == TW($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
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RTLIL::Wire *co = c1->type == TW($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
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RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
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RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
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supercell->parameters[ID::A_SIGNED] = a_signed;
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supercell->parameters[ID::B_SIGNED] = b_signed;
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supercell->parameters[ID::A_WIDTH] = a_width;
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@ -669,7 +669,7 @@ struct ShareWorker
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supercell->setPort(TW::A, a);
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supercell->setPort(TW::B, b);
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supercell->setPort(TW::Y, y);
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if (c1->type == ID($alu)) {
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if (c1->type == TW($alu)) {
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RTLIL::Wire *ci = module->addWire(NEW_TWINE), *bi = module->addWire(NEW_TWINE);
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supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci));
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supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi));
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@ -682,7 +682,7 @@ struct ShareWorker
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supercell_aux.insert(module->addPos(NEW_TWINE, y, y1));
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supercell_aux.insert(module->addPos(NEW_TWINE, y, y2));
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if (c1->type == ID($alu)) {
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if (c1->type == TW($alu)) {
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supercell_aux.insert(module->addPos(NEW_TWINE, co, c1->getPort(TW::CO)));
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supercell_aux.insert(module->addPos(NEW_TWINE, co, c2->getPort(TW::CO)));
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supercell_aux.insert(module->addPos(NEW_TWINE, x, c1->getPort(TW::X)));
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@ -693,16 +693,16 @@ struct ShareWorker
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return supercell;
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}
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if (c1->type == ID($macc))
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if (c1->type == TW($macc))
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{
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RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
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RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type_impl);
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supercell_aux.insert(supercell);
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share_macc(c1, c2, act, supercell, &supercell_aux);
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supercell->check();
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return supercell;
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}
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if (c1->type.in(ID($memrd), ID($memrd_v2)))
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if (c1->type.in(TW($memrd), TW($memrd_v2)))
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{
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RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1);
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RTLIL::SigSpec addr1 = c1->getPort(TW::ADDR);
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@ -744,7 +744,7 @@ struct ShareWorker
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modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
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for (auto &bit : pbits) {
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if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == TW::S)
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if ((bit.cell->type == TW($mux) || bit.cell->type == TW($pmux)) && bit.port == TW::S)
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forbidden_controls_cache[cell].insert(bit.cell->getPort(TW::S).extract(bit.offset, 1));
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consumer_cells.insert(bit.cell);
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}
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@ -752,7 +752,7 @@ struct ShareWorker
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recursion_state.insert(cell);
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for (auto c : consumer_cells)
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if (StaticCellTypes::Compat::internals_nomem_noff(c->type)) {
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if (StaticCellTypes::Compat::internals_nomem_noff(c->type_impl)) {
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const pool<RTLIL::SigBit> &bits = find_forbidden_controls(c);
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forbidden_controls_cache[cell].insert(bits.begin(), bits.end());
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}
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@ -891,8 +891,8 @@ struct ShareWorker
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return activation_patterns_cache.at(cell);
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}
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for (auto &pbit : modwalker.signal_consumers[bit]) {
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log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type));
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if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == TW::A || pbit.port == TW::B))
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log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type_impl));
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if ((pbit.cell->type == TW($mux) || pbit.cell->type == TW($pmux)) && (pbit.port == TW::A || pbit.port == TW::B))
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driven_data_muxes.insert(pbit.cell);
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else
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driven_cells.insert(pbit.cell);
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@ -1095,9 +1095,9 @@ struct ShareWorker
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dict<RTLIL::SigBit, pool<RTLIL::Cell*>> bit_to_cells;
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for (auto cell : module->cells())
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if (ct.cell_known(cell->type))
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if (ct.cell_known(cell->type_impl))
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for (auto &conn : cell->connections()) {
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if (ct.cell_output(cell->type, conn.first))
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if (ct.cell_output(cell->type_impl, conn.first))
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for (auto bit : topo_sigmap(conn.second)) {
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cell_to_bits[cell].insert(bit);
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topo_bit_drivers[bit].insert(cell);
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@ -1123,7 +1123,7 @@ struct ShareWorker
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for (auto &loop : toposort.loops) {
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log("### loop ###\n");
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for (auto &c : loop)
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log("%s (%s)\n", c, c->type.unescape());
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log("%s (%s)\n", c, design->twines.unescaped_str(c->type));
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}
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return found_scc;
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@ -1167,13 +1167,13 @@ struct ShareWorker
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pool<RTLIL::Cell*> new_queue;
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for (auto c : queue) {
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if (!ct.cell_known(c->type))
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if (!ct.cell_known(c->type_impl))
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continue;
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for (auto &conn : c->connections())
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if (ct.cell_input(c->type, conn.first))
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if (ct.cell_input(c->type_impl, conn.first))
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for (auto bit : conn.second)
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for (auto &pi : mi.query_ports(bit))
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if (ct.cell_known(pi.cell->type) && ct.cell_output(pi.cell->type, pi.port))
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if (ct.cell_known(pi.cell->type_impl) && ct.cell_output(pi.cell->type_impl, pi.port))
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new_queue.insert(pi.cell);
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covered.insert(c);
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}
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@ -1247,7 +1247,7 @@ struct ShareWorker
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RTLIL::Cell *cell = *shareable_cells.begin();
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shareable_cells.erase(cell);
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log(" Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescape());
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log(" Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescaped());
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const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, " ");
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RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
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@ -1280,7 +1280,7 @@ struct ShareWorker
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for (auto other_cell : candidates)
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{
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log(" Analyzing resource sharing with %s (%s):\n", other_cell, other_cell->type.unescape());
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log(" Analyzing resource sharing with %s (%s):\n", other_cell, design->twines.unescaped_str(other_cell->type));
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const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " ");
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RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
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@ -1431,7 +1431,7 @@ struct ShareWorker
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log(" Activation signal for %s: %s\n", other_cell, log_signal(act));
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}
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log(" New cell: %s (%s)\n", supercell, supercell->type.unescape());
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log(" New cell: %s (%s)\n", supercell, design->twines.unescaped_str(supercell->type));
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cells_to_remove.insert(cell);
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cells_to_remove.insert(other_cell);
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@ -1478,7 +1478,7 @@ struct ShareWorker
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if (!cells_to_remove.empty()) {
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log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), module);
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for (auto c : cells_to_remove) {
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log(" Removing cell %s (%s).\n", c, c->type.unescape());
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log(" Removing cell %s (%s).\n", c, design->twines.unescaped_str(c->type));
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remove_cell(c);
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}
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}
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@ -1532,45 +1532,45 @@ struct SharePass : public Pass {
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config.opt_aggressive = false;
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config.opt_fast = false;
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config.generic_uni_ops.set_id(ID($not));
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// config.generic_uni_ops.set_id(ID($pos));
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config.generic_uni_ops.set_id(ID($neg));
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config.generic_uni_ops.set_id(TW($not));
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// config.generic_uni_ops.set_id(TW($pos));
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config.generic_uni_ops.set_id(TW($neg));
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config.generic_cbin_ops.set_id(ID($and));
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config.generic_cbin_ops.set_id(ID($or));
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config.generic_cbin_ops.set_id(ID($xor));
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config.generic_cbin_ops.set_id(ID($xnor));
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config.generic_cbin_ops.set_id(TW($and));
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config.generic_cbin_ops.set_id(TW($or));
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config.generic_cbin_ops.set_id(TW($xor));
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config.generic_cbin_ops.set_id(TW($xnor));
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config.generic_bin_ops.set_id(ID($shl));
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config.generic_bin_ops.set_id(ID($shr));
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config.generic_bin_ops.set_id(ID($sshl));
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config.generic_bin_ops.set_id(ID($sshr));
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config.generic_bin_ops.set_id(TW($shl));
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config.generic_bin_ops.set_id(TW($shr));
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config.generic_bin_ops.set_id(TW($sshl));
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config.generic_bin_ops.set_id(TW($sshr));
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|
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config.generic_bin_ops.set_id(ID($lt));
|
||||
config.generic_bin_ops.set_id(ID($le));
|
||||
config.generic_bin_ops.set_id(ID($eq));
|
||||
config.generic_bin_ops.set_id(ID($ne));
|
||||
config.generic_bin_ops.set_id(ID($eqx));
|
||||
config.generic_bin_ops.set_id(ID($nex));
|
||||
config.generic_bin_ops.set_id(ID($ge));
|
||||
config.generic_bin_ops.set_id(ID($gt));
|
||||
config.generic_bin_ops.set_id(TW($lt));
|
||||
config.generic_bin_ops.set_id(TW($le));
|
||||
config.generic_bin_ops.set_id(TW($eq));
|
||||
config.generic_bin_ops.set_id(TW($ne));
|
||||
config.generic_bin_ops.set_id(TW($eqx));
|
||||
config.generic_bin_ops.set_id(TW($nex));
|
||||
config.generic_bin_ops.set_id(TW($ge));
|
||||
config.generic_bin_ops.set_id(TW($gt));
|
||||
|
||||
config.generic_cbin_ops.set_id(ID($add));
|
||||
config.generic_cbin_ops.set_id(ID($mul));
|
||||
config.generic_cbin_ops.set_id(TW($add));
|
||||
config.generic_cbin_ops.set_id(TW($mul));
|
||||
|
||||
config.generic_bin_ops.set_id(ID($sub));
|
||||
config.generic_bin_ops.set_id(ID($div));
|
||||
config.generic_bin_ops.set_id(ID($mod));
|
||||
config.generic_bin_ops.set_id(ID($divfloor));
|
||||
config.generic_bin_ops.set_id(ID($modfloor));
|
||||
// config.generic_bin_ops.set_id(ID($pow));
|
||||
config.generic_bin_ops.set_id(TW($sub));
|
||||
config.generic_bin_ops.set_id(TW($div));
|
||||
config.generic_bin_ops.set_id(TW($mod));
|
||||
config.generic_bin_ops.set_id(TW($divfloor));
|
||||
config.generic_bin_ops.set_id(TW($modfloor));
|
||||
// config.generic_bin_ops.set_id(TW($pow));
|
||||
|
||||
config.generic_uni_ops.set_id(ID($logic_not));
|
||||
config.generic_cbin_ops.set_id(ID($logic_and));
|
||||
config.generic_cbin_ops.set_id(ID($logic_or));
|
||||
config.generic_uni_ops.set_id(TW($logic_not));
|
||||
config.generic_cbin_ops.set_id(TW($logic_and));
|
||||
config.generic_cbin_ops.set_id(TW($logic_or));
|
||||
|
||||
config.generic_other_ops.set_id(ID($alu));
|
||||
config.generic_other_ops.set_id(ID($macc));
|
||||
config.generic_other_ops.set_id(TW($alu));
|
||||
config.generic_other_ops.set_id(TW($macc));
|
||||
|
||||
log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue