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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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38
passes/opt/opt_reduce.cc
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@ -50,7 +50,7 @@ struct OptReduceWorker
for (auto &bit : sig_a)
{
if (bit == RTLIL::State::S0) {
if (cell->type == ID($reduce_and)) {
if (cell->type == TW($reduce_and)) {
new_sig_a_bits.clear();
new_sig_a_bits.insert(RTLIL::State::S0);
break;
@ -58,7 +58,7 @@ struct OptReduceWorker
continue;
}
if (bit == RTLIL::State::S1) {
if (cell->type == ID($reduce_or)) {
if (cell->type == TW($reduce_or)) {
new_sig_a_bits.clear();
new_sig_a_bits.insert(RTLIL::State::S1);
break;
@ -90,7 +90,7 @@ struct OptReduceWorker
new_sig_a.sort_and_unify();
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
new_sig_a = (cell->type == TW($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(TW::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
@ -126,7 +126,7 @@ struct OptReduceWorker
RTLIL::SigSpec this_s{this_s_bit};
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, TW($reduce_or));
reduce_or_cell->setPort(TW::A, this_s);
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
@ -151,7 +151,7 @@ struct OptReduceWorker
return;
}
if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {
if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == TW($pmux))) {
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
@ -338,7 +338,7 @@ struct OptReduceWorker
SigSpec sig_y = assign_map(cell->getPort(TW::Y));
int width = GetSize(sig_y);
if (cell->type != ID($bmux))
if (cell->type != TW($bmux))
sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSig old_sig_conn;
@ -386,7 +386,7 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
if (cell->type != ID($bmux)) {
if (cell->type != TW($bmux)) {
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
} else {
@ -403,7 +403,7 @@ struct OptReduceWorker
new_sig_a.append(sig_a[i+j]);
cell->setPort(TW::A, new_sig_a);
if (cell->type != ID($bmux)) {
if (cell->type != TW($bmux)) {
SigSpec new_sig_b;
for (int i = 0; i < GetSize(sig_b); i += width)
for (int j: swizzle)
@ -418,7 +418,7 @@ struct OptReduceWorker
cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
if (cell->type != ID($bmux)) {
if (cell->type != TW($bmux)) {
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
} else {
@ -520,14 +520,14 @@ struct OptReduceWorker
SigPool mem_wren_sigs;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type.in(ID($mem), ID($mem_v2)))
if (cell->type.in(TW($mem), TW($mem_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(TW::WR_EN)));
if (cell->type.in(ID($memwr), ID($memwr_v2)))
if (cell->type.in(TW($memwr), TW($memwr_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(TW::EN)));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
if (cell->type == TW($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
mem_wren_sigs.add(assign_map(cell->getPort(TW::D)));
}
@ -536,7 +536,7 @@ struct OptReduceWorker
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
if (cell->type == TW($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
if (!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::A))) ||
!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::B))))
keep_expanding_mem_wren_sigs = true;
@ -553,7 +553,7 @@ struct OptReduceWorker
// merge trees of reduce_* cells to one single cell and unify input vectors
// (only handle reduce_and and reduce_or for various reasons)
const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
const IdString type_list[] = { TW($reduce_or), TW($reduce_and) };
for (auto type : type_list)
{
SigSet<RTLIL::Cell*> drivers;
@ -577,13 +577,13 @@ struct OptReduceWorker
for (auto cell : module->selected_cells())
{
if (!cell->type.in(ID($mux), ID($pmux), ID($bmux), ID($demux)))
if (!cell->type.in(TW($mux), TW($pmux), TW($bmux), TW($demux)))
continue;
// this optimization is to aggressive for most coarse-grain applications.
// but we always want it for multiplexers driving write enable ports.
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
if (cell->type == ID($demux)) {
if (cell->type == TW($demux)) {
if (opt_demux_bits(cell))
continue;
} else {
@ -592,11 +592,11 @@ struct OptReduceWorker
}
}
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->type.in(TW($mux), TW($pmux)))
opt_pmux(cell);
else if (cell->type == ID($bmux))
else if (cell->type == TW($bmux))
opt_bmux(cell);
else if (cell->type == ID($demux))
else if (cell->type == TW($demux))
opt_demux(cell);
}
}