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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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8
passes/opt/opt_mem_feedback.cc
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@ -163,7 +163,7 @@ struct OptMemFeedbackWorker
{
auto &port = mem.wr_ports[i];
log(" Analyzing %s.%s write port %d.\n", module, mem.memid.unescape(), i);
log(" Analyzing %s.%s write port %d.\n", module, design->twines.unescaped_str(mem.memid), i);
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
@ -232,7 +232,7 @@ struct OptMemFeedbackWorker
// Okay, let's do it.
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, mem.memid.unescape());
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, design->twines.unescaped_str(mem.memid));
// If a write port has a feedback path that we're about to bypass,
// but also has priority over some other write port, the feedback
@ -293,7 +293,7 @@ struct OptMemFeedbackWorker
for (auto cell : module->cells())
{
if (cell->type == ID($mux))
if (cell->type == TW($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
@ -304,7 +304,7 @@ struct OptMemFeedbackWorker
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->type.in(TW($mux), TW($pmux)))
{
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < int(sig_y.size()); i++)