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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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46
passes/opt/opt_dff.cc
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@ -123,7 +123,7 @@ struct OptDffWorker
bitusers[bit]++;
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
if (cell->type.in(TW($mux), TW($pmux), TW($_MUX_))) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
@ -302,7 +302,7 @@ struct OptDffWorker
initvals.remove_init(ff.sig_q[i]);
module->connect(ff.sig_q[i], State::S0);
log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n",
i, cell, cell->type.unescape(), module);
i, cell, cell->type.unescaped(), module);
sr_removed = true;
} else if (is_always_active(ff.sig_set[i], ff.pol_set)) {
initvals.remove_init(ff.sig_q[i]);
@ -313,7 +313,7 @@ struct OptDffWorker
else
module->addNot(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, cell, cell->type.unescape(), module);
i, cell, cell->type.unescaped(), module);
sr_removed = true;
} else {
keep_bits.push_back(i);
@ -336,7 +336,7 @@ struct OptDffWorker
if (clr_inactive && signal_all_same(ff.sig_set)) {
log("Removing never-active CLR on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_set;
@ -345,7 +345,7 @@ struct OptDffWorker
changed = true;
} else if (set_inactive && signal_all_same(ff.sig_clr)) {
log("Removing never-active SET on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_clr;
@ -371,7 +371,7 @@ struct OptDffWorker
if (!failed) {
log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.val_arst = val_arst_builder.build();
@ -390,7 +390,7 @@ struct OptDffWorker
// Converts constant Async Load to ARST
if (is_always_inactive(ff.sig_aload, ff.pol_aload)) {
log("Removing never-active async load on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_aload = false;
changed = true;
return false;
@ -399,7 +399,7 @@ struct OptDffWorker
if (is_active(ff.sig_aload, ff.pol_aload)) {
// ALOAD always active
log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.remove();
if (ff.has_sr) {
@ -434,7 +434,7 @@ struct OptDffWorker
// AD is constant -> ARST
if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {
log("Changing const-value async load to async reset on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_arst = true;
ff.has_aload = false;
ff.sig_arst = ff.sig_aload;
@ -451,12 +451,12 @@ struct OptDffWorker
// Removes ARST if never active or replaces FF if always active
if (is_inactive(ff.sig_arst, ff.pol_arst)) {
log("Removing never-active ARST on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_arst = false;
changed = true;
} else if (is_always_active(ff.sig_arst, ff.pol_arst)) {
log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.remove();
module->connect(ff.sig_q, ff.val_arst);
return true;
@ -470,12 +470,12 @@ struct OptDffWorker
// Removes SRST if never active or forces D to reset value if always active
if (is_inactive(ff.sig_srst, ff.pol_srst)) {
log("Removing never-active SRST on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_srst = false;
changed = true;
} else if (is_always_active(ff.sig_srst, ff.pol_srst)) {
log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_srst = false;
if (!ff.ce_over_srst)
ff.has_ce = false;
@ -490,7 +490,7 @@ struct OptDffWorker
if (is_always_inactive(ff.sig_ce, ff.pol_ce)) {
if (ff.has_srst && !ff.ce_over_srst) {
log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.pol_ce = ff.pol_srst;
ff.sig_ce = ff.sig_srst;
ff.has_srst = false;
@ -498,7 +498,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else {
@ -508,7 +508,7 @@ struct OptDffWorker
}
} else if (is_active(ff.sig_ce, ff.pol_ce)) {
log("Removing always-active EN on %s (%s) from module %s.\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_ce = false;
changed = true;
}
@ -518,7 +518,7 @@ struct OptDffWorker
{
if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) {
@ -533,7 +533,7 @@ struct OptDffWorker
// Detect feedback loops where D is hardwired to Q
if (ff.has_clk && ff.has_srst) {
log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
if (ff.has_ce && ff.ce_over_srst) {
SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine);
SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine);
@ -550,7 +550,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_gclk = ff.has_clk = ff.has_ce = false;
changed = true;
}
@ -623,7 +623,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n",
cell, cell->type.unescape(), module,
cell, cell->type.unescaped(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst));
}
@ -693,7 +693,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n",
cell, cell->type.unescape(), module,
cell, cell->type.unescaped(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q));
}
@ -760,7 +760,7 @@ struct OptDffWorker
if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",
cell, cell->type.unescape(), module);
cell, cell->type.unescaped(), module);
ff.has_aload = false;
changed = true;
}
@ -878,7 +878,7 @@ struct OptDffWorker
}
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
val ? 1 : 0, i, cell, cell->type.unescape(), module);
val ? 1 : 0, i, cell, cell->type.unescaped(), module);
// Replace the Q output with the constant value
initvals.remove_init(ff.sig_q[i]);